Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 9264307 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 16980437 1 T16 289 T109 251 T110 178



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 8074241 1 T16 92 T109 94 T110 61
values[0x0] 6917452 1 T16 97 T109 100 T110 58
values[0x1] 11253051 1 T16 101 T109 58 T110 82



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 4804213 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 21440531 1 T16 290 T109 252 T110 187



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 101439 1 T16 2 T110 2 T181 1
valid_sources[0x01] 106585 1 T16 1 T110 2 T183 3
valid_sources[0x02] 101847 1 T16 3 T109 1 T183 3
valid_sources[0x03] 97024 1 T16 1 T110 3 T111 1
valid_sources[0x04] 100418 1 T115 3 T248 1 T249 2
valid_sources[0x05] 103163 1 T110 1 T111 1 T183 3
valid_sources[0x06] 103215 1 T16 5 T115 9 T297 1
valid_sources[0x07] 97162 1 T110 5 T114 3 T183 4
valid_sources[0x08] 97602 1 T16 1 T115 14 T247 2
valid_sources[0x09] 97505 1 T16 1 T110 2 T181 1
valid_sources[0x0a] 104068 1 T16 2 T110 1 T217 1
valid_sources[0x0b] 97422 1 T248 2 T211 8 T187 2
valid_sources[0x0c] 98132 1 T16 4 T109 6 T183 3
valid_sources[0x0d] 95184 1 T16 2 T109 10 T111 1
valid_sources[0x0e] 95622 1 T16 2 T181 1 T182 1
valid_sources[0x0f] 100380 1 T16 4 T183 1 T248 1
valid_sources[0x10] 103450 1 T183 1 T115 1 T248 3
valid_sources[0x11] 115036 1 T16 2 T109 5 T111 1
valid_sources[0x12] 101235 1 T16 1 T115 7 T284 1
valid_sources[0x13] 95890 1 T109 20 T115 2 T248 2
valid_sources[0x14] 166991 1 T110 1 T183 3 T248 4
valid_sources[0x15] 98245 1 T183 3 T248 3 T211 9
valid_sources[0x16] 97352 1 T110 2 T112 2 T193 1
valid_sources[0x17] 100945 1 T16 1 T181 1 T182 1
valid_sources[0x18] 101416 1 T16 3 T110 1 T114 1
valid_sources[0x19] 98847 1 T112 1 T193 1 T184 2
valid_sources[0x1a] 98806 1 T16 2 T109 21 T182 1
valid_sources[0x1b] 100656 1 T16 1 T110 2 T183 5
valid_sources[0x1c] 102745 1 T16 4 T109 1 T114 1
valid_sources[0x1d] 102188 1 T16 1 T248 1 T249 1
valid_sources[0x1e] 95944 1 T16 2 T112 1 T248 3
valid_sources[0x1f] 108510 1 T110 3 T112 1 T181 1
valid_sources[0x20] 105980 1 T181 1 T249 1 T211 12
valid_sources[0x21] 103479 1 T112 1 T183 1 T115 14
valid_sources[0x22] 99820 1 T16 4 T109 2 T181 2
valid_sources[0x23] 102390 1 T109 13 T110 1 T183 1
valid_sources[0x24] 99179 1 T247 1 T248 3 T386 1
valid_sources[0x25] 100882 1 T112 1 T115 5 T193 1
valid_sources[0x26] 101836 1 T16 2 T115 10 T248 3
valid_sources[0x27] 99146 1 T16 5 T109 4 T112 1
valid_sources[0x28] 102633 1 T111 1 T183 3 T115 8
valid_sources[0x29] 101446 1 T183 7 T247 1 T248 3
valid_sources[0x2a] 99445 1 T16 1 T115 3 T248 1
valid_sources[0x2b] 102327 1 T16 4 T111 1 T112 1
valid_sources[0x2c] 95618 1 T112 1 T183 1 T210 74
valid_sources[0x2d] 103492 1 T16 1 T111 1 T183 1
valid_sources[0x2e] 101720 1 T16 1 T114 1 T111 1
valid_sources[0x2f] 101820 1 T16 4 T115 1 T248 1
valid_sources[0x30] 103317 1 T183 5 T115 3 T210 61
valid_sources[0x31] 103059 1 T16 1 T109 4 T110 1
valid_sources[0x32] 104030 1 T114 5 T115 8 T247 10
valid_sources[0x33] 101202 1 T16 1 T181 1 T210 28
valid_sources[0x34] 100322 1 T114 1 T248 2 T249 1
valid_sources[0x35] 97586 1 T16 4 T183 3 T115 5
valid_sources[0x36] 97097 1 T16 1 T109 23 T111 1
valid_sources[0x37] 102890 1 T110 3 T115 5 T248 1
valid_sources[0x38] 99451 1 T110 1 T183 1 T115 1
valid_sources[0x39] 102113 1 T16 1 T110 2 T112 1
valid_sources[0x3a] 101173 1 T16 1 T114 3 T248 3
valid_sources[0x3b] 100221 1 T16 2 T110 3 T181 2
valid_sources[0x3c] 103779 1 T16 3 T110 1 T112 1
valid_sources[0x3d] 97180 1 T16 3 T110 2 T183 1
valid_sources[0x3e] 98127 1 T16 1 T109 4 T183 3
valid_sources[0x3f] 99306 1 T16 1 T110 1 T183 1
valid_sources[0x40] 96915 1 T16 2 T114 1 T211 2
valid_sources[0x41] 97234 1 T16 2 T181 1 T193 1
valid_sources[0x42] 109251 1 T183 1 T115 1 T248 1
valid_sources[0x43] 101257 1 T16 1 T110 3 T111 1
valid_sources[0x44] 100038 1 T16 1 T183 3 T248 2
valid_sources[0x45] 97616 1 T16 1 T115 3 T210 20
valid_sources[0x46] 140130 1 T16 3 T181 1 T183 1
valid_sources[0x47] 98752 1 T183 7 T115 1 T248 1
valid_sources[0x48] 104671 1 T111 1 T183 3 T211 4
valid_sources[0x49] 103281 1 T111 1 T115 8 T116 1
valid_sources[0x4a] 100020 1 T16 1 T183 2 T115 1
valid_sources[0x4b] 98412 1 T16 1 T110 11 T181 1
valid_sources[0x4c] 111543 1 T110 3 T114 2 T112 1
valid_sources[0x4d] 103904 1 T16 1 T109 4 T115 5
valid_sources[0x4e] 96557 1 T248 3 T249 1 T211 7
valid_sources[0x4f] 100828 1 T16 3 T110 1 T193 1
valid_sources[0x50] 99787 1 T110 3 T114 6 T211 10
valid_sources[0x51] 102269 1 T16 1 T211 3 T186 4
valid_sources[0x52] 100543 1 T16 2 T110 1 T248 4
valid_sources[0x53] 109465 1 T16 1 T115 2 T193 1
valid_sources[0x54] 110981 1 T111 1 T248 4 T297 2
valid_sources[0x55] 101820 1 T16 1 T110 2 T183 1
valid_sources[0x56] 102068 1 T112 1 T183 2 T248 1
valid_sources[0x57] 96137 1 T110 1 T182 1 T115 3
valid_sources[0x58] 100349 1 T16 1 T183 4 T115 2
valid_sources[0x59] 99058 1 T110 1 T114 2 T112 1
valid_sources[0x5a] 98865 1 T16 1 T110 4 T211 13
valid_sources[0x5b] 99702 1 T16 2 T111 2 T182 1
valid_sources[0x5c] 106520 1 T112 1 T284 1 T248 6
valid_sources[0x5d] 156864 1 T114 3 T111 4 T181 3
valid_sources[0x5e] 99019 1 T110 1 T114 1 T249 1
valid_sources[0x5f] 111740 1 T16 3 T110 3 T248 1
valid_sources[0x60] 98085 1 T16 2 T115 4 T248 4
valid_sources[0x61] 101837 1 T16 7 T110 1 T115 2
valid_sources[0x62] 99440 1 T16 1 T183 4 T284 2
valid_sources[0x63] 99767 1 T16 2 T110 5 T283 1
valid_sources[0x64] 95834 1 T16 1 T110 2 T210 121
valid_sources[0x65] 100813 1 T112 1 T248 2 T297 1
valid_sources[0x66] 105091 1 T110 2 T183 1 T248 3
valid_sources[0x67] 100540 1 T16 2 T182 1 T248 4
valid_sources[0x68] 99932 1 T16 1 T110 4 T111 1
valid_sources[0x69] 98054 1 T16 1 T110 2 T115 2
valid_sources[0x6a] 109059 1 T16 2 T248 3 T211 6
valid_sources[0x6b] 127382 1 T115 1 T248 2 T185 5
valid_sources[0x6c] 102201 1 T16 1 T114 1 T112 1
valid_sources[0x6d] 100408 1 T112 1 T181 1 T217 1
valid_sources[0x6e] 100949 1 T210 12 T253 1 T241 2
valid_sources[0x6f] 102865 1 T109 2 T183 3 T115 8
valid_sources[0x70] 105351 1 T109 4 T183 4 T115 1
valid_sources[0x71] 101820 1 T16 1 T182 2 T115 1
valid_sources[0x72] 103717 1 T16 4 T111 1 T183 2
valid_sources[0x73] 101253 1 T16 3 T109 10 T114 2
valid_sources[0x74] 103413 1 T114 8 T113 40 T248 1
valid_sources[0x75] 101237 1 T16 2 T183 1 T115 3
valid_sources[0x76] 101200 1 T16 1 T110 4 T115 15
valid_sources[0x77] 99673 1 T16 1 T115 1 T193 1
valid_sources[0x78] 97210 1 T16 1 T248 2 T249 1
valid_sources[0x79] 101260 1 T16 2 T115 3 T248 1
valid_sources[0x7a] 101430 1 T16 1 T110 4 T183 3
valid_sources[0x7b] 99264 1 T16 1 T183 3 T115 1
valid_sources[0x7c] 98317 1 T183 1 T115 1 T193 3
valid_sources[0x7d] 102243 1 T183 1 T284 1 T248 2
valid_sources[0x7e] 103783 1 T16 2 T248 1 T186 1
valid_sources[0x7f] 100963 1 T110 6 T183 1 T248 4
valid_sources[0x80] 101431 1 T110 4 T181 1 T115 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 4652569 1 T16 91 T109 93 T110 45
values[0x0] all_enables biggest_size 6203039 1 T16 97 T109 100 T110 56
values[0x1] all_enables biggest_size 6124829 1 T16 101 T109 58 T110 77


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 867262 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 31769332 1 T16 99 T109 77 T110 75



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 7995992 1 T16 55 T109 42 T110 42
values[0x0] 11952323 1 T16 18 T109 21 T110 30
values[0x1] 12688279 1 T16 26 T109 14 T110 29



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 297807 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 32338787 1 T16 99 T109 77 T110 85



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 129517 1 T110 1 T115 4 T210 1
valid_sources[0x01] 125006 1 T115 1 T210 9 T248 2
valid_sources[0x02] 125759 1 T115 1 T210 7 T211 1
valid_sources[0x03] 128471 1 T115 1 T210 11 T211 5
valid_sources[0x04] 125585 1 T110 2 T115 2 T210 9
valid_sources[0x05] 126807 1 T114 1 T115 1 T210 8
valid_sources[0x06] 124397 1 T183 1 T115 2 T210 7
valid_sources[0x07] 124168 1 T183 1 T210 3 T185 1
valid_sources[0x08] 127613 1 T114 1 T210 3 T248 1
valid_sources[0x09] 124734 1 T110 1 T115 2 T210 9
valid_sources[0x0a] 126196 1 T115 2 T210 7 T211 3
valid_sources[0x0b] 128570 1 T110 1 T183 1 T210 7
valid_sources[0x0c] 127832 1 T183 1 T115 1 T210 6
valid_sources[0x0d] 124432 1 T109 1 T115 1 T210 5
valid_sources[0x0e] 123470 1 T114 3 T183 1 T115 1
valid_sources[0x0f] 127889 1 T110 1 T115 3 T210 10
valid_sources[0x10] 128845 1 T109 1 T114 2 T183 3
valid_sources[0x11] 129506 1 T114 1 T115 3 T210 10
valid_sources[0x12] 124717 1 T109 1 T114 2 T183 1
valid_sources[0x13] 126591 1 T114 2 T183 1 T115 3
valid_sources[0x14] 129908 1 T110 1 T114 1 T183 1
valid_sources[0x15] 126490 1 T109 1 T114 2 T210 8
valid_sources[0x16] 129494 1 T115 1 T210 10 T211 7
valid_sources[0x17] 125887 1 T183 1 T115 2 T210 5
valid_sources[0x18] 123743 1 T109 1 T183 1 T115 1
valid_sources[0x19] 128726 1 T210 11 T184 2 T185 1
valid_sources[0x1a] 124853 1 T109 2 T110 1 T114 1
valid_sources[0x1b] 125499 1 T115 3 T210 11 T248 2
valid_sources[0x1c] 131522 1 T110 1 T183 1 T210 12
valid_sources[0x1d] 125351 1 T115 2 T210 13 T211 4
valid_sources[0x1e] 127483 1 T210 5 T185 11 T211 4
valid_sources[0x1f] 129532 1 T183 3 T210 14 T248 1
valid_sources[0x20] 126278 1 T183 1 T115 3 T210 5
valid_sources[0x21] 125453 1 T114 1 T115 2 T210 5
valid_sources[0x22] 130984 1 T115 2 T210 12 T184 1
valid_sources[0x23] 126649 1 T110 2 T210 8 T249 4
valid_sources[0x24] 123251 1 T110 2 T114 3 T115 2
valid_sources[0x25] 128976 1 T109 2 T183 1 T210 6
valid_sources[0x26] 127448 1 T114 1 T115 2 T210 15
valid_sources[0x27] 132280 1 T114 1 T115 1 T210 6
valid_sources[0x28] 125865 1 T115 1 T210 10 T248 2
valid_sources[0x29] 124621 1 T115 1 T210 8 T211 2
valid_sources[0x2a] 125559 1 T210 6 T248 1 T185 2
valid_sources[0x2b] 125285 1 T114 1 T210 14 T248 3
valid_sources[0x2c] 127677 1 T115 1 T210 9 T211 4
valid_sources[0x2d] 130821 1 T115 1 T210 11 T211 1
valid_sources[0x2e] 126346 1 T16 9 T115 2 T210 9
valid_sources[0x2f] 131423 1 T115 1 T210 10 T248 1
valid_sources[0x30] 130102 1 T183 1 T115 1 T210 8
valid_sources[0x31] 130519 1 T110 1 T115 1 T210 8
valid_sources[0x32] 128647 1 T210 16 T211 1 T255 1
valid_sources[0x33] 125836 1 T109 1 T114 1 T183 1
valid_sources[0x34] 128678 1 T115 1 T210 7 T211 3
valid_sources[0x35] 128065 1 T110 2 T115 1 T210 8
valid_sources[0x36] 129324 1 T115 1 T210 15 T248 1
valid_sources[0x37] 123278 1 T210 11 T211 5 T217 60
valid_sources[0x38] 127345 1 T109 1 T114 3 T210 6
valid_sources[0x39] 128219 1 T115 1 T210 6 T211 5
valid_sources[0x3a] 130398 1 T210 7 T184 1 T211 6
valid_sources[0x3b] 129735 1 T183 1 T115 2 T210 9
valid_sources[0x3c] 127286 1 T183 2 T210 5 T248 3
valid_sources[0x3d] 122375 1 T115 1 T210 4 T211 3
valid_sources[0x3e] 128511 1 T109 1 T110 1 T183 2
valid_sources[0x3f] 127684 1 T110 1 T114 1 T210 4
valid_sources[0x40] 129943 1 T210 10 T248 1 T211 2
valid_sources[0x41] 129120 1 T115 1 T210 5 T248 1
valid_sources[0x42] 125932 1 T210 13 T211 2 T186 2
valid_sources[0x43] 127988 1 T110 1 T183 1 T115 5
valid_sources[0x44] 125617 1 T183 1 T115 2 T210 8
valid_sources[0x45] 130236 1 T115 2 T210 5 T248 3
valid_sources[0x46] 127889 1 T109 1 T110 1 T183 1
valid_sources[0x47] 129081 1 T115 1 T210 8 T248 1
valid_sources[0x48] 129919 1 T210 3 T211 2 T250 1
valid_sources[0x49] 128629 1 T115 1 T210 5 T184 2
valid_sources[0x4a] 124911 1 T115 4 T210 9 T248 1
valid_sources[0x4b] 128849 1 T183 1 T115 1 T210 11
valid_sources[0x4c] 126922 1 T115 1 T210 8 T248 1
valid_sources[0x4d] 128730 1 T183 1 T115 2 T210 7
valid_sources[0x4e] 129093 1 T110 1 T210 9 T116 8
valid_sources[0x4f] 123688 1 T110 1 T114 2 T115 1
valid_sources[0x50] 124875 1 T114 4 T115 3 T210 7
valid_sources[0x51] 125796 1 T110 1 T210 10 T184 1
valid_sources[0x52] 129916 1 T110 1 T115 1 T210 6
valid_sources[0x53] 129400 1 T115 1 T210 8 T211 5
valid_sources[0x54] 127715 1 T109 2 T110 1 T115 4
valid_sources[0x55] 123239 1 T110 1 T183 2 T115 3
valid_sources[0x56] 126039 1 T109 1 T115 2 T210 8
valid_sources[0x57] 124826 1 T115 1 T210 10 T248 1
valid_sources[0x58] 125792 1 T109 3 T114 1 T115 2
valid_sources[0x59] 126626 1 T109 1 T183 1 T210 9
valid_sources[0x5a] 128539 1 T115 1 T210 6 T186 1
valid_sources[0x5b] 126514 1 T115 1 T210 7 T248 2
valid_sources[0x5c] 126692 1 T183 1 T115 3 T210 5
valid_sources[0x5d] 127888 1 T183 3 T115 2 T210 6
valid_sources[0x5e] 128236 1 T16 6 T114 3 T115 2
valid_sources[0x5f] 128022 1 T110 1 T115 1 T210 13
valid_sources[0x60] 126876 1 T183 2 T115 3 T210 12
valid_sources[0x61] 124372 1 T210 7 T211 5 T256 1
valid_sources[0x62] 123041 1 T110 2 T183 2 T115 2
valid_sources[0x63] 132311 1 T210 11 T211 4 T253 1
valid_sources[0x64] 127064 1 T115 3 T210 5 T248 1
valid_sources[0x65] 133282 1 T114 4 T183 2 T115 2
valid_sources[0x66] 129838 1 T110 1 T115 2 T210 11
valid_sources[0x67] 128608 1 T115 1 T210 12 T248 3
valid_sources[0x68] 126813 1 T115 2 T210 11 T248 1
valid_sources[0x69] 132119 1 T210 10 T248 2 T211 2
valid_sources[0x6a] 123439 1 T115 1 T210 6 T248 2
valid_sources[0x6b] 127638 1 T115 2 T210 6 T249 8
valid_sources[0x6c] 126629 1 T110 1 T114 1 T210 8
valid_sources[0x6d] 130930 1 T109 1 T183 1 T210 6
valid_sources[0x6e] 125765 1 T114 1 T115 2 T210 6
valid_sources[0x6f] 129813 1 T109 2 T110 2 T115 1
valid_sources[0x70] 129256 1 T210 6 T248 2 T211 3
valid_sources[0x71] 131857 1 T115 1 T210 4 T248 1
valid_sources[0x72] 126182 1 T115 3 T210 15 T211 1
valid_sources[0x73] 126299 1 T183 1 T115 1 T210 5
valid_sources[0x74] 123136 1 T16 5 T115 2 T210 4
valid_sources[0x75] 125421 1 T115 1 T210 11 T248 1
valid_sources[0x76] 125550 1 T16 16 T110 1 T115 1
valid_sources[0x77] 124084 1 T114 1 T183 1 T115 1
valid_sources[0x78] 129747 1 T115 1 T210 5 T211 5
valid_sources[0x79] 127956 1 T110 3 T115 1 T210 9
valid_sources[0x7a] 126588 1 T114 1 T115 1 T210 10
valid_sources[0x7b] 129769 1 T114 1 T115 1 T210 4
valid_sources[0x7c] 126719 1 T183 2 T115 2 T210 9
valid_sources[0x7d] 129716 1 T110 1 T210 5 T185 2
valid_sources[0x7e] 127960 1 T110 3 T115 2 T210 2
valid_sources[0x7f] 124577 1 T109 2 T183 1 T115 3
valid_sources[0x80] 127118 1 T109 4 T114 2 T183 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 7981912 1 T16 55 T109 42 T110 22
values[0x0] all_enables biggest_size 11892623 1 T16 18 T109 21 T110 28
values[0x1] all_enables biggest_size 11894797 1 T16 26 T109 14 T110 25

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%