Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

70339308

1

T16

1

T109

1

T110

77

full_word

20960469

1

T16

289

T109

251

T110

184

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	91299447	1			T16	290		T109	252		T110	261
auto[TlIntgErrCmd]	110	1			T115	5		T211	8		T217	6
auto[TlIntgErrData]	103	1			T115	3		T211	5		T217	8
auto[TlIntgErrBoth]	117	1			T115	2		T211	7		T217	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12853869

1

T16

92

T109

94

T110

67

auto[1]

78445908

1

T16

198

T109

158

T110

194

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7715336	1			T16	1		T109	1		T110	21
auto[TlIntgErrNone]	partial	auto[1]	62623661	1			T110	56		T114	8		T111	13
auto[TlIntgErrNone]	full_word	auto[0]	5138400	1			T16	91		T109	93		T110	46
auto[TlIntgErrNone]	full_word	auto[1]	15822050	1			T16	198		T109	158		T110	138
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T211	2		T217	2		T241	1
auto[TlIntgErrCmd]	partial	auto[1]	67	1			T115	5		T211	6		T217	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T282	1		T323	1		T324	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T217	1		T245	1		T325	1
auto[TlIntgErrData]	partial	auto[0]	51	1			T115	2		T211	2		T217	5
auto[TlIntgErrData]	partial	auto[1]	44	1			T115	1		T211	3		T217	3
auto[TlIntgErrData]	full_word	auto[0]	3	1			T282	1		T323	1		T326	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T245	1		T282	1		T323	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T115	1		T211	4		T217	3
auto[TlIntgErrBoth]	partial	auto[1]	73	1			T115	1		T211	3		T217	3
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T246	1		T327	1		T328	1