Unified Coverage Report :: Module :: prim_lfsr

Module : prim_lfsr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.29			72.29

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_lfsr_0.1/rtl/prim_lfsr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.gen_double_lfsr[0].u_prim_lfsr	72.29			72.29
tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.gen_double_lfsr[1].u_prim_lfsr	72.29			72.29

---

Module Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.gen_double_lfsr[0].u_prim_lfsr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.29			72.29

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.29			72.29

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_prim_double_lfsr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.gen_double_lfsr[1].u_prim_lfsr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.29			72.29

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.29			72.29

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_prim_double_lfsr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_lfsr

	Total	Covered	Percent
Totals	5	4	80.00
Total Bits	166	120	72.29
Total Bits 0->1	83	60	72.29
Total Bits 1->0	83	60	72.29

Ports	5	4	80.00
Port Bits	166	120	72.29
Port Bits 0->1	83	60	72.29
Port Bits 1->0	83	60	72.29

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
seed_en_i	Unreachable	Unreachable		Unreachable		INPUT
seed_i[39:0]	Unreachable	Unreachable		Unreachable		INPUT
lfsr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
entropy_i[1:0]	No	No		No		INPUT
entropy_i[2]	Yes	Yes	*T4	Yes	T4	INPUT
entropy_i[3]	No	No		No		INPUT
entropy_i[7:4]	Yes	Yes	T4	Yes	T4	INPUT
entropy_i[11:8]	No	No		No		INPUT
entropy_i[13:12]	Yes	Yes	T4	Yes	T4	INPUT
entropy_i[14]	No	No		No		INPUT
entropy_i[15]	Yes	Yes	*T4	Yes	T4	INPUT
entropy_i[19:16]	No	No		No		INPUT
entropy_i[22:20]	Yes	Yes	T4	Yes	T4	INPUT
entropy_i[23]	No	No		No		INPUT
entropy_i[24]	Yes	Yes	*T4	Yes	T4	INPUT
entropy_i[25]	No	No		No		INPUT
entropy_i[28:26]	Yes	Yes	T4	Yes	T4	INPUT
entropy_i[30:29]	No	No		No		INPUT
entropy_i[32:31]	Yes	Yes	T4	Yes	T4	INPUT
entropy_i[39:33]	No	No		No		INPUT
state_o[39:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.gen_double_lfsr[0].u_prim_lfsr

	Total	Covered	Percent
Totals	5	4	80.00
Total Bits	166	120	72.29
Total Bits 0->1	83	60	72.29
Total Bits 1->0	83	60	72.29

Ports	5	4	80.00
Port Bits	166	120	72.29
Port Bits 0->1	83	60	72.29
Port Bits 1->0	83	60	72.29

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
seed_en_i	Unreachable	Unreachable		Unreachable		INPUT
seed_i[39:0]	Unreachable	Unreachable		Unreachable		INPUT
lfsr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
entropy_i[1:0]	No	No		No		INPUT
entropy_i[2]	Yes	Yes	*T4	Yes	T4	INPUT
entropy_i[3]	No	No		No		INPUT
entropy_i[7:4]	Yes	Yes	T4	Yes	T4	INPUT
entropy_i[11:8]	No	No		No		INPUT
entropy_i[13:12]	Yes	Yes	T4	Yes	T4	INPUT
entropy_i[14]	No	No		No		INPUT
entropy_i[15]	Yes	Yes	*T4	Yes	T4	INPUT
entropy_i[19:16]	No	No		No		INPUT
entropy_i[22:20]	Yes	Yes	T4	Yes	T4	INPUT
entropy_i[23]	No	No		No		INPUT
entropy_i[24]	Yes	Yes	*T4	Yes	T4	INPUT
entropy_i[25]	No	No		No		INPUT
entropy_i[28:26]	Yes	Yes	T4	Yes	T4	INPUT
entropy_i[30:29]	No	No		No		INPUT
entropy_i[32:31]	Yes	Yes	T4	Yes	T4	INPUT
entropy_i[39:33]	No	No		No		INPUT
state_o[39:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.gen_double_lfsr[1].u_prim_lfsr

	Total	Covered	Percent
Totals	5	4	80.00
Total Bits	166	120	72.29
Total Bits 0->1	83	60	72.29
Total Bits 1->0	83	60	72.29

Ports	5	4	80.00
Port Bits	166	120	72.29
Port Bits 0->1	83	60	72.29
Port Bits 1->0	83	60	72.29

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
seed_en_i	Unreachable	Unreachable		Unreachable		INPUT
seed_i[39:0]	Unreachable	Unreachable		Unreachable		INPUT
lfsr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
entropy_i[1:0]	No	No		No		INPUT
entropy_i[2]	Yes	Yes	*T4	Yes	T4	INPUT
entropy_i[3]	No	No		No		INPUT
entropy_i[7:4]	Yes	Yes	T4	Yes	T4	INPUT
entropy_i[11:8]	No	No		No		INPUT
entropy_i[13:12]	Yes	Yes	T4	Yes	T4	INPUT
entropy_i[14]	No	No		No		INPUT
entropy_i[15]	Yes	Yes	*T4	Yes	T4	INPUT
entropy_i[19:16]	No	No		No		INPUT
entropy_i[22:20]	Yes	Yes	T4	Yes	T4	INPUT
entropy_i[23]	No	No		No		INPUT
entropy_i[24]	Yes	Yes	*T4	Yes	T4	INPUT
entropy_i[25]	No	No		No		INPUT
entropy_i[28:26]	Yes	Yes	T4	Yes	T4	INPUT
entropy_i[30:29]	No	No		No		INPUT
entropy_i[32:31]	Yes	Yes	T4	Yes	T4	INPUT
entropy_i[39:33]	No	No		No		INPUT
state_o[39:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range