Unified Coverage Report :: Module :: prim_generic_otp

Module : prim_generic_otp

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.39	96.91	95.45		100.00	94.59	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_otp_0/rtl/prim_generic_otp.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_otp.gen_generic.u_impl_generic	97.39	96.91	95.45		100.00	94.59	100.00

---

Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.39	96.91	95.45		100.00	94.59	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.20	91.72	94.75	100.00	100.00	90.71	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_otp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_dec	100.00	100.00	100.00
u_enc	100.00	100.00
u_prim_ram_1p_adv	99.58	98.31	100.00			100.00	100.00
u_reg_top	94.55	89.51	93.40	100.00		89.82	100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_generic_otp

	Line No.	Total	Covered	Percent
TOTAL		97	94	96.91
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	78	1	0	0.00
CONT_ASSIGN	82	1	0	0.00
CONT_ASSIGN	84	1	0	0.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	173	1	1	100.00
ALWAYS	177	60	60	100.00
CONT_ASSIGN	301	1	1	100.00
CONT_ASSIGN	321	1	1	100.00
CONT_ASSIGN	325	1	1	100.00
CONT_ASSIGN	328	1	1	100.00
ALWAYS	332	0	0
ALWAYS	332	3	3	100.00
ALWAYS	365	3	3	100.00
ALWAYS	368	17	17	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_otp_0/rtl/prim_generic_otp.sv' or '../src/lowrisc_prim_generic_otp_0/rtl/prim_generic_otp.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
74	1	1
78	0	1
82	0	1
84	0	1
87	1	1
90	1	1
113	1	1
169	1	1
172	1	1
173	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			==> MISSING_ELSE
			MISSING_ELSE
201	1	1
202	1	1
203	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
			MISSING_ELSE
221	1	1
222	1	1
226	1	1
227	1	1
229	1	1
230	1	1
231	1	1
232	1	1
234	1	1
235	1	1
236	1	1
238	1	1
241	1	1
242	1	1
			MISSING_ELSE
			MISSING_ELSE
250	1	1
251	1	1
253	1	1
258	1	1
259	1	1
260	1	1
262	1	1
263	1	1
264	1	1
266	1	1
			MISSING_ELSE
273	1	1
274	1	1
275	1	1
276	1	1
277	1	1
			MISSING_ELSE
280	1	1
281	1	1
282	1	1
			MISSING_ELSE
287	1	1
301	1	1
321	1	1
325	1	1
328	1	1
332	1	1
333	1	1
335	1	1
365	3	3
368	1	1
369	1	1
370	1	1
371	1	1
372	1	1
373	1	1
374	1	1
375	1	1
377	1	1
378	1	1
379	1	1
380	1	1
381	1	1
382	1	1
383	1	1
			MISSING_ELSE
385	1	1
386	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_generic_otp

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       90
 EXPRESSION (intg_err || fsm_err)
             ----1---    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T20,T21,T22
1	0	Covered	T20,T21,T22

 LINE       169
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       169
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       194
 EXPRESSION (cmd_i == Init)
            -------1-------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       234
 EXPRESSION (cnt_q == size_q)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       262
 EXPRESSION (cnt_q == size_q)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       280
 EXPRESSION (cnt_q == size_q)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       321
 EXPRESSION (read_ecc_on ? ({{EccWidth {1'b0}}, rdata_corr}) : rdata_ecc)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       328
 EXPRESSION ((rdata_q[cnt_q] & wdata_ecc) != rdata_q[cnt_q])
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       380
 EXPRESSION (ready_o && valid_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Module : prim_generic_otp

Summary for FSM :: state_q

	Total	Covered	Percent
States	9	9	100.00	(Not included in score)
Transitions	11	11	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	286	Covered	T16
IdleSt	201	Covered	T16
InitSt	195	Covered	T16
ReadSt	213	Covered	T16
ReadWaitSt	221	Covered	T16
ResetSt	190	Covered	T16
WriteCheckSt	214	Covered	T16
WriteSt	264	Covered	T16
WriteWaitSt	250	Covered	T16

transitions	Line No.	Covered	Tests
IdleSt->ReadSt	213	Covered	T16
IdleSt->WriteCheckSt	214	Covered	T16
InitSt->IdleSt	201	Covered	T16
ReadSt->ReadWaitSt	221	Covered	T16
ReadWaitSt->IdleSt	230	Covered	T16
ReadWaitSt->ReadSt	238	Covered	T16
ResetSt->InitSt	195	Covered	T16
WriteCheckSt->WriteWaitSt	250	Covered	T16
WriteSt->IdleSt	282	Covered	T16
WriteWaitSt->WriteCheckSt	266	Covered	T16
WriteWaitSt->WriteSt	264	Covered	T16

---

Branch Coverage for Module : prim_generic_otp

	Line No.	Total	Covered	Percent
Branches		37	35	94.59
TERNARY	169	3	3	100.00
TERNARY	321	2	2	100.00
CASE	188	25	23	92.00
IF	365	2	2	100.00
IF	368	5	5	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_otp_0/rtl/prim_generic_otp.sv' or '../src/lowrisc_prim_generic_otp_0/rtl/prim_generic_otp.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	169	(cnt_clr) ? 
-2-:	169	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	(read_ecc_on) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	188	case (state_q)
-2-:	193	if (valid_i)
-3-:	194	if ((cmd_i == Init))
-4-:	209	if (valid_i)
-5-:	212	case (cmd_i)
-6-:	226	if (rvalid)
-7-:	229	if (rerror[1])
-8-:	234	if ((cnt_q == size_q))
-9-:	241	if (rerror[0])
-10-:	259	if (rvalid)
-11-:	262	if ((cnt_q == size_q))
-12-:	276	if (wdata_inconsistent)
-13-:	280	if ((cnt_q == size_q))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	Not Covered
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	1	Read	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	1	Write	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	1	default	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T9,T37,T48
ReadWaitSt	-	-	-	-	1	0	1	-	-	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	1	0	0	-	-	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	1	0	-	1	-	-	-	-	Covered	T9,T37,T58
ReadWaitSt	-	-	-	-	1	0	-	0	-	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
WriteCheckSt	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
WriteWaitSt	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T1,T2,T3
WriteWaitSt	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T1,T2,T3
WriteWaitSt	-	-	-	-	-	-	-	-	0	-	-	-	Covered	T1,T2,T3
WriteSt	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T9,T95,T14
WriteSt	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T1,T2,T3
WriteSt	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T3
WriteSt	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T22
default	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	365	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	368	if ((!rst_ni))
-2-:	380	if ((ready_o && valid_i))
-3-:	385	if (rvalid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	-	Covered	T1,T2,T3
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_otp

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckCommands0_A	2147483647	11695	0	0
CheckCommands1_A	2147483647	1332342	0	0
NoWrapArounds_A	2147483647	4038174	0	0
SecDecWidth_A	1157	1157	0	0
u_state_regs_A	2147483647	2147483647	0	0

CheckCommands0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	11695	0	0
T1	73436	19	0	0
T2	38018	11	0	0
T3	110228	16	0	0
T5	7499	4	0	0
T6	50788	14	0	0
T7	111091	6	0	0
T8	8171	1	0	0
T9	19415	3	0	0
T10	10832	3	0	0
T11	12755	4	0	0

CheckCommands1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1332342	0	0
T1	73436	1463	0	0
T2	38018	833	0	0
T3	110228	1315	0	0
T5	7499	134	0	0
T6	50788	2590	0	0
T7	111091	1038	0	0
T8	8171	51	0	0
T9	19415	159	0	0
T10	10832	251	0	0
T11	12755	268	0	0

NoWrapArounds_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4038174	0	0
T1	73436	4781	0	0
T2	38018	2795	0	0
T3	110228	4300	0	0
T5	7499	542	0	0
T6	50788	6643	0	0
T7	111091	3364	0	0
T8	8171	204	0	0
T9	19415	656	0	0
T10	10832	832	0	0
T11	12755	990	0	0

SecDecWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0