Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.gen_alert_tx[4].u_prim_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
77.78 77.78


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
77.78 77.78


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.99 97.89 88.57 96.52 96.97 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alert_tx[0].u_prim_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.99 97.89 88.57 96.52 96.97 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alert_tx[1].u_prim_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.99 97.89 88.57 96.52 96.97 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alert_tx[2].u_prim_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.99 97.89 88.57 96.52 96.97 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alert_tx[3].u_prim_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.99 97.89 88.57 96.52 96.97 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_alert_sender
TotalCoveredPercent
Totals 10 10 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 10 10 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T16,T109,T110 Yes T16,T109,T110 INPUT
rst_ni Yes Yes T110,T115,T184 Yes T16,T109,T110 INPUT
alert_test_i Yes Yes T16,T109,T110 Yes T16,T109,T110 INPUT
alert_req_i Yes Yes T115,T211,T217 Yes T115,T211,T217 INPUT
alert_ack_o Yes Yes T115,T211,T217 Yes T115,T211,T217 OUTPUT
alert_state_o Yes Yes T115,T211,T217 Yes T115,T211,T217 OUTPUT
alert_rx_i.ack_n Yes Yes T16,T109,T110 Yes T16,T109,T110 INPUT
alert_rx_i.ack_p Yes Yes T16,T109,T110 Yes T16,T109,T110 INPUT
alert_rx_i.ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i.ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o.alert_n Yes Yes T16,T109,T110 Yes T16,T109,T110 OUTPUT
alert_tx_o.alert_p Yes Yes T16,T109,T110 Yes T16,T109,T110 OUTPUT

Toggle Coverage for Instance : tb.dut.gen_alert_tx[4].u_prim_alert_sender
TotalCoveredPercent
Totals 9 7 77.78
Total Bits 18 14 77.78
Total Bits 0->1 9 7 77.78
Total Bits 1->0 9 7 77.78

Ports 9 7 77.78
Port Bits 18 14 77.78
Port Bits 0->1 9 7 77.78
Port Bits 1->0 9 7 77.78

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T16,T109,T110 Yes T16,T109,T110 INPUT
rst_ni Yes Yes T110,T115,T184 Yes T16,T109,T110 INPUT
alert_test_i Yes Yes T16,T109,T114 Yes T16,T109,T114 INPUT
alert_req_i Unreachable Unreachable Unreachable INPUT
alert_ack_o No No No OUTPUT
alert_state_o No No No OUTPUT
alert_rx_i.ack_n Yes Yes T16,T109,T110 Yes T16,T109,T110 INPUT
alert_rx_i.ack_p Yes Yes T16,T109,T114 Yes T16,T109,T114 INPUT
alert_rx_i.ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i.ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o.alert_n Yes Yes T16,T109,T110 Yes T16,T109,T110 OUTPUT
alert_tx_o.alert_p Yes Yes T16,T109,T114 Yes T16,T109,T114 OUTPUT

Toggle Coverage for Instance : tb.dut.gen_alert_tx[0].u_prim_alert_sender
TotalCoveredPercent
Totals 10 10 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 10 10 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T16,T109,T110 Yes T16,T109,T110 INPUT
rst_ni Yes Yes T110,T115,T184 Yes T16,T109,T110 INPUT
alert_test_i Yes Yes T16,T109,T110 Yes T16,T109,T110 INPUT
alert_req_i Yes Yes T9,T37,T48 Yes T9,T37,T48 INPUT
alert_ack_o Yes Yes T9,T37,T48 Yes T9,T37,T48 OUTPUT
alert_state_o Yes Yes T9,T37,T48 Yes T9,T37,T48 OUTPUT
alert_rx_i.ack_n Yes Yes T16,T109,T110 Yes T16,T109,T110 INPUT
alert_rx_i.ack_p Yes Yes T16,T109,T110 Yes T16,T109,T110 INPUT
alert_rx_i.ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i.ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o.alert_n Yes Yes T16,T109,T110 Yes T16,T109,T110 OUTPUT
alert_tx_o.alert_p Yes Yes T16,T109,T110 Yes T16,T109,T110 OUTPUT

Toggle Coverage for Instance : tb.dut.gen_alert_tx[1].u_prim_alert_sender
TotalCoveredPercent
Totals 10 10 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 10 10 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T16,T109,T110 Yes T16,T109,T110 INPUT
rst_ni Yes Yes T110,T115,T184 Yes T16,T109,T110 INPUT
alert_test_i Yes Yes T16,T109,T183 Yes T16,T109,T183 INPUT
alert_req_i Yes Yes T7,T9,T37 Yes T7,T9,T37 INPUT
alert_ack_o Yes Yes T7,T9,T37 Yes T7,T9,T37 OUTPUT
alert_state_o Yes Yes T7,T9,T37 Yes T7,T9,T37 OUTPUT
alert_rx_i.ack_n Yes Yes T16,T109,T110 Yes T16,T109,T110 INPUT
alert_rx_i.ack_p Yes Yes T16,T109,T183 Yes T16,T109,T183 INPUT
alert_rx_i.ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i.ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o.alert_n Yes Yes T16,T109,T110 Yes T16,T109,T110 OUTPUT
alert_tx_o.alert_p Yes Yes T16,T109,T183 Yes T16,T109,T183 OUTPUT

Toggle Coverage for Instance : tb.dut.gen_alert_tx[2].u_prim_alert_sender
TotalCoveredPercent
Totals 10 10 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 10 10 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T16,T109,T110 Yes T16,T109,T110 INPUT
rst_ni Yes Yes T110,T115,T184 Yes T16,T109,T110 INPUT
alert_test_i Yes Yes T16,T109,T110 Yes T16,T109,T110 INPUT
alert_req_i Yes Yes T115,T211,T217 Yes T115,T211,T217 INPUT
alert_ack_o Yes Yes T115,T211,T217 Yes T115,T211,T217 OUTPUT
alert_state_o Yes Yes T115,T211,T217 Yes T115,T211,T217 OUTPUT
alert_rx_i.ack_n Yes Yes T16,T109,T110 Yes T16,T109,T110 INPUT
alert_rx_i.ack_p Yes Yes T16,T109,T110 Yes T16,T109,T110 INPUT
alert_rx_i.ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i.ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o.alert_n Yes Yes T16,T109,T110 Yes T16,T109,T110 OUTPUT
alert_tx_o.alert_p Yes Yes T16,T109,T110 Yes T16,T109,T110 OUTPUT

Toggle Coverage for Instance : tb.dut.gen_alert_tx[3].u_prim_alert_sender
TotalCoveredPercent
Totals 10 10 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 10 10 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T16,T109,T110 Yes T16,T109,T110 INPUT
rst_ni Yes Yes T110,T115,T184 Yes T16,T109,T110 INPUT
alert_test_i Yes Yes T16,T109,T110 Yes T16,T109,T110 INPUT
alert_req_i Yes Yes T115,T211,T217 Yes T115,T211,T217 INPUT
alert_ack_o Yes Yes T115,T211,T217 Yes T115,T211,T217 OUTPUT
alert_state_o Yes Yes T115,T211,T217 Yes T115,T211,T217 OUTPUT
alert_rx_i.ack_n Yes Yes T16,T109,T110 Yes T16,T109,T110 INPUT
alert_rx_i.ack_p Yes Yes T16,T109,T110 Yes T16,T109,T110 INPUT
alert_rx_i.ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i.ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o.alert_n Yes Yes T16,T109,T110 Yes T16,T109,T110 OUTPUT
alert_tx_o.alert_p Yes Yes T16,T109,T110 Yes T16,T109,T110 OUTPUT

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%