Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
33.39	22.78	29.38	12.68	0.00	22.85	99.69	46.35

Total tests in report: 174

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
31.96	31.96	21.72	21.72	25.12	25.12	32.23	32.23	0.00	0.00	21.96	21.96	93.45	93.45	29.22	29.22	/workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.1282584298
34.08	2.12	22.27	0.56	27.79	2.67	32.30	0.07	0.00	0.00	22.43	0.47	94.70	1.25	39.04	9.82	/workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.3657466658
34.62	0.54	22.31	0.04	28.21	0.43	32.33	0.03	0.00	0.00	22.64	0.21	94.85	0.16	41.98	2.94	/workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.2486052909
35.13	0.51	22.31	0.00	28.21	0.00	32.33	0.00	0.00	0.00	22.64	0.00	97.82	2.96	42.57	0.59	/workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.3046773682
35.45	0.32	22.31	0.00	28.29	0.08	32.35	0.02	0.00	0.00	22.64	0.00	98.44	0.62	44.08	1.51	/workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.1562626424
35.69	0.25	22.37	0.06	28.80	0.51	32.35	0.00	0.00	0.00	22.96	0.32	99.22	0.78	44.16	0.08	/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.1815025582
35.80	0.11	22.37	0.00	28.80	0.00	32.35	0.00	0.00	0.00	22.96	0.00	99.38	0.16	44.75	0.59	/workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.2149700802
35.88	0.08	22.37	0.00	28.85	0.05	32.35	0.00	0.00	0.00	22.96	0.00	99.38	0.00	45.26	0.50	/workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.2085078450
35.96	0.07	22.70	0.33	28.96	0.11	32.35	0.00	0.00	0.00	22.96	0.00	99.38	0.00	45.34	0.08	/workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.43534074
35.99	0.04	22.70	0.00	29.07	0.11	32.35	0.00	0.00	0.00	22.96	0.00	99.38	0.00	45.51	0.17	/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.2585220779
36.03	0.04	22.70	0.00	29.07	0.00	32.35	0.00	0.00	0.00	22.96	0.00	99.38	0.00	45.76	0.25	/workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.1636625120
36.06	0.03	22.72	0.02	29.09	0.03	32.35	0.00	0.00	0.00	22.96	0.00	99.38	0.00	45.93	0.17	/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.2529456651
36.09	0.03	22.72	0.00	29.15	0.05	32.35	0.00	0.00	0.00	22.96	0.00	99.53	0.16	45.93	0.00	/workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.1207725461
36.11	0.02	22.72	0.00	29.15	0.00	32.35	0.00	0.00	0.00	22.96	0.00	99.69	0.16	45.93	0.00	/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.1372089888
36.14	0.02	22.79	0.07	29.23	0.08	32.35	0.00	0.00	0.00	22.96	0.00	99.69	0.00	45.93	0.00	/workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.366914357
36.15	0.02	22.79	0.00	29.25	0.03	32.35	0.00	0.00	0.00	22.96	0.00	99.69	0.00	46.01	0.08	/workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.3265628462
36.16	0.01	22.79	0.00	29.25	0.00	32.35	0.00	0.00	0.00	22.96	0.00	99.69	0.00	46.10	0.08	/workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.628485635
36.17	0.01	22.79	0.00	29.25	0.00	32.35	0.00	0.00	0.00	22.96	0.00	99.69	0.00	46.18	0.08	/workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.3382435610
36.19	0.01	22.79	0.00	29.25	0.00	32.35	0.00	0.00	0.00	22.96	0.00	99.69	0.00	46.26	0.08	/workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.396537730
36.20	0.01	22.79	0.00	29.25	0.00	32.35	0.00	0.00	0.00	22.96	0.00	99.69	0.00	46.35	0.08	/workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.2896454329
36.21	0.01	22.79	0.00	29.33	0.08	32.35	0.00	0.00	0.00	22.96	0.00	99.69	0.00	46.35	0.00	/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.3990141069
36.22	0.01	22.83	0.04	29.33	0.00	32.35	0.00	0.00	0.00	22.96	0.00	99.69	0.00	46.35	0.00	/workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.3421714847
36.22	0.01	22.83	0.00	29.36	0.03	32.35	0.00	0.00	0.00	22.96	0.00	99.69	0.00	46.35	0.00	/workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.4237728119
36.22	0.01	22.83	0.00	29.39	0.03	32.35	0.00	0.00	0.00	22.96	0.00	99.69	0.00	46.35	0.00	/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.1626189367
36.23	0.01	22.83	0.00	29.41	0.03	32.35	0.00	0.00	0.00	22.96	0.00	99.69	0.00	46.35	0.00	/workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.1328962040

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.163773156
/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.3236359586
/workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.2295945033
/workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.2714383151
/workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.306881326
/workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.421564856
/workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.2634927775
/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.4214782361
/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.3689818905
/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.2365835092
/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.769886525
/workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.2317009119
/workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.597384609
/workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.532144652
/workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.2514466825
/workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.1174308472
/workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.1084942451
/workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.228914309
/workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.1727632673
/workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.1991764754
/workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.1562485611
/workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.533649204
/workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.1005925087
/workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.1913634575
/workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.2391926874
/workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.559038237
/workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.3547964058
/workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.3810868070
/workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.1287112125
/workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.2458923525
/workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.798305123
/workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.1944568906
/workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.1431396317
/workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.1373559883
/workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.4054803677
/workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.159403247
/workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.3261744511
/workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.2324843440
/workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.3234954322
/workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.2908753560
/workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.2773654584
/workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.3035339086
/workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.2609729414
/workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.1083857436
/workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.3043939827
/workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.3000415985
/workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.1991926442
/workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.1962095628
/workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.2038639436
/workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.2849395476
/workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.1772581279
/workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.1142270488
/workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.477355506
/workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.1740276466
/workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.2590446810
/workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.4173024249
/workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.1566837976
/workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.3797650438
/workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.1005379748
/workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.3222146924
/workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.3303437883
/workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.744399842
/workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.192454113
/workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.1739560425
/workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.3103090780
/workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.703093223
/workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.2099859918
/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.4021590458
/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.1557953235
/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.355679429
/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.1025878143
/workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.2623016035
/workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.892753262
/workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.742676156
/workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.1878109792
/workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.3250454885
/workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.2701573413
/workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.4165063640
/workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.3966078342
/workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.328369771
/workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.2395188171
/workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.429386769
/workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.1224341598
/workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.2967025037
/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.3427192046
/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.1068128480
/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.2679073499
/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.3610974496
/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.3815339669
/workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.1568852954
/workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.854982147
/workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.2577993258
/workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.3534570995
/workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.2983650039
/workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.2892066561
/workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.3501578924
/workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.3316397458
/workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.2840931674
/workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.3233573881
/workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.3483469290
/workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.3531504525
/workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.3470397677
/workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.1961657164
/workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.3874881902
/workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.4234671620
/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.575625828
/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.3360463357
/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.832884655
/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.3681694394
/workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.735907533
/workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.3908956159
/workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.128107039
/workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.828431845
/workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.1944919783
/workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.426586420
/workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.4181712933
/workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.1388549874
/workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.577589052
/workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.3435148343
/workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.749529168
/workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.1237757634
/workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.72474829
/workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.345941679
/workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.691609195
/workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.2953277024
/workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.161184849
/workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.98926542
/workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.3575357121
/workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.3075779471
/workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.2583768498
/workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.3139127206
/workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.2178992099
/workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.642578371
/workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.699416142
/workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.3678367478
/workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.31556967
/workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.1128240445
/workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.2296439514
/workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.675871341
/workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.3092064885
/workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.2702861880
/workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.625590401
/workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.680694890
/workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.173484274
/workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.3039297457
/workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.303516503
/workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.901540377
/workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.2056617588
/workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.2862683859

Total test records in report: 174

tests.html | tests1.html | tests2.html

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.1282584298	Feb 04 12:37:53 PM PST 24	Feb 04 12:38:07 PM PST 24	2527848307 ps
T2	/workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.3092064885	Feb 04 12:37:33 PM PST 24	Feb 04 12:37:51 PM PST 24	1564931444 ps
T3	/workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.2896454329	Feb 04 12:37:39 PM PST 24	Feb 04 12:37:57 PM PST 24	1349997088 ps
T4	/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.832884655	Feb 04 12:37:33 PM PST 24	Feb 04 12:37:47 PM PST 24	181089289 ps
T5	/workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.3382435610	Feb 04 12:37:37 PM PST 24	Feb 04 12:37:59 PM PST 24	10850157969 ps
T11	/workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.2085078450	Feb 04 12:37:31 PM PST 24	Feb 04 12:37:52 PM PST 24	1477798485 ps
T12	/workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.1207725461	Feb 04 12:37:27 PM PST 24	Feb 04 12:37:35 PM PST 24	936560444 ps
T13	/workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.128107039	Feb 04 12:37:34 PM PST 24	Feb 04 12:37:46 PM PST 24	37411807 ps
T14	/workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.2773654584	Feb 04 12:37:56 PM PST 24	Feb 04 12:38:02 PM PST 24	108614638 ps
T6	/workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.3043939827	Feb 04 12:37:56 PM PST 24	Feb 04 12:38:01 PM PST 24	38102342 ps
T23	/workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.3797650438	Feb 04 12:37:51 PM PST 24	Feb 04 12:37:57 PM PST 24	40207099 ps
T15	/workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.3657466658	Feb 04 12:37:56 PM PST 24	Feb 04 12:38:05 PM PST 24	600422873 ps
T16	/workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.4237728119	Feb 04 12:37:08 PM PST 24	Feb 04 12:37:21 PM PST 24	98604033 ps
T27	/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.3689818905	Feb 04 12:37:08 PM PST 24	Feb 04 12:37:27 PM PST 24	406602516 ps
T24	/workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.2702861880	Feb 04 12:37:26 PM PST 24	Feb 04 12:37:57 PM PST 24	18542946572 ps
T17	/workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.173484274	Feb 04 12:37:40 PM PST 24	Feb 04 12:37:49 PM PST 24	137006090 ps
T25	/workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.2634927775	Feb 04 12:37:07 PM PST 24	Feb 04 12:37:30 PM PST 24	9409232463 ps
T34	/workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.396537730	Feb 04 12:37:56 PM PST 24	Feb 04 12:38:09 PM PST 24	607237185 ps
T28	/workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.3046773682	Feb 04 12:37:38 PM PST 24	Feb 04 12:37:47 PM PST 24	38711775 ps
T29	/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.3427192046	Feb 04 12:37:41 PM PST 24	Feb 04 12:37:52 PM PST 24	57783628 ps
T7	/workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.328369771	Feb 04 12:37:41 PM PST 24	Feb 04 12:37:48 PM PST 24	34343753 ps
T8	/workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.2149700802	Feb 04 12:37:39 PM PST 24	Feb 04 12:37:48 PM PST 24	568914207 ps
T9	/workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.2953277024	Feb 04 12:37:47 PM PST 24	Feb 04 12:37:55 PM PST 24	40009340 ps
T26	/workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.1562626424	Feb 04 12:37:36 PM PST 24	Feb 04 12:38:02 PM PST 24	1611354983 ps
T18	/workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.2583768498	Feb 04 12:37:18 PM PST 24	Feb 04 12:37:33 PM PST 24	194134093 ps
T19	/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.2365835092	Feb 04 12:37:12 PM PST 24	Feb 04 12:37:30 PM PST 24	392588031 ps
T10	/workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.3316397458	Feb 04 12:37:35 PM PST 24	Feb 04 12:37:47 PM PST 24	72048950 ps
T30	/workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.680694890	Feb 04 12:37:35 PM PST 24	Feb 04 12:37:47 PM PST 24	235161331 ps
T68	/workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.4181712933	Feb 04 12:37:48 PM PST 24	Feb 04 12:37:55 PM PST 24	41354589 ps
T69	/workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.1224341598	Feb 04 12:37:38 PM PST 24	Feb 04 12:37:47 PM PST 24	580017801 ps
T20	/workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.744399842	Feb 04 12:37:48 PM PST 24	Feb 04 12:37:56 PM PST 24	281144898 ps
T21	/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.3610974496	Feb 04 12:37:32 PM PST 24	Feb 04 12:37:47 PM PST 24	73529152 ps
T70	/workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.2849395476	Feb 04 12:37:37 PM PST 24	Feb 04 12:37:47 PM PST 24	41983062 ps
T31	/workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.1913634575	Feb 04 12:37:40 PM PST 24	Feb 04 12:37:48 PM PST 24	572677092 ps
T32	/workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.559038237	Feb 04 12:37:23 PM PST 24	Feb 04 12:37:34 PM PST 24	154158601 ps
T33	/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.3360463357	Feb 04 12:37:19 PM PST 24	Feb 04 12:37:36 PM PST 24	550451428 ps
T45	/workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.2486052909	Feb 04 12:37:39 PM PST 24	Feb 04 12:37:47 PM PST 24	80304861 ps
T38	/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.163773156	Feb 04 12:37:02 PM PST 24	Feb 04 12:37:16 PM PST 24	190908610 ps
T46	/workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.3483469290	Feb 04 12:37:42 PM PST 24	Feb 04 12:37:51 PM PST 24	39037176 ps
T47	/workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.691609195	Feb 04 12:37:46 PM PST 24	Feb 04 12:37:54 PM PST 24	49803854 ps
T37	/workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.3547964058	Feb 04 12:37:35 PM PST 24	Feb 04 12:38:04 PM PST 24	1456012870 ps
T22	/workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.533649204	Feb 04 12:37:37 PM PST 24	Feb 04 12:37:49 PM PST 24	375898149 ps
T85	/workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.628485635	Feb 04 12:37:39 PM PST 24	Feb 04 12:38:07 PM PST 24	18466177854 ps
T58	/workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.421564856	Feb 04 12:37:10 PM PST 24	Feb 04 12:37:29 PM PST 24	882396423 ps
T39	/workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.798305123	Feb 04 12:37:28 PM PST 24	Feb 04 12:37:38 PM PST 24	56577771 ps
T84	/workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.3265628462	Feb 04 12:37:28 PM PST 24	Feb 04 12:37:48 PM PST 24	589558011 ps
T89	/workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.3233573881	Feb 04 12:37:50 PM PST 24	Feb 04 12:37:56 PM PST 24	39112419 ps
T59	/workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.3039297457	Feb 04 12:37:20 PM PST 24	Feb 04 12:37:33 PM PST 24	66533997 ps
T35	/workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.1944568906	Feb 04 12:37:22 PM PST 24	Feb 04 12:37:34 PM PST 24	122427454 ps
T40	/workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.2514466825	Feb 04 12:37:29 PM PST 24	Feb 04 12:37:44 PM PST 24	295657253 ps
T90	/workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.3470397677	Feb 04 12:37:37 PM PST 24	Feb 04 12:37:47 PM PST 24	566587810 ps
T60	/workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.1878109792	Feb 04 12:37:46 PM PST 24	Feb 04 12:37:54 PM PST 24	61709988 ps
T36	/workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.1991926442	Feb 04 12:37:43 PM PST 24	Feb 04 12:37:56 PM PST 24	561308029 ps
T91	/workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.159403247	Feb 04 12:37:51 PM PST 24	Feb 04 12:37:57 PM PST 24	74420450 ps
T92	/workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.303516503	Feb 04 12:37:22 PM PST 24	Feb 04 12:37:33 PM PST 24	585432720 ps
T93	/workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.2701573413	Feb 04 12:37:47 PM PST 24	Feb 04 12:37:54 PM PST 24	39184538 ps
T62	/workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.1005925087	Feb 04 12:37:20 PM PST 24	Feb 04 12:37:33 PM PST 24	133576397 ps
T94	/workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.699416142	Feb 04 12:37:35 PM PST 24	Feb 04 12:37:47 PM PST 24	523129331 ps
T41	/workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.477355506	Feb 04 12:37:28 PM PST 24	Feb 04 12:37:38 PM PST 24	77549774 ps
T42	/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.3681694394	Feb 04 12:37:20 PM PST 24	Feb 04 12:37:33 PM PST 24	42568657 ps
T95	/workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.3435148343	Feb 04 12:37:40 PM PST 24	Feb 04 12:37:48 PM PST 24	72941099 ps
T82	/workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.2099859918	Feb 04 12:37:50 PM PST 24	Feb 04 12:38:12 PM PST 24	4667919540 ps
T61	/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.2529456651	Feb 04 12:37:18 PM PST 24	Feb 04 12:37:32 PM PST 24	98505978 ps
T96	/workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.2324843440	Feb 04 12:37:56 PM PST 24	Feb 04 12:38:02 PM PST 24	213868527 ps
T97	/workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.1727632673	Feb 04 12:37:19 PM PST 24	Feb 04 12:37:32 PM PST 24	145584719 ps
T88	/workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.1142270488	Feb 04 12:37:28 PM PST 24	Feb 04 12:37:41 PM PST 24	129683818 ps
T98	/workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.597384609	Feb 04 12:37:10 PM PST 24	Feb 04 12:37:28 PM PST 24	531369331 ps
T43	/workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.642578371	Feb 04 12:37:41 PM PST 24	Feb 04 12:37:50 PM PST 24	62961460 ps
T99	/workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.345941679	Feb 04 12:37:41 PM PST 24	Feb 04 12:37:49 PM PST 24	78355601 ps
T100	/workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.2178992099	Feb 04 12:37:31 PM PST 24	Feb 04 12:37:45 PM PST 24	132145433 ps
T63	/workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.161184849	Feb 04 12:37:22 PM PST 24	Feb 04 12:37:34 PM PST 24	112858762 ps
T101	/workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.1084942451	Feb 04 12:37:12 PM PST 24	Feb 04 12:37:36 PM PST 24	1418940369 ps
T102	/workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.2458923525	Feb 04 12:37:39 PM PST 24	Feb 04 12:37:47 PM PST 24	35590798 ps
T103	/workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.4165063640	Feb 04 12:37:34 PM PST 24	Feb 04 12:37:46 PM PST 24	144859877 ps
T104	/workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.1005379748	Feb 04 12:37:39 PM PST 24	Feb 04 12:37:47 PM PST 24	60112724 ps
T74	/workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.2983650039	Feb 04 12:37:33 PM PST 24	Feb 04 12:37:51 PM PST 24	2259820857 ps
T105	/workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.1562485611	Feb 04 12:37:38 PM PST 24	Feb 04 12:37:48 PM PST 24	45407916 ps
T75	/workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.3035339086	Feb 04 12:37:40 PM PST 24	Feb 04 12:37:53 PM PST 24	2256383781 ps
T106	/workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.3139127206	Feb 04 12:37:32 PM PST 24	Feb 04 12:38:05 PM PST 24	3384414337 ps
T107	/workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.3908956159	Feb 04 12:37:28 PM PST 24	Feb 04 12:37:41 PM PST 24	490360117 ps
T44	/workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.2038639436	Feb 04 12:37:44 PM PST 24	Feb 04 12:37:53 PM PST 24	41175675 ps
T48	/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.1025878143	Feb 04 12:37:16 PM PST 24	Feb 04 12:37:31 PM PST 24	134177779 ps
T108	/workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.625590401	Feb 04 12:37:40 PM PST 24	Feb 04 12:37:48 PM PST 24	66897902 ps
T49	/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.575625828	Feb 04 12:37:35 PM PST 24	Feb 04 12:37:49 PM PST 24	63420479 ps
T109	/workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.1944919783	Feb 04 12:37:21 PM PST 24	Feb 04 12:37:35 PM PST 24	785507957 ps
T110	/workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.2967025037	Feb 04 12:37:51 PM PST 24	Feb 04 12:37:57 PM PST 24	37940882 ps
T71	/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.2585220779	Feb 04 12:37:10 PM PST 24	Feb 04 12:37:28 PM PST 24	185312532 ps
T111	/workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.1566837976	Feb 04 12:37:48 PM PST 24	Feb 04 12:37:57 PM PST 24	100526685 ps
T112	/workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.2296439514	Feb 04 12:37:39 PM PST 24	Feb 04 12:37:47 PM PST 24	629182900 ps
T78	/workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.3250454885	Feb 04 12:37:11 PM PST 24	Feb 04 12:37:32 PM PST 24	1616320698 ps
T50	/workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.1128240445	Feb 04 12:37:41 PM PST 24	Feb 04 12:37:49 PM PST 24	55323291 ps
T113	/workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.2317009119	Feb 04 12:37:11 PM PST 24	Feb 04 12:37:28 PM PST 24	73717331 ps
T114	/workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.2395188171	Feb 04 12:37:43 PM PST 24	Feb 04 12:37:52 PM PST 24	75786298 ps
T115	/workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.892753262	Feb 04 12:37:21 PM PST 24	Feb 04 12:37:32 PM PST 24	136567699 ps
T51	/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.1815025582	Feb 04 12:37:29 PM PST 24	Feb 04 12:37:43 PM PST 24	189119729 ps
T53	/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.4021590458	Feb 04 12:37:34 PM PST 24	Feb 04 12:37:50 PM PST 24	237956146 ps
T116	/workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.2056617588	Feb 04 12:37:29 PM PST 24	Feb 04 12:37:43 PM PST 24	811071357 ps
T117	/workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.2577993258	Feb 04 12:37:19 PM PST 24	Feb 04 12:37:32 PM PST 24	73921243 ps
T76	/workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.4173024249	Feb 04 12:37:41 PM PST 24	Feb 04 12:37:51 PM PST 24	223739388 ps
T64	/workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.1772581279	Feb 04 12:37:28 PM PST 24	Feb 04 12:37:43 PM PST 24	1050952381 ps
T118	/workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.2590446810	Feb 04 12:37:56 PM PST 24	Feb 04 12:38:01 PM PST 24	43693074 ps
T119	/workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.3261744511	Feb 04 12:37:40 PM PST 24	Feb 04 12:37:51 PM PST 24	121644020 ps
T120	/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.1068128480	Feb 04 12:37:28 PM PST 24	Feb 04 12:37:43 PM PST 24	130937188 ps
T121	/workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.3222146924	Feb 04 12:37:36 PM PST 24	Feb 04 12:37:47 PM PST 24	94041902 ps
T54	/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.3815339669	Feb 04 12:37:34 PM PST 24	Feb 04 12:37:47 PM PST 24	173437226 ps
T79	/workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.43534074	Feb 04 12:37:21 PM PST 24	Feb 04 12:37:41 PM PST 24	2652824837 ps
T83	/workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.2892066561	Feb 04 12:37:35 PM PST 24	Feb 04 12:38:05 PM PST 24	2314043293 ps
T122	/workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.749529168	Feb 04 12:37:41 PM PST 24	Feb 04 12:37:49 PM PST 24	66887758 ps
T123	/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.3236359586	Feb 04 12:37:18 PM PST 24	Feb 04 12:37:43 PM PST 24	7433957334 ps
T80	/workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.3421714847	Feb 04 12:37:32 PM PST 24	Feb 04 12:37:50 PM PST 24	144106961 ps
T124	/workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.3534570995	Feb 04 12:37:21 PM PST 24	Feb 04 12:37:33 PM PST 24	88016287 ps
T125	/workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.3000415985	Feb 04 12:37:37 PM PST 24	Feb 04 12:37:48 PM PST 24	54454699 ps
T126	/workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.1373559883	Feb 04 12:37:49 PM PST 24	Feb 04 12:37:56 PM PST 24	203292196 ps
T77	/workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.1328962040	Feb 04 12:37:15 PM PST 24	Feb 04 12:37:40 PM PST 24	1693153780 ps
T127	/workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.2623016035	Feb 04 12:37:13 PM PST 24	Feb 04 12:37:29 PM PST 24	62301837 ps
T128	/workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.1083857436	Feb 04 12:37:55 PM PST 24	Feb 04 12:38:01 PM PST 24	45464794 ps
T129	/workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.1961657164	Feb 04 12:37:48 PM PST 24	Feb 04 12:37:55 PM PST 24	37320369 ps
T130	/workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.1568852954	Feb 04 12:37:21 PM PST 24	Feb 04 12:37:32 PM PST 24	589460649 ps
T52	/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.1372089888	Feb 04 12:37:09 PM PST 24	Feb 04 12:37:25 PM PST 24	45392484 ps
T131	/workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.703093223	Feb 04 12:37:57 PM PST 24	Feb 04 12:38:05 PM PST 24	905052141 ps
T132	/workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.3575357121	Feb 04 12:37:41 PM PST 24	Feb 04 12:37:49 PM PST 24	39079018 ps
T133	/workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.3075779471	Feb 04 12:37:29 PM PST 24	Feb 04 12:37:43 PM PST 24	47606103 ps
T134	/workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.3810868070	Feb 04 12:37:35 PM PST 24	Feb 04 12:37:48 PM PST 24	202837568 ps
T135	/workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.2840931674	Feb 04 12:37:44 PM PST 24	Feb 04 12:37:53 PM PST 24	68794408 ps
T136	/workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.532144652	Feb 04 12:37:13 PM PST 24	Feb 04 12:37:29 PM PST 24	141595998 ps
T137	/workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.2609729414	Feb 04 12:37:34 PM PST 24	Feb 04 12:37:48 PM PST 24	1516354631 ps
T138	/workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.2862683859	Feb 04 12:37:32 PM PST 24	Feb 04 12:37:55 PM PST 24	1256127122 ps
T139	/workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.306881326	Feb 04 12:37:13 PM PST 24	Feb 04 12:37:29 PM PST 24	70613722 ps
T140	/workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.3966078342	Feb 04 12:37:40 PM PST 24	Feb 04 12:37:48 PM PST 24	566461146 ps
T141	/workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.675871341	Feb 04 12:37:39 PM PST 24	Feb 04 12:37:48 PM PST 24	81021392 ps
T142	/workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.228914309	Feb 04 12:37:19 PM PST 24	Feb 04 12:37:33 PM PST 24	64452202 ps
T143	/workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.31556967	Feb 04 12:37:32 PM PST 24	Feb 04 12:37:48 PM PST 24	101619026 ps
T144	/workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.429386769	Feb 04 12:37:51 PM PST 24	Feb 04 12:37:57 PM PST 24	73008074 ps
T72	/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.2679073499	Feb 04 12:37:31 PM PST 24	Feb 04 12:37:45 PM PST 24	187334798 ps
T145	/workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.98926542	Feb 04 12:37:39 PM PST 24	Feb 04 12:37:47 PM PST 24	112447963 ps
T146	/workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.3874881902	Feb 04 12:37:45 PM PST 24	Feb 04 12:37:53 PM PST 24	38918109 ps
T147	/workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.1740276466	Feb 04 12:37:41 PM PST 24	Feb 04 12:37:48 PM PST 24	79009125 ps
T148	/workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.2908753560	Feb 04 12:37:31 PM PST 24	Feb 04 12:37:45 PM PST 24	610804929 ps
T55	/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.769886525	Feb 04 12:37:15 PM PST 24	Feb 04 12:37:31 PM PST 24	176418797 ps
T87	/workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.1431396317	Feb 04 12:37:35 PM PST 24	Feb 04 12:37:54 PM PST 24	625306645 ps
T149	/workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.3303437883	Feb 04 12:37:56 PM PST 24	Feb 04 12:38:03 PM PST 24	180521114 ps
T150	/workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.1739560425	Feb 04 12:37:49 PM PST 24	Feb 04 12:37:55 PM PST 24	74869775 ps
T65	/workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.3678367478	Feb 04 12:37:18 PM PST 24	Feb 04 12:37:33 PM PST 24	67717438 ps
T86	/workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.426586420	Feb 04 12:37:30 PM PST 24	Feb 04 12:38:00 PM PST 24	1216371409 ps
T67	/workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.366914357	Feb 04 12:37:22 PM PST 24	Feb 04 12:37:38 PM PST 24	697435468 ps
T151	/workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.2714383151	Feb 04 12:37:10 PM PST 24	Feb 04 12:37:27 PM PST 24	127478566 ps
T152	/workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.742676156	Feb 04 12:37:16 PM PST 24	Feb 04 12:37:31 PM PST 24	516295743 ps
T153	/workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.901540377	Feb 04 12:37:20 PM PST 24	Feb 04 12:37:33 PM PST 24	59979930 ps
T57	/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.1626189367	Feb 04 12:37:09 PM PST 24	Feb 04 12:37:26 PM PST 24	1499932609 ps
T154	/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.355679429	Feb 04 12:37:37 PM PST 24	Feb 04 12:37:48 PM PST 24	287415044 ps
T66	/workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.828431845	Feb 04 12:37:41 PM PST 24	Feb 04 12:37:51 PM PST 24	504547705 ps
T155	/workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.3103090780	Feb 04 12:37:36 PM PST 24	Feb 04 12:37:49 PM PST 24	224444828 ps
T156	/workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.735907533	Feb 04 12:37:41 PM PST 24	Feb 04 12:37:49 PM PST 24	557452458 ps
T157	/workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.4054803677	Feb 04 12:37:44 PM PST 24	Feb 04 12:37:53 PM PST 24	661421389 ps
T56	/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.4214782361	Feb 04 12:37:12 PM PST 24	Feb 04 12:37:33 PM PST 24	2025191294 ps
T158	/workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.3501578924	Feb 04 12:37:49 PM PST 24	Feb 04 12:37:55 PM PST 24	143207335 ps
T159	/workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.1388549874	Feb 04 12:37:46 PM PST 24	Feb 04 12:37:54 PM PST 24	40267712 ps
T160	/workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.2391926874	Feb 04 12:37:21 PM PST 24	Feb 04 12:37:33 PM PST 24	44922398 ps
T161	/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.1557953235	Feb 04 12:37:10 PM PST 24	Feb 04 12:37:31 PM PST 24	1215546096 ps
T162	/workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.854982147	Feb 04 12:37:30 PM PST 24	Feb 04 12:37:43 PM PST 24	53101125 ps
T163	/workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.3234954322	Feb 04 12:37:32 PM PST 24	Feb 04 12:37:46 PM PST 24	570155307 ps
T164	/workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.72474829	Feb 04 12:37:40 PM PST 24	Feb 04 12:37:48 PM PST 24	38527369 ps
T165	/workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.3531504525	Feb 04 12:37:48 PM PST 24	Feb 04 12:37:55 PM PST 24	39094790 ps
T166	/workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.1287112125	Feb 04 12:37:51 PM PST 24	Feb 04 12:37:57 PM PST 24	142150673 ps
T167	/workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.1174308472	Feb 04 12:37:18 PM PST 24	Feb 04 12:37:34 PM PST 24	233999401 ps
T168	/workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.1237757634	Feb 04 12:37:43 PM PST 24	Feb 04 12:37:52 PM PST 24	525689308 ps
T81	/workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.1636625120	Feb 04 12:37:31 PM PST 24	Feb 04 12:38:01 PM PST 24	2549757586 ps
T169	/workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.1962095628	Feb 04 12:37:35 PM PST 24	Feb 04 12:37:47 PM PST 24	126137156 ps
T73	/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.3990141069	Feb 04 12:37:15 PM PST 24	Feb 04 12:37:31 PM PST 24	234246783 ps
T170	/workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.4234671620	Feb 04 12:37:41 PM PST 24	Feb 04 12:37:48 PM PST 24	44877245 ps
T171	/workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.2295945033	Feb 04 12:37:00 PM PST 24	Feb 04 12:37:16 PM PST 24	42588818 ps
T172	/workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.192454113	Feb 04 12:37:47 PM PST 24	Feb 04 12:37:54 PM PST 24	74852227 ps
T173	/workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.577589052	Feb 04 12:37:51 PM PST 24	Feb 04 12:37:56 PM PST 24	82192733 ps
T174	/workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.1991764754	Feb 04 12:37:33 PM PST 24	Feb 04 12:37:46 PM PST 24	41950651 ps

Test location	/workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.1282584298
Short name	T1
Test name
Test status
Simulation time	2527848307 ps
CPU time	10.06 seconds
Started	Feb 04 12:37:53 PM PST 24
Finished	Feb 04 12:38:07 PM PST 24
Peak memory	241192 kb
Host	smart-f8926f13-38d5-47e2-8930-bd0352654f94
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282584298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_i ntg_err.1282584298
Directory	/workspace/13.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.3657466658
Short name	T15
Test name
Test status
Simulation time	600422873 ps
CPU time	5.78 seconds
Started	Feb 04 12:37:56 PM PST 24
Finished	Feb 04 12:38:05 PM PST 24
Peak memory	238012 kb
Host	smart-c6c56174-808d-4ee4-ae8c-7917d5d12e21
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657466658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_errors.3657466658
Directory	/workspace/16.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.2486052909
Short name	T45
Test name
Test status
Simulation time	80304861 ps
CPU time	1.42 seconds
Started	Feb 04 12:37:39 PM PST 24
Finished	Feb 04 12:37:47 PM PST 24
Peak memory	229952 kb
Host	smart-db1d68b7-889a-4417-97df-f3079730f3b5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486052909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_intr_test.2486052909
Directory	/workspace/24.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.3046773682
Short name	T28
Test name
Test status
Simulation time	38711775 ps
CPU time	1.45 seconds
Started	Feb 04 12:37:38 PM PST 24
Finished	Feb 04 12:37:47 PM PST 24
Peak memory	229612 kb
Host	smart-5e0d09c9-8e29-4f8b-b2c5-29dbfa6993fd
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046773682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_rw.3046773682
Directory	/workspace/8.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.1562626424
Short name	T26
Test name
Test status
Simulation time	1611354983 ps
CPU time	17.38 seconds
Started	Feb 04 12:37:36 PM PST 24
Finished	Feb 04 12:38:02 PM PST 24
Peak memory	241224 kb
Host	smart-8af7ac97-f154-492d-980e-cfe13e2119a9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562626424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_in tg_err.1562626424
Directory	/workspace/8.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.1815025582
Short name	T51
Test name
Test status
Simulation time	189119729 ps
CPU time	2.29 seconds
Started	Feb 04 12:37:29 PM PST 24
Finished	Feb 04 12:37:43 PM PST 24
Peak memory	229712 kb
Host	smart-c1b52e3b-1847-4a98-a6a6-889e6f67cedf
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815025582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_hw_r eset.1815025582
Directory	/workspace/4.otp_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.2149700802
Short name	T8
Test name
Test status
Simulation time	568914207 ps
CPU time	1.97 seconds
Started	Feb 04 12:37:39 PM PST 24
Finished	Feb 04 12:37:48 PM PST 24
Peak memory	229956 kb
Host	smart-5e2ee001-420c-42f6-90a3-058831c6b575
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149700802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_intr_test.2149700802
Directory	/workspace/21.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.2085078450
Short name	T11
Test name
Test status
Simulation time	1477798485 ps
CPU time	9.17 seconds
Started	Feb 04 12:37:31 PM PST 24
Finished	Feb 04 12:37:52 PM PST 24
Peak memory	230100 kb
Host	smart-f97ac52d-35d7-4fe1-bb1b-fac7ccc7f362
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085078450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_i ntg_err.2085078450
Directory	/workspace/14.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.43534074
Short name	T79
Test name
Test status
Simulation time	2652824837 ps
CPU time	9.56 seconds
Started	Feb 04 12:37:21 PM PST 24
Finished	Feb 04 12:37:41 PM PST 24
Peak memory	244140 kb
Host	smart-14755864-2691-4e05-93cf-bf62f74816c2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43534074 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_errors.43534074
Directory	/workspace/11.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.2585220779
Short name	T71
Test name
Test status
Simulation time	185312532 ps
CPU time	2.23 seconds
Started	Feb 04 12:37:10 PM PST 24
Finished	Feb 04 12:37:28 PM PST 24
Peak memory	229664 kb
Host	smart-7a72d42f-b793-46d8-a7c6-8bb8aeb24583
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585220779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_hw_r eset.2585220779
Directory	/workspace/0.otp_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.1636625120
Short name	T81
Test name
Test status
Simulation time	2549757586 ps
CPU time	18.13 seconds
Started	Feb 04 12:37:31 PM PST 24
Finished	Feb 04 12:38:01 PM PST 24
Peak memory	238308 kb
Host	smart-df9c6468-af6b-4997-a9bc-4e9a91c05cd8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636625120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_i ntg_err.1636625120
Directory	/workspace/16.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.2529456651
Short name	T61
Test name
Test status
Simulation time	98505978 ps
CPU time	2.44 seconds
Started	Feb 04 12:37:18 PM PST 24
Finished	Feb 04 12:37:32 PM PST 24
Peak memory	237996 kb
Host	smart-0a166d91-2cb9-4087-8b61-68c871196d86
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529456651 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_mem_rw_with_rand_reset.2529456651
Directory	/workspace/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.1207725461
Short name	T12
Test name
Test status
Simulation time	936560444 ps
CPU time	2.86 seconds
Started	Feb 04 12:37:27 PM PST 24
Finished	Feb 04 12:37:35 PM PST 24
Peak memory	238088 kb
Host	smart-e8b5036d-80d8-492f-a831-b9bebca6ef94
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207725461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ ctrl_same_csr_outstanding.1207725461
Directory	/workspace/13.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.1372089888
Short name	T52
Test name
Test status
Simulation time	45392484 ps
CPU time	1.6 seconds
Started	Feb 04 12:37:09 PM PST 24
Finished	Feb 04 12:37:25 PM PST 24
Peak memory	229660 kb
Host	smart-050591bb-9204-42a1-975d-ef251d688e1b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372089888 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_rw.1372089888
Directory	/workspace/0.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.366914357
Short name	T67
Test name
Test status
Simulation time	697435468 ps
CPU time	7.02 seconds
Started	Feb 04 12:37:22 PM PST 24
Finished	Feb 04 12:37:38 PM PST 24
Peak memory	243768 kb
Host	smart-a652e1e7-6a25-46e2-b638-d27e6e41d502
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366914357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_errors.366914357
Directory	/workspace/8.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.3265628462
Short name	T84
Test name
Test status
Simulation time	589558011 ps
CPU time	9.04 seconds
Started	Feb 04 12:37:28 PM PST 24
Finished	Feb 04 12:37:48 PM PST 24
Peak memory	240836 kb
Host	smart-f1fc49d7-0c04-47fa-915c-571eaae8382e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265628462 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_i ntg_err.3265628462
Directory	/workspace/18.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.628485635
Short name	T85
Test name
Test status
Simulation time	18466177854 ps
CPU time	21.55 seconds
Started	Feb 04 12:37:39 PM PST 24
Finished	Feb 04 12:38:07 PM PST 24
Peak memory	241832 kb
Host	smart-d5272d95-a0f1-43bc-abc7-a230efa3fc86
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628485635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_in tg_err.628485635
Directory	/workspace/10.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.3382435610
Short name	T5
Test name
Test status
Simulation time	10850157969 ps
CPU time	13.44 seconds
Started	Feb 04 12:37:37 PM PST 24
Finished	Feb 04 12:37:59 PM PST 24
Peak memory	229920 kb
Host	smart-94592eb6-93f9-496e-83d3-4f210fa44e6f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382435610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_i ntg_err.3382435610
Directory	/workspace/15.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.396537730
Short name	T34
Test name
Test status
Simulation time	607237185 ps
CPU time	9.07 seconds
Started	Feb 04 12:37:56 PM PST 24
Finished	Feb 04 12:38:09 PM PST 24
Peak memory	240596 kb
Host	smart-0c70888a-382e-4f8e-bb59-9310fe903972
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396537730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_in tg_err.396537730
Directory	/workspace/17.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.2896454329
Short name	T3
Test name
Test status
Simulation time	1349997088 ps
CPU time	11.06 seconds
Started	Feb 04 12:37:39 PM PST 24
Finished	Feb 04 12:37:57 PM PST 24
Peak memory	229924 kb
Host	smart-225b6ded-3d37-4ab4-9be8-fb3e49045bff
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896454329 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_in tg_err.2896454329
Directory	/workspace/6.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.3990141069
Short name	T73
Test name
Test status
Simulation time	234246783 ps
CPU time	1.84 seconds
Started	Feb 04 12:37:15 PM PST 24
Finished	Feb 04 12:37:31 PM PST 24
Peak memory	229596 kb
Host	smart-2c551c97-2d76-45a6-b833-f6e6f7a3c585
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990141069 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_hw_r eset.3990141069
Directory	/workspace/1.otp_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.3421714847
Short name	T80
Test name
Test status
Simulation time	144106961 ps
CPU time	5.16 seconds
Started	Feb 04 12:37:32 PM PST 24
Finished	Feb 04 12:37:50 PM PST 24
Peak memory	238008 kb
Host	smart-cdd6b344-f5d2-45c7-a5ca-bd79dd7d59e5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421714847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_errors.3421714847
Directory	/workspace/6.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.4237728119
Short name	T16
Test name
Test status
Simulation time	98604033 ps
CPU time	2.89 seconds
Started	Feb 04 12:37:08 PM PST 24
Finished	Feb 04 12:37:21 PM PST 24
Peak memory	237888 kb
Host	smart-4d849efb-8b29-43db-9943-43db8aed9653
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237728119 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_errors.4237728119
Directory	/workspace/0.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.1626189367
Short name	T57
Test name
Test status
Simulation time	1499932609 ps
CPU time	2.25 seconds
Started	Feb 04 12:37:09 PM PST 24
Finished	Feb 04 12:37:26 PM PST 24
Peak memory	229704 kb
Host	smart-94590906-17f9-4a67-89f0-dff13732f0fe
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626189367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_hw_r eset.1626189367
Directory	/workspace/2.otp_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.1328962040
Short name	T77
Test name
Test status
Simulation time	1693153780 ps
CPU time	10.79 seconds
Started	Feb 04 12:37:15 PM PST 24
Finished	Feb 04 12:37:40 PM PST 24
Peak memory	230148 kb
Host	smart-1aa688ed-4083-44f1-a238-7bca7c520153
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328962040 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_in tg_err.1328962040
Directory	/workspace/2.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.163773156
Short name	T38
Test name
Test status
Simulation time	190908610 ps
CPU time	2.69 seconds
Started	Feb 04 12:37:02 PM PST 24
Finished	Feb 04 12:37:16 PM PST 24
Peak memory	237904 kb
Host	smart-5291a24c-46af-4717-9fc8-8bb98a0f031b
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163773156 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_alias ing.163773156
Directory	/workspace/0.otp_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.3236359586
Short name	T123
Test name
Test status
Simulation time	7433957334 ps
CPU time	13.51 seconds
Started	Feb 04 12:37:18 PM PST 24
Finished	Feb 04 12:37:43 PM PST 24
Peak memory	237984 kb
Host	smart-7b661821-73d1-4182-ab74-3879a86098cd
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236359586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_bit_ bash.3236359586
Directory	/workspace/0.otp_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.2295945033
Short name	T171
Test name
Test status
Simulation time	42588818 ps
CPU time	1.43 seconds
Started	Feb 04 12:37:00 PM PST 24
Finished	Feb 04 12:37:16 PM PST 24
Peak memory	229748 kb
Host	smart-c69d2825-ee27-4711-b354-424b800a3288
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295945033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_intr_test.2295945033
Directory	/workspace/0.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.2714383151
Short name	T151
Test name
Test status
Simulation time	127478566 ps
CPU time	1.3 seconds
Started	Feb 04 12:37:10 PM PST 24
Finished	Feb 04 12:37:27 PM PST 24
Peak memory	229496 kb
Host	smart-93b7d7d6-a339-440b-9b1b-c4cbe6ce9af2
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714383151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctr l_mem_partial_access.2714383151
Directory	/workspace/0.otp_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.306881326
Short name	T139
Test name
Test status
Simulation time	70613722 ps
CPU time	1.3 seconds
Started	Feb 04 12:37:13 PM PST 24
Finished	Feb 04 12:37:29 PM PST 24
Peak memory	229376 kb
Host	smart-6a1b0352-c41a-4eec-8066-8fc5c2ac3ee2
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306881326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_walk. 306881326
Directory	/workspace/0.otp_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.421564856
Short name	T58
Test name
Test status
Simulation time	882396423 ps
CPU time	3.01 seconds
Started	Feb 04 12:37:10 PM PST 24
Finished	Feb 04 12:37:29 PM PST 24
Peak memory	237996 kb
Host	smart-b38ce1d7-3eca-49a1-9c87-cafe5c3684b3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421564856 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ct rl_same_csr_outstanding.421564856
Directory	/workspace/0.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.2634927775
Short name	T25
Test name
Test status
Simulation time	9409232463 ps
CPU time	12.23 seconds
Started	Feb 04 12:37:07 PM PST 24
Finished	Feb 04 12:37:30 PM PST 24
Peak memory	241532 kb
Host	smart-9ee3bb6f-7557-4ed4-89b9-bc78ec40e9db
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634927775 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_in tg_err.2634927775
Directory	/workspace/0.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.4214782361
Short name	T56
Test name
Test status
Simulation time	2025191294 ps
CPU time	5.82 seconds
Started	Feb 04 12:37:12 PM PST 24
Finished	Feb 04 12:37:33 PM PST 24
Peak memory	237876 kb
Host	smart-e45179d2-1499-4a70-b8c7-c745abebd607
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214782361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_alia sing.4214782361
Directory	/workspace/1.otp_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.3689818905
Short name	T27
Test name
Test status
Simulation time	406602516 ps
CPU time	8.66 seconds
Started	Feb 04 12:37:08 PM PST 24
Finished	Feb 04 12:37:27 PM PST 24
Peak memory	229692 kb
Host	smart-e2dc73a7-674c-4bcc-907d-c4a1da888ddc
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689818905 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_bit_ bash.3689818905
Directory	/workspace/1.otp_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.2365835092
Short name	T19
Test name
Test status
Simulation time	392588031 ps
CPU time	2.86 seconds
Started	Feb 04 12:37:12 PM PST 24
Finished	Feb 04 12:37:30 PM PST 24
Peak memory	245272 kb
Host	smart-f9f4939d-47e7-4fe2-b63e-bef4dcbbe43e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365835092 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_mem_rw_with_rand_reset.2365835092
Directory	/workspace/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.769886525
Short name	T55
Test name
Test status
Simulation time	176418797 ps
CPU time	1.63 seconds
Started	Feb 04 12:37:15 PM PST 24
Finished	Feb 04 12:37:31 PM PST 24
Peak memory	229488 kb
Host	smart-bc7be445-1f7f-4075-9348-cd1cc766a844
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769886525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_rw.769886525
Directory	/workspace/1.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.2317009119
Short name	T113
Test name
Test status
Simulation time	73717331 ps
CPU time	1.37 seconds
Started	Feb 04 12:37:11 PM PST 24
Finished	Feb 04 12:37:28 PM PST 24
Peak memory	229752 kb
Host	smart-84602d5c-5fde-406d-81dd-eda63ac90edf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317009119 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_intr_test.2317009119
Directory	/workspace/1.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.597384609
Short name	T98
Test name
Test status
Simulation time	531369331 ps
CPU time	1.92 seconds
Started	Feb 04 12:37:10 PM PST 24
Finished	Feb 04 12:37:28 PM PST 24
Peak memory	229484 kb
Host	smart-8c7d4549-1724-49f1-831d-dd5962513423
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597384609 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl _mem_partial_access.597384609
Directory	/workspace/1.otp_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.532144652
Short name	T136
Test name
Test status
Simulation time	141595998 ps
CPU time	1.21 seconds
Started	Feb 04 12:37:13 PM PST 24
Finished	Feb 04 12:37:29 PM PST 24
Peak memory	229444 kb
Host	smart-58a856e4-53b5-42f1-b65b-a7f1b94176d1
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532144652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_walk. 532144652
Directory	/workspace/1.otp_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.2514466825
Short name	T40
Test name
Test status
Simulation time	295657253 ps
CPU time	3.78 seconds
Started	Feb 04 12:37:29 PM PST 24
Finished	Feb 04 12:37:44 PM PST 24
Peak memory	237980 kb
Host	smart-26aa9b98-8ac8-49c8-a637-b471d80b55ef
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514466825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_c trl_same_csr_outstanding.2514466825
Directory	/workspace/1.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.1174308472
Short name	T167
Test name
Test status
Simulation time	233999401 ps
CPU time	4.12 seconds
Started	Feb 04 12:37:18 PM PST 24
Finished	Feb 04 12:37:34 PM PST 24
Peak memory	238044 kb
Host	smart-c7ca12b0-535c-4ce6-b558-52ecc358208b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174308472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_errors.1174308472
Directory	/workspace/1.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.1084942451
Short name	T101
Test name
Test status
Simulation time	1418940369 ps
CPU time	9.11 seconds
Started	Feb 04 12:37:12 PM PST 24
Finished	Feb 04 12:37:36 PM PST 24
Peak memory	240700 kb
Host	smart-80bb4822-52ab-4e7a-958b-929423b20694
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084942451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_in tg_err.1084942451
Directory	/workspace/1.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.228914309
Short name	T142
Test name
Test status
Simulation time	64452202 ps
CPU time	1.89 seconds
Started	Feb 04 12:37:19 PM PST 24
Finished	Feb 04 12:37:33 PM PST 24
Peak memory	238044 kb
Host	smart-a88a5525-defe-4e1a-821c-5070cfffbe4c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228914309 -assert nopostproc +UVM_TESTNAME= otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_mem_rw_with_rand_reset.228914309
Directory	/workspace/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.1727632673
Short name	T97
Test name
Test status
Simulation time	145584719 ps
CPU time	1.44 seconds
Started	Feb 04 12:37:19 PM PST 24
Finished	Feb 04 12:37:32 PM PST 24
Peak memory	229436 kb
Host	smart-ef0f8e25-0a72-44b1-a7fa-ada7d9973f1c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727632673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_rw.1727632673
Directory	/workspace/10.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.1991764754
Short name	T174
Test name
Test status
Simulation time	41950651 ps
CPU time	1.4 seconds
Started	Feb 04 12:37:33 PM PST 24
Finished	Feb 04 12:37:46 PM PST 24
Peak memory	229656 kb
Host	smart-03dd4d84-48e3-4c11-80fb-b284d48ccd3a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991764754 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_intr_test.1991764754
Directory	/workspace/10.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.1562485611
Short name	T105
Test name
Test status
Simulation time	45407916 ps
CPU time	1.79 seconds
Started	Feb 04 12:37:38 PM PST 24
Finished	Feb 04 12:37:48 PM PST 24
Peak memory	238180 kb
Host	smart-4829154d-2bdc-4fff-8b1f-aed56e9fd30e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562485611 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ ctrl_same_csr_outstanding.1562485611
Directory	/workspace/10.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.533649204
Short name	T22
Test name
Test status
Simulation time	375898149 ps
CPU time	3.61 seconds
Started	Feb 04 12:37:37 PM PST 24
Finished	Feb 04 12:37:49 PM PST 24
Peak memory	237992 kb
Host	smart-197d6a2e-6594-45e9-8597-51d636dc3a9b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533649204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_errors.533649204
Directory	/workspace/10.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.1005925087
Short name	T62
Test name
Test status
Simulation time	133576397 ps
CPU time	2.02 seconds
Started	Feb 04 12:37:20 PM PST 24
Finished	Feb 04 12:37:33 PM PST 24
Peak memory	238000 kb
Host	smart-479d4bec-ae95-4183-930d-692d47fe5541
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005925087 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_mem_rw_with_rand_reset.1005925087
Directory	/workspace/11.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.1913634575
Short name	T31
Test name
Test status
Simulation time	572677092 ps
CPU time	1.67 seconds
Started	Feb 04 12:37:40 PM PST 24
Finished	Feb 04 12:37:48 PM PST 24
Peak memory	229680 kb
Host	smart-5f4e9484-99cb-4ceb-ac91-4e366ce57aac
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913634575 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_rw.1913634575
Directory	/workspace/11.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.2391926874
Short name	T160
Test name
Test status
Simulation time	44922398 ps
CPU time	1.44 seconds
Started	Feb 04 12:37:21 PM PST 24
Finished	Feb 04 12:37:33 PM PST 24
Peak memory	229764 kb
Host	smart-6abb8f66-251f-467e-aede-eb90e1f3460d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391926874 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_intr_test.2391926874
Directory	/workspace/11.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.559038237
Short name	T32
Test name
Test status
Simulation time	154158601 ps
CPU time	2.79 seconds
Started	Feb 04 12:37:23 PM PST 24
Finished	Feb 04 12:37:34 PM PST 24
Peak memory	238024 kb
Host	smart-026b481e-34ab-401d-ba67-6b12db3e5f9f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559038237 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_c trl_same_csr_outstanding.559038237
Directory	/workspace/11.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.3547964058
Short name	T37
Test name
Test status
Simulation time	1456012870 ps
CPU time	18.94 seconds
Started	Feb 04 12:37:35 PM PST 24
Finished	Feb 04 12:38:04 PM PST 24
Peak memory	241240 kb
Host	smart-c0e5d695-b697-42ea-929e-3f00780c8a6b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547964058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_i ntg_err.3547964058
Directory	/workspace/11.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.3810868070
Short name	T134
Test name
Test status
Simulation time	202837568 ps
CPU time	2.26 seconds
Started	Feb 04 12:37:35 PM PST 24
Finished	Feb 04 12:37:48 PM PST 24
Peak memory	238008 kb
Host	smart-e2657eda-f1ec-4d31-a4bd-23aaa8e908c7
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810868070 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_mem_rw_with_rand_reset.3810868070
Directory	/workspace/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.1287112125
Short name	T166
Test name
Test status
Simulation time	142150673 ps
CPU time	1.49 seconds
Started	Feb 04 12:37:51 PM PST 24
Finished	Feb 04 12:37:57 PM PST 24
Peak memory	229568 kb
Host	smart-5df3121b-619b-4767-8331-dbe598dad30f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287112125 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_rw.1287112125
Directory	/workspace/12.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.2458923525
Short name	T102
Test name
Test status
Simulation time	35590798 ps
CPU time	1.32 seconds
Started	Feb 04 12:37:39 PM PST 24
Finished	Feb 04 12:37:47 PM PST 24
Peak memory	229668 kb
Host	smart-45ff73df-e3ae-4474-b0a8-bd12b009fc21
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458923525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_intr_test.2458923525
Directory	/workspace/12.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.798305123
Short name	T39
Test name
Test status
Simulation time	56577771 ps
CPU time	1.83 seconds
Started	Feb 04 12:37:28 PM PST 24
Finished	Feb 04 12:37:38 PM PST 24
Peak memory	237880 kb
Host	smart-4c477168-c9a4-4e8b-9383-3a5f777338e8
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798305123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_c trl_same_csr_outstanding.798305123
Directory	/workspace/12.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.1944568906
Short name	T35
Test name
Test status
Simulation time	122427454 ps
CPU time	3.19 seconds
Started	Feb 04 12:37:22 PM PST 24
Finished	Feb 04 12:37:34 PM PST 24
Peak memory	238104 kb
Host	smart-4d703159-23be-4162-b469-a20117c49702
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944568906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_errors.1944568906
Directory	/workspace/12.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.1431396317
Short name	T87
Test name
Test status
Simulation time	625306645 ps
CPU time	9.36 seconds
Started	Feb 04 12:37:35 PM PST 24
Finished	Feb 04 12:37:54 PM PST 24
Peak memory	240712 kb
Host	smart-574cbc59-acf7-44cc-b837-c9670b08d131
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431396317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_i ntg_err.1431396317
Directory	/workspace/12.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.1373559883
Short name	T126
Test name
Test status
Simulation time	203292196 ps
CPU time	2.22 seconds
Started	Feb 04 12:37:49 PM PST 24
Finished	Feb 04 12:37:56 PM PST 24
Peak memory	237996 kb
Host	smart-cfa00ed5-39fc-4eb2-bbc0-f538a3119284
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373559883 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_mem_rw_with_rand_reset.1373559883
Directory	/workspace/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.4054803677
Short name	T157
Test name
Test status
Simulation time	661421389 ps
CPU time	1.64 seconds
Started	Feb 04 12:37:44 PM PST 24
Finished	Feb 04 12:37:53 PM PST 24
Peak memory	229668 kb
Host	smart-26924979-5ff2-4ce7-a3f4-a37e9dad647c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054803677 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_rw.4054803677
Directory	/workspace/13.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.159403247
Short name	T91
Test name
Test status
Simulation time	74420450 ps
CPU time	1.39 seconds
Started	Feb 04 12:37:51 PM PST 24
Finished	Feb 04 12:37:57 PM PST 24
Peak memory	229676 kb
Host	smart-6b656fad-bca5-41e1-a9a0-99daac5c4583
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159403247 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_intr_test.159403247
Directory	/workspace/13.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.3261744511
Short name	T119
Test name
Test status
Simulation time	121644020 ps
CPU time	4.68 seconds
Started	Feb 04 12:37:40 PM PST 24
Finished	Feb 04 12:37:51 PM PST 24
Peak memory	238108 kb
Host	smart-0e66218d-cb67-49c9-861e-ffa63931a0f3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261744511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_errors.3261744511
Directory	/workspace/13.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.2324843440
Short name	T96
Test name
Test status
Simulation time	213868527 ps
CPU time	2.36 seconds
Started	Feb 04 12:37:56 PM PST 24
Finished	Feb 04 12:38:02 PM PST 24
Peak memory	237988 kb
Host	smart-77231791-2941-469e-b655-2d3e8e96c970
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324843440 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_mem_rw_with_rand_reset.2324843440
Directory	/workspace/14.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.3234954322
Short name	T163
Test name
Test status
Simulation time	570155307 ps
CPU time	2.2 seconds
Started	Feb 04 12:37:32 PM PST 24
Finished	Feb 04 12:37:46 PM PST 24
Peak memory	229608 kb
Host	smart-c6e4b292-f196-42cf-9e60-cf30579dfdfc
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234954322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_rw.3234954322
Directory	/workspace/14.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.2908753560
Short name	T148
Test name
Test status
Simulation time	610804929 ps
CPU time	2.08 seconds
Started	Feb 04 12:37:31 PM PST 24
Finished	Feb 04 12:37:45 PM PST 24
Peak memory	229716 kb
Host	smart-b054b134-3c64-4899-9b04-da987b2b4b38
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908753560 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_intr_test.2908753560
Directory	/workspace/14.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.2773654584
Short name	T14
Test name
Test status
Simulation time	108614638 ps
CPU time	2.17 seconds
Started	Feb 04 12:37:56 PM PST 24
Finished	Feb 04 12:38:02 PM PST 24
Peak memory	237836 kb
Host	smart-da386003-18e9-4ee7-ab35-bd1debefb879
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773654584 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ ctrl_same_csr_outstanding.2773654584
Directory	/workspace/14.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.3035339086
Short name	T75
Test name
Test status
Simulation time	2256383781 ps
CPU time	6.86 seconds
Started	Feb 04 12:37:40 PM PST 24
Finished	Feb 04 12:37:53 PM PST 24
Peak memory	238016 kb
Host	smart-050ad316-3e92-4d55-b65f-7213c111bd8b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035339086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_errors.3035339086
Directory	/workspace/14.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.2609729414
Short name	T137
Test name
Test status
Simulation time	1516354631 ps
CPU time	2.64 seconds
Started	Feb 04 12:37:34 PM PST 24
Finished	Feb 04 12:37:48 PM PST 24
Peak memory	246168 kb
Host	smart-1520ef1a-302b-46ab-8d92-720380d70dd2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609729414 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_mem_rw_with_rand_reset.2609729414
Directory	/workspace/15.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.1083857436
Short name	T128
Test name
Test status
Simulation time	45464794 ps
CPU time	1.56 seconds
Started	Feb 04 12:37:55 PM PST 24
Finished	Feb 04 12:38:01 PM PST 24
Peak memory	229708 kb
Host	smart-43812fdf-5014-49bd-bafe-60d9bbcf6434
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083857436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_rw.1083857436
Directory	/workspace/15.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.3043939827
Short name	T6
Test name
Test status
Simulation time	38102342 ps
CPU time	1.31 seconds
Started	Feb 04 12:37:56 PM PST 24
Finished	Feb 04 12:38:01 PM PST 24
Peak memory	229632 kb
Host	smart-322af4d1-e474-4da7-a248-923ae675b8ee
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043939827 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_intr_test.3043939827
Directory	/workspace/15.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.3000415985
Short name	T125
Test name
Test status
Simulation time	54454699 ps
CPU time	2.18 seconds
Started	Feb 04 12:37:37 PM PST 24
Finished	Feb 04 12:37:48 PM PST 24
Peak memory	237888 kb
Host	smart-aa1b19a2-35e6-4b10-b693-0634d550fe25
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000415985 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ ctrl_same_csr_outstanding.3000415985
Directory	/workspace/15.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.1991926442
Short name	T36
Test name
Test status
Simulation time	561308029 ps
CPU time	5.73 seconds
Started	Feb 04 12:37:43 PM PST 24
Finished	Feb 04 12:37:56 PM PST 24
Peak memory	238076 kb
Host	smart-d16d6236-0ea7-491d-848c-37aba8d1f574
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991926442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_errors.1991926442
Directory	/workspace/15.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.1962095628
Short name	T169
Test name
Test status
Simulation time	126137156 ps
CPU time	1.98 seconds
Started	Feb 04 12:37:35 PM PST 24
Finished	Feb 04 12:37:47 PM PST 24
Peak memory	237956 kb
Host	smart-6dffbb35-e8a6-4618-a83a-aa1fa83e1759
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962095628 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_mem_rw_with_rand_reset.1962095628
Directory	/workspace/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.2038639436
Short name	T44
Test name
Test status
Simulation time	41175675 ps
CPU time	1.6 seconds
Started	Feb 04 12:37:44 PM PST 24
Finished	Feb 04 12:37:53 PM PST 24
Peak memory	229600 kb
Host	smart-c9eae986-c3c7-4cd8-beb3-39f8c86c00d4
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038639436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_rw.2038639436
Directory	/workspace/16.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.2849395476
Short name	T70
Test name
Test status
Simulation time	41983062 ps
CPU time	1.32 seconds
Started	Feb 04 12:37:37 PM PST 24
Finished	Feb 04 12:37:47 PM PST 24
Peak memory	229708 kb
Host	smart-9b597979-d656-45b3-8dc4-ca7c7181f830
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849395476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_intr_test.2849395476
Directory	/workspace/16.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.1772581279
Short name	T64
Test name
Test status
Simulation time	1050952381 ps
CPU time	2.88 seconds
Started	Feb 04 12:37:28 PM PST 24
Finished	Feb 04 12:37:43 PM PST 24
Peak memory	238212 kb
Host	smart-1a529112-621d-4e27-8e37-12af73d97278
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772581279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ ctrl_same_csr_outstanding.1772581279
Directory	/workspace/16.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.1142270488
Short name	T88
Test name
Test status
Simulation time	129683818 ps
CPU time	1.89 seconds
Started	Feb 04 12:37:28 PM PST 24
Finished	Feb 04 12:37:41 PM PST 24
Peak memory	237980 kb
Host	smart-f874f2ec-f809-4f6a-b2ef-46f8f1962fbc
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142270488 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_mem_rw_with_rand_reset.1142270488
Directory	/workspace/17.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.477355506
Short name	T41
Test name
Test status
Simulation time	77549774 ps
CPU time	1.41 seconds
Started	Feb 04 12:37:28 PM PST 24
Finished	Feb 04 12:37:38 PM PST 24
Peak memory	229664 kb
Host	smart-9d56d645-e981-4632-b353-f70bbbaf7aa7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477355506 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_rw.477355506
Directory	/workspace/17.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.1740276466
Short name	T147
Test name
Test status
Simulation time	79009125 ps
CPU time	1.42 seconds
Started	Feb 04 12:37:41 PM PST 24
Finished	Feb 04 12:37:48 PM PST 24
Peak memory	229748 kb
Host	smart-9350de2c-ff20-4a3d-b0a6-1db7e865b6a8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740276466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_intr_test.1740276466
Directory	/workspace/17.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.2590446810
Short name	T118
Test name
Test status
Simulation time	43693074 ps
CPU time	1.75 seconds
Started	Feb 04 12:37:56 PM PST 24
Finished	Feb 04 12:38:01 PM PST 24
Peak memory	237980 kb
Host	smart-2d8a2ab2-854f-4c44-ab32-4ce42fe66ccc
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590446810 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ ctrl_same_csr_outstanding.2590446810
Directory	/workspace/17.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.4173024249
Short name	T76
Test name
Test status
Simulation time	223739388 ps
CPU time	3.57 seconds
Started	Feb 04 12:37:41 PM PST 24
Finished	Feb 04 12:37:51 PM PST 24
Peak memory	238024 kb
Host	smart-42175c84-3b13-48c1-8679-68578e8c1146
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173024249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_errors.4173024249
Directory	/workspace/17.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.1566837976
Short name	T111
Test name
Test status
Simulation time	100526685 ps
CPU time	3.66 seconds
Started	Feb 04 12:37:48 PM PST 24
Finished	Feb 04 12:37:57 PM PST 24
Peak memory	238068 kb
Host	smart-4459771b-6798-425a-8a3b-286e8fb94d9e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566837976 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_mem_rw_with_rand_reset.1566837976
Directory	/workspace/18.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.3797650438
Short name	T23
Test name
Test status
Simulation time	40207099 ps
CPU time	1.49 seconds
Started	Feb 04 12:37:51 PM PST 24
Finished	Feb 04 12:37:57 PM PST 24
Peak memory	229664 kb
Host	smart-f520f2c8-368e-4c14-9a45-2c7d95980a84
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797650438 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_rw.3797650438
Directory	/workspace/18.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.1005379748
Short name	T104
Test name
Test status
Simulation time	60112724 ps
CPU time	1.48 seconds
Started	Feb 04 12:37:39 PM PST 24
Finished	Feb 04 12:37:47 PM PST 24
Peak memory	229716 kb
Host	smart-8ab94f6a-ecda-46fe-b928-5b367641ad06
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005379748 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_intr_test.1005379748
Directory	/workspace/18.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.3222146924
Short name	T121
Test name
Test status
Simulation time	94041902 ps
CPU time	2.14 seconds
Started	Feb 04 12:37:36 PM PST 24
Finished	Feb 04 12:37:47 PM PST 24
Peak memory	237904 kb
Host	smart-de91553a-58d0-49fb-88a2-74d8c7b534de
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222146924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ ctrl_same_csr_outstanding.3222146924
Directory	/workspace/18.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.3303437883
Short name	T149
Test name
Test status
Simulation time	180521114 ps
CPU time	3.56 seconds
Started	Feb 04 12:37:56 PM PST 24
Finished	Feb 04 12:38:03 PM PST 24
Peak memory	238008 kb
Host	smart-5f3d1290-8e95-448c-9ab5-b33119e9af28
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303437883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_errors.3303437883
Directory	/workspace/18.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.744399842
Short name	T20
Test name
Test status
Simulation time	281144898 ps
CPU time	2.22 seconds
Started	Feb 04 12:37:48 PM PST 24
Finished	Feb 04 12:37:56 PM PST 24
Peak memory	243672 kb
Host	smart-335d515b-5cd1-4673-951c-346e1bd7bb55
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744399842 -assert nopostproc +UVM_TESTNAME= otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_mem_rw_with_rand_reset.744399842
Directory	/workspace/19.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.192454113
Short name	T172
Test name
Test status
Simulation time	74852227 ps
CPU time	1.41 seconds
Started	Feb 04 12:37:47 PM PST 24
Finished	Feb 04 12:37:54 PM PST 24
Peak memory	229632 kb
Host	smart-c9740337-ebbd-4e2f-b165-cc3564cbefdd
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192454113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_rw.192454113
Directory	/workspace/19.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.1739560425
Short name	T150
Test name
Test status
Simulation time	74869775 ps
CPU time	1.35 seconds
Started	Feb 04 12:37:49 PM PST 24
Finished	Feb 04 12:37:55 PM PST 24
Peak memory	229796 kb
Host	smart-4009f704-5bb4-4434-aa28-050355581567
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739560425 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_intr_test.1739560425
Directory	/workspace/19.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.3103090780
Short name	T155
Test name
Test status
Simulation time	224444828 ps
CPU time	3.61 seconds
Started	Feb 04 12:37:36 PM PST 24
Finished	Feb 04 12:37:49 PM PST 24
Peak memory	237952 kb
Host	smart-c8124c07-dfa3-4700-8958-f7ff4a1e84f6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103090780 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ ctrl_same_csr_outstanding.3103090780
Directory	/workspace/19.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.703093223
Short name	T131
Test name
Test status
Simulation time	905052141 ps
CPU time	4.36 seconds
Started	Feb 04 12:37:57 PM PST 24
Finished	Feb 04 12:38:05 PM PST 24
Peak memory	238072 kb
Host	smart-6c70c8a6-202a-4163-9576-19ccd4636d8c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703093223 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_errors.703093223
Directory	/workspace/19.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.2099859918
Short name	T82
Test name
Test status
Simulation time	4667919540 ps
CPU time	17.41 seconds
Started	Feb 04 12:37:50 PM PST 24
Finished	Feb 04 12:38:12 PM PST 24
Peak memory	241724 kb
Host	smart-ef11dbf6-e7a9-467f-879a-32a5754281ca
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099859918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_i ntg_err.2099859918
Directory	/workspace/19.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.4021590458
Short name	T53
Test name
Test status
Simulation time	237956146 ps
CPU time	4.74 seconds
Started	Feb 04 12:37:34 PM PST 24
Finished	Feb 04 12:37:50 PM PST 24
Peak memory	237868 kb
Host	smart-e84a0d8b-f968-4e8d-9d4c-0258a7d27e99
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021590458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_alia sing.4021590458
Directory	/workspace/2.otp_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.1557953235
Short name	T161
Test name
Test status
Simulation time	1215546096 ps
CPU time	5.07 seconds
Started	Feb 04 12:37:10 PM PST 24
Finished	Feb 04 12:37:31 PM PST 24
Peak memory	229616 kb
Host	smart-f19b8d02-1ebb-4a28-a416-aff02ed777d1
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557953235 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_bit_ bash.1557953235
Directory	/workspace/2.otp_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.355679429
Short name	T154
Test name
Test status
Simulation time	287415044 ps
CPU time	2.97 seconds
Started	Feb 04 12:37:37 PM PST 24
Finished	Feb 04 12:37:48 PM PST 24
Peak memory	245780 kb
Host	smart-f72dfb2e-54ee-4148-83e5-5832ecea072e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355679429 -assert nopostproc +UVM_TESTNAME= otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_mem_rw_with_rand_reset.355679429
Directory	/workspace/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.1025878143
Short name	T48
Test name
Test status
Simulation time	134177779 ps
CPU time	1.42 seconds
Started	Feb 04 12:37:16 PM PST 24
Finished	Feb 04 12:37:31 PM PST 24
Peak memory	229604 kb
Host	smart-16ecc976-9c05-4f07-a936-e1a0f7b5b98a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025878143 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_rw.1025878143
Directory	/workspace/2.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.2623016035
Short name	T127
Test name
Test status
Simulation time	62301837 ps
CPU time	1.34 seconds
Started	Feb 04 12:37:13 PM PST 24
Finished	Feb 04 12:37:29 PM PST 24
Peak memory	229728 kb
Host	smart-766b2f23-b70f-42b0-9da3-f9502591b9ce
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623016035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_intr_test.2623016035
Directory	/workspace/2.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.892753262
Short name	T115
Test name
Test status
Simulation time	136567699 ps
CPU time	1.3 seconds
Started	Feb 04 12:37:21 PM PST 24
Finished	Feb 04 12:37:32 PM PST 24
Peak memory	229444 kb
Host	smart-f724cda3-d496-4c82-837a-9782fecac17d
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892753262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl _mem_partial_access.892753262
Directory	/workspace/2.otp_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.742676156
Short name	T152
Test name
Test status
Simulation time	516295743 ps
CPU time	1.68 seconds
Started	Feb 04 12:37:16 PM PST 24
Finished	Feb 04 12:37:31 PM PST 24
Peak memory	229416 kb
Host	smart-a7c914a7-ad9f-4fc4-bb06-79dbc6ea8664
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742676156 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_walk. 742676156
Directory	/workspace/2.otp_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.1878109792
Short name	T60
Test name
Test status
Simulation time	61709988 ps
CPU time	1.8 seconds
Started	Feb 04 12:37:46 PM PST 24
Finished	Feb 04 12:37:54 PM PST 24
Peak memory	237984 kb
Host	smart-a91d25fd-6b1a-4e8d-9d9a-a3c7dcb9995e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878109792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_c trl_same_csr_outstanding.1878109792
Directory	/workspace/2.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.3250454885
Short name	T78
Test name
Test status
Simulation time	1616320698 ps
CPU time	5.61 seconds
Started	Feb 04 12:37:11 PM PST 24
Finished	Feb 04 12:37:32 PM PST 24
Peak memory	238024 kb
Host	smart-d625d772-4b0f-4afe-9365-715479b75cb3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250454885 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_errors.3250454885
Directory	/workspace/2.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.2701573413
Short name	T93
Test name
Test status
Simulation time	39184538 ps
CPU time	1.37 seconds
Started	Feb 04 12:37:47 PM PST 24
Finished	Feb 04 12:37:54 PM PST 24
Peak memory	229764 kb
Host	smart-12e3d415-fb4b-4632-9ed1-9a8dd2ec84d4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701573413 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_intr_test.2701573413
Directory	/workspace/20.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.4165063640
Short name	T103
Test name
Test status
Simulation time	144859877 ps
CPU time	1.32 seconds
Started	Feb 04 12:37:34 PM PST 24
Finished	Feb 04 12:37:46 PM PST 24
Peak memory	229764 kb
Host	smart-215775af-fa8e-49d9-97e5-8c24a4c71fc6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165063640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_intr_test.4165063640
Directory	/workspace/22.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.3966078342
Short name	T140
Test name
Test status
Simulation time	566461146 ps
CPU time	1.52 seconds
Started	Feb 04 12:37:40 PM PST 24
Finished	Feb 04 12:37:48 PM PST 24
Peak memory	229772 kb
Host	smart-5a313c1c-e816-4b0a-ba79-33c4a242445c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966078342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_intr_test.3966078342
Directory	/workspace/23.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.328369771
Short name	T7
Test name
Test status
Simulation time	34343753 ps
CPU time	1.31 seconds
Started	Feb 04 12:37:41 PM PST 24
Finished	Feb 04 12:37:48 PM PST 24
Peak memory	229712 kb
Host	smart-b1cfa6e6-d496-4527-8de8-b3c7b4fa6270
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328369771 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_intr_test.328369771
Directory	/workspace/25.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.2395188171
Short name	T114
Test name
Test status
Simulation time	75786298 ps
CPU time	1.31 seconds
Started	Feb 04 12:37:43 PM PST 24
Finished	Feb 04 12:37:52 PM PST 24
Peak memory	229696 kb
Host	smart-22bda6e9-818e-494e-97ae-b727ed3ef082
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395188171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_intr_test.2395188171
Directory	/workspace/26.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.429386769
Short name	T144
Test name
Test status
Simulation time	73008074 ps
CPU time	1.49 seconds
Started	Feb 04 12:37:51 PM PST 24
Finished	Feb 04 12:37:57 PM PST 24
Peak memory	229720 kb
Host	smart-7f2b66dc-cf87-41aa-8ace-b347760e2759
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429386769 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_intr_test.429386769
Directory	/workspace/27.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.1224341598
Short name	T69
Test name
Test status
Simulation time	580017801 ps
CPU time	1.55 seconds
Started	Feb 04 12:37:38 PM PST 24
Finished	Feb 04 12:37:47 PM PST 24
Peak memory	229712 kb
Host	smart-e49d29ca-82aa-46e7-881c-3c88087dc7db
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224341598 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_intr_test.1224341598
Directory	/workspace/28.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.2967025037
Short name	T110
Test name
Test status
Simulation time	37940882 ps
CPU time	1.44 seconds
Started	Feb 04 12:37:51 PM PST 24
Finished	Feb 04 12:37:57 PM PST 24
Peak memory	229724 kb
Host	smart-ee4c5804-a9d1-4fac-90dd-4d4d646dfe15
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967025037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_intr_test.2967025037
Directory	/workspace/29.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.3427192046
Short name	T29
Test name
Test status
Simulation time	57783628 ps
CPU time	2.65 seconds
Started	Feb 04 12:37:41 PM PST 24
Finished	Feb 04 12:37:52 PM PST 24
Peak memory	229704 kb
Host	smart-824642f4-9449-45a4-b9dd-b80c500d6503
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427192046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_alia sing.3427192046
Directory	/workspace/3.otp_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.1068128480
Short name	T120
Test name
Test status
Simulation time	130937188 ps
CPU time	5.93 seconds
Started	Feb 04 12:37:28 PM PST 24
Finished	Feb 04 12:37:43 PM PST 24
Peak memory	237912 kb
Host	smart-7f88f67d-2f5b-408f-841b-e73374e96057
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068128480 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_bit_ bash.1068128480
Directory	/workspace/3.otp_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.2679073499
Short name	T72
Test name
Test status
Simulation time	187334798 ps
CPU time	2.29 seconds
Started	Feb 04 12:37:31 PM PST 24
Finished	Feb 04 12:37:45 PM PST 24
Peak memory	229648 kb
Host	smart-1c46c0eb-061f-485b-b2fa-9bee9cbe70c6
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679073499 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_hw_r eset.2679073499
Directory	/workspace/3.otp_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.3610974496
Short name	T21
Test name
Test status
Simulation time	73529152 ps
CPU time	2.27 seconds
Started	Feb 04 12:37:32 PM PST 24
Finished	Feb 04 12:37:47 PM PST 24
Peak memory	237964 kb
Host	smart-4180beb4-cfe9-46b5-894e-a29107ce27ea
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610974496 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_mem_rw_with_rand_reset.3610974496
Directory	/workspace/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.3815339669
Short name	T54
Test name
Test status
Simulation time	173437226 ps
CPU time	1.58 seconds
Started	Feb 04 12:37:34 PM PST 24
Finished	Feb 04 12:37:47 PM PST 24
Peak memory	229828 kb
Host	smart-d5db0f4a-191d-49bd-bf59-d63f2767ed6c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815339669 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_rw.3815339669
Directory	/workspace/3.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.1568852954
Short name	T130
Test name
Test status
Simulation time	589460649 ps
CPU time	1.41 seconds
Started	Feb 04 12:37:21 PM PST 24
Finished	Feb 04 12:37:32 PM PST 24
Peak memory	229732 kb
Host	smart-3648614a-52f0-460b-9b95-104928aba824
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568852954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_intr_test.1568852954
Directory	/workspace/3.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.854982147
Short name	T162
Test name
Test status
Simulation time	53101125 ps
CPU time	1.22 seconds
Started	Feb 04 12:37:30 PM PST 24
Finished	Feb 04 12:37:43 PM PST 24
Peak memory	229484 kb
Host	smart-a7f95923-3b46-4582-b229-52e0c4aab3f3
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854982147 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl _mem_partial_access.854982147
Directory	/workspace/3.otp_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.2577993258
Short name	T117
Test name
Test status
Simulation time	73921243 ps
CPU time	1.24 seconds
Started	Feb 04 12:37:19 PM PST 24
Finished	Feb 04 12:37:32 PM PST 24
Peak memory	229448 kb
Host	smart-bbc63748-486b-4844-91a5-b1faabb91c90
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577993258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_walk .2577993258
Directory	/workspace/3.otp_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.3534570995
Short name	T124
Test name
Test status
Simulation time	88016287 ps
CPU time	1.84 seconds
Started	Feb 04 12:37:21 PM PST 24
Finished	Feb 04 12:37:33 PM PST 24
Peak memory	238112 kb
Host	smart-30dade82-6ed9-4949-8b82-e348f05f4f64
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534570995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_c trl_same_csr_outstanding.3534570995
Directory	/workspace/3.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.2983650039
Short name	T74
Test name
Test status
Simulation time	2259820857 ps
CPU time	5.94 seconds
Started	Feb 04 12:37:33 PM PST 24
Finished	Feb 04 12:37:51 PM PST 24
Peak memory	238144 kb
Host	smart-86c92828-fa7a-435b-a184-a7d24d185fdb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983650039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_errors.2983650039
Directory	/workspace/3.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.2892066561
Short name	T83
Test name
Test status
Simulation time	2314043293 ps
CPU time	19.18 seconds
Started	Feb 04 12:37:35 PM PST 24
Finished	Feb 04 12:38:05 PM PST 24
Peak memory	238200 kb
Host	smart-6952b825-48e8-44f9-a10d-322cdcc5d423
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892066561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_in tg_err.2892066561
Directory	/workspace/3.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.3501578924
Short name	T158
Test name
Test status
Simulation time	143207335 ps
CPU time	1.4 seconds
Started	Feb 04 12:37:49 PM PST 24
Finished	Feb 04 12:37:55 PM PST 24
Peak memory	229712 kb
Host	smart-9902d996-fccb-431d-9ef2-86449e19f279
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501578924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_intr_test.3501578924
Directory	/workspace/30.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.3316397458
Short name	T10
Test name
Test status
Simulation time	72048950 ps
CPU time	1.47 seconds
Started	Feb 04 12:37:35 PM PST 24
Finished	Feb 04 12:37:47 PM PST 24
Peak memory	229812 kb
Host	smart-da0ac75a-9d61-48c4-9949-fdbdd73a5956
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316397458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_intr_test.3316397458
Directory	/workspace/31.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.2840931674
Short name	T135
Test name
Test status
Simulation time	68794408 ps
CPU time	1.42 seconds
Started	Feb 04 12:37:44 PM PST 24
Finished	Feb 04 12:37:53 PM PST 24
Peak memory	229712 kb
Host	smart-640a0a7e-b125-4dd8-aa58-3a5fd6931581
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840931674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_intr_test.2840931674
Directory	/workspace/32.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.3233573881
Short name	T89
Test name
Test status
Simulation time	39112419 ps
CPU time	1.44 seconds
Started	Feb 04 12:37:50 PM PST 24
Finished	Feb 04 12:37:56 PM PST 24
Peak memory	229724 kb
Host	smart-086fd8e2-7577-430b-bf36-4ac9f589a9f0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233573881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_intr_test.3233573881
Directory	/workspace/33.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.3483469290
Short name	T46
Test name
Test status
Simulation time	39037176 ps
CPU time	1.31 seconds
Started	Feb 04 12:37:42 PM PST 24
Finished	Feb 04 12:37:51 PM PST 24
Peak memory	229692 kb
Host	smart-d8a7440d-c849-489f-8900-1338002790e2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483469290 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_intr_test.3483469290
Directory	/workspace/34.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.3531504525
Short name	T165
Test name
Test status
Simulation time	39094790 ps
CPU time	1.37 seconds
Started	Feb 04 12:37:48 PM PST 24
Finished	Feb 04 12:37:55 PM PST 24
Peak memory	229780 kb
Host	smart-b325d4bb-64d3-411c-ac3c-908ec0ef792d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531504525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_intr_test.3531504525
Directory	/workspace/35.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.3470397677
Short name	T90
Test name
Test status
Simulation time	566587810 ps
CPU time	1.83 seconds
Started	Feb 04 12:37:37 PM PST 24
Finished	Feb 04 12:37:47 PM PST 24
Peak memory	229776 kb
Host	smart-54459203-f77d-438a-a57c-f1b97a05df8d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470397677 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_intr_test.3470397677
Directory	/workspace/36.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.1961657164
Short name	T129
Test name
Test status
Simulation time	37320369 ps
CPU time	1.38 seconds
Started	Feb 04 12:37:48 PM PST 24
Finished	Feb 04 12:37:55 PM PST 24
Peak memory	229700 kb
Host	smart-30ca4643-88c7-43c5-95e7-3ecd4bcb029c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961657164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_intr_test.1961657164
Directory	/workspace/37.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.3874881902
Short name	T146
Test name
Test status
Simulation time	38918109 ps
CPU time	1.34 seconds
Started	Feb 04 12:37:45 PM PST 24
Finished	Feb 04 12:37:53 PM PST 24
Peak memory	229740 kb
Host	smart-5fba9ba9-f3b5-4d89-9a9b-169843a663d0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874881902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_intr_test.3874881902
Directory	/workspace/38.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.4234671620
Short name	T170
Test name
Test status
Simulation time	44877245 ps
CPU time	1.35 seconds
Started	Feb 04 12:37:41 PM PST 24
Finished	Feb 04 12:37:48 PM PST 24
Peak memory	229764 kb
Host	smart-90dae5c5-2411-411b-b541-6760d10b40a9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234671620 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_intr_test.4234671620
Directory	/workspace/39.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.575625828
Short name	T49
Test name
Test status
Simulation time	63420479 ps
CPU time	3.6 seconds
Started	Feb 04 12:37:35 PM PST 24
Finished	Feb 04 12:37:49 PM PST 24
Peak memory	229672 kb
Host	smart-6c9b3ed6-c5e2-4c18-982c-b83c404d89c3
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575625828 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_alias ing.575625828
Directory	/workspace/4.otp_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.3360463357
Short name	T33
Test name
Test status
Simulation time	550451428 ps
CPU time	5.07 seconds
Started	Feb 04 12:37:19 PM PST 24
Finished	Feb 04 12:37:36 PM PST 24
Peak memory	229476 kb
Host	smart-85b9748f-b0b6-4adf-9415-4b85106dcd2e
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360463357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_bit_ bash.3360463357
Directory	/workspace/4.otp_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.832884655
Short name	T4
Test name
Test status
Simulation time	181089289 ps
CPU time	2.49 seconds
Started	Feb 04 12:37:33 PM PST 24
Finished	Feb 04 12:37:47 PM PST 24
Peak memory	246160 kb
Host	smart-42034dd8-0375-4b59-a929-93cce821b1e1
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832884655 -assert nopostproc +UVM_TESTNAME= otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_mem_rw_with_rand_reset.832884655
Directory	/workspace/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.3681694394
Short name	T42
Test name
Test status
Simulation time	42568657 ps
CPU time	1.67 seconds
Started	Feb 04 12:37:20 PM PST 24
Finished	Feb 04 12:37:33 PM PST 24
Peak memory	229716 kb
Host	smart-f472fd80-fee0-4579-8d78-09d66d5c349c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681694394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_rw.3681694394
Directory	/workspace/4.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.735907533
Short name	T156
Test name
Test status
Simulation time	557452458 ps
CPU time	1.52 seconds
Started	Feb 04 12:37:41 PM PST 24
Finished	Feb 04 12:37:49 PM PST 24
Peak memory	229712 kb
Host	smart-03135658-2f21-4773-846d-12882d6bfe0e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735907533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_intr_test.735907533
Directory	/workspace/4.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.3908956159
Short name	T107
Test name
Test status
Simulation time	490360117 ps
CPU time	1.41 seconds
Started	Feb 04 12:37:28 PM PST 24
Finished	Feb 04 12:37:41 PM PST 24
Peak memory	229448 kb
Host	smart-243e1e56-aee7-4043-8f23-05e5d23e519c
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908956159 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctr l_mem_partial_access.3908956159
Directory	/workspace/4.otp_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.128107039
Short name	T13
Test name
Test status
Simulation time	37411807 ps
CPU time	1.28 seconds
Started	Feb 04 12:37:34 PM PST 24
Finished	Feb 04 12:37:46 PM PST 24
Peak memory	229468 kb
Host	smart-1ee75f4a-9b05-458c-ab4e-fa82b247a599
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128107039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_walk. 128107039
Directory	/workspace/4.otp_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.828431845
Short name	T66
Test name
Test status
Simulation time	504547705 ps
CPU time	3.05 seconds
Started	Feb 04 12:37:41 PM PST 24
Finished	Feb 04 12:37:51 PM PST 24
Peak memory	237916 kb
Host	smart-ce3e8f32-3452-4321-9f38-ecedc54ae632
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828431845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ct rl_same_csr_outstanding.828431845
Directory	/workspace/4.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.1944919783
Short name	T109
Test name
Test status
Simulation time	785507957 ps
CPU time	3.65 seconds
Started	Feb 04 12:37:21 PM PST 24
Finished	Feb 04 12:37:35 PM PST 24
Peak memory	238028 kb
Host	smart-ec6c5626-57bb-4d98-a7ec-4e359aea7593
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944919783 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_errors.1944919783
Directory	/workspace/4.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.426586420
Short name	T86
Test name
Test status
Simulation time	1216371409 ps
CPU time	17.78 seconds
Started	Feb 04 12:37:30 PM PST 24
Finished	Feb 04 12:38:00 PM PST 24
Peak memory	241088 kb
Host	smart-e037fd2e-769b-44db-9204-8f83bcf9396b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426586420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_int g_err.426586420
Directory	/workspace/4.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.4181712933
Short name	T68
Test name
Test status
Simulation time	41354589 ps
CPU time	1.37 seconds
Started	Feb 04 12:37:48 PM PST 24
Finished	Feb 04 12:37:55 PM PST 24
Peak memory	229728 kb
Host	smart-620697c0-1e8d-4486-b9c4-676735203c05
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181712933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_intr_test.4181712933
Directory	/workspace/40.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.1388549874
Short name	T159
Test name
Test status
Simulation time	40267712 ps
CPU time	1.38 seconds
Started	Feb 04 12:37:46 PM PST 24
Finished	Feb 04 12:37:54 PM PST 24
Peak memory	229680 kb
Host	smart-a0c28806-c7c7-4f19-be0c-42fe85d1e7e2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388549874 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_intr_test.1388549874
Directory	/workspace/41.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.577589052
Short name	T173
Test name
Test status
Simulation time	82192733 ps
CPU time	1.4 seconds
Started	Feb 04 12:37:51 PM PST 24
Finished	Feb 04 12:37:56 PM PST 24
Peak memory	229708 kb
Host	smart-def1a048-67d2-4110-b68c-c08a1bec57dd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577589052 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_intr_test.577589052
Directory	/workspace/42.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.3435148343
Short name	T95
Test name
Test status
Simulation time	72941099 ps
CPU time	1.38 seconds
Started	Feb 04 12:37:40 PM PST 24
Finished	Feb 04 12:37:48 PM PST 24
Peak memory	229772 kb
Host	smart-6f1185f9-8a79-46b1-ab9d-1ed7b028a33a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435148343 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_intr_test.3435148343
Directory	/workspace/43.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.749529168
Short name	T122
Test name
Test status
Simulation time	66887758 ps
CPU time	1.33 seconds
Started	Feb 04 12:37:41 PM PST 24
Finished	Feb 04 12:37:49 PM PST 24
Peak memory	229644 kb
Host	smart-e73ec671-80cb-43a6-ad51-91d9c7ceb59f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749529168 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_intr_test.749529168
Directory	/workspace/44.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.1237757634
Short name	T168
Test name
Test status
Simulation time	525689308 ps
CPU time	1.49 seconds
Started	Feb 04 12:37:43 PM PST 24
Finished	Feb 04 12:37:52 PM PST 24
Peak memory	229740 kb
Host	smart-49c440d7-a8c2-437a-9fc4-96a70f699840
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237757634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_intr_test.1237757634
Directory	/workspace/45.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.72474829
Short name	T164
Test name
Test status
Simulation time	38527369 ps
CPU time	1.32 seconds
Started	Feb 04 12:37:40 PM PST 24
Finished	Feb 04 12:37:48 PM PST 24
Peak memory	229760 kb
Host	smart-a40a198d-f306-48d8-97fc-9a083c4ccdc4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72474829 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_intr_test.72474829
Directory	/workspace/46.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.345941679
Short name	T99
Test name
Test status
Simulation time	78355601 ps
CPU time	1.45 seconds
Started	Feb 04 12:37:41 PM PST 24
Finished	Feb 04 12:37:49 PM PST 24
Peak memory	229708 kb
Host	smart-b9d0214c-1050-438d-b549-4a7d7c47d306
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345941679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_intr_test.345941679
Directory	/workspace/47.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.691609195
Short name	T47
Test name
Test status
Simulation time	49803854 ps
CPU time	1.4 seconds
Started	Feb 04 12:37:46 PM PST 24
Finished	Feb 04 12:37:54 PM PST 24
Peak memory	229728 kb
Host	smart-3229f098-05af-4060-abde-731c0393175e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691609195 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_intr_test.691609195
Directory	/workspace/48.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.2953277024
Short name	T9
Test name
Test status
Simulation time	40009340 ps
CPU time	1.41 seconds
Started	Feb 04 12:37:47 PM PST 24
Finished	Feb 04 12:37:55 PM PST 24
Peak memory	229764 kb
Host	smart-5bde1efc-4bbd-46da-8570-9c0daed761de
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953277024 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_intr_test.2953277024
Directory	/workspace/49.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.161184849
Short name	T63
Test name
Test status
Simulation time	112858762 ps
CPU time	3.04 seconds
Started	Feb 04 12:37:22 PM PST 24
Finished	Feb 04 12:37:34 PM PST 24
Peak memory	245584 kb
Host	smart-017a1bfa-ef85-40cb-b41c-dee2df0629aa
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161184849 -assert nopostproc +UVM_TESTNAME= otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_mem_rw_with_rand_reset.161184849
Directory	/workspace/5.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.98926542
Short name	T145
Test name
Test status
Simulation time	112447963 ps
CPU time	1.58 seconds
Started	Feb 04 12:37:39 PM PST 24
Finished	Feb 04 12:37:47 PM PST 24
Peak memory	229712 kb
Host	smart-fcedfb65-0cd3-491c-8e75-0b1f26905b75
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98926542 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_rw.98926542
Directory	/workspace/5.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.3575357121
Short name	T132
Test name
Test status
Simulation time	39079018 ps
CPU time	1.4 seconds
Started	Feb 04 12:37:41 PM PST 24
Finished	Feb 04 12:37:49 PM PST 24
Peak memory	229708 kb
Host	smart-043c41c9-5610-4722-b9fe-ee7128558522
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575357121 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_intr_test.3575357121
Directory	/workspace/5.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.3075779471
Short name	T133
Test name
Test status
Simulation time	47606103 ps
CPU time	1.73 seconds
Started	Feb 04 12:37:29 PM PST 24
Finished	Feb 04 12:37:43 PM PST 24
Peak memory	237984 kb
Host	smart-05d40c79-28df-4ed5-8dc0-a4f0a7dfa5d2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075779471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_c trl_same_csr_outstanding.3075779471
Directory	/workspace/5.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.2583768498
Short name	T18
Test name
Test status
Simulation time	194134093 ps
CPU time	3.32 seconds
Started	Feb 04 12:37:18 PM PST 24
Finished	Feb 04 12:37:33 PM PST 24
Peak memory	238092 kb
Host	smart-0177a333-8ff2-4c9f-b4a4-f1e27d51ff87
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583768498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_errors.2583768498
Directory	/workspace/5.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.3139127206
Short name	T106
Test name
Test status
Simulation time	3384414337 ps
CPU time	21 seconds
Started	Feb 04 12:37:32 PM PST 24
Finished	Feb 04 12:38:05 PM PST 24
Peak memory	241812 kb
Host	smart-2bb77d94-b5c9-4fed-8858-7024c64822cd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139127206 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_in tg_err.3139127206
Directory	/workspace/5.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.2178992099
Short name	T100
Test name
Test status
Simulation time	132145433 ps
CPU time	1.94 seconds
Started	Feb 04 12:37:31 PM PST 24
Finished	Feb 04 12:37:45 PM PST 24
Peak memory	237892 kb
Host	smart-78dc9d6b-fc1f-4803-a22d-d2b520d66762
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178992099 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_mem_rw_with_rand_reset.2178992099
Directory	/workspace/6.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.642578371
Short name	T43
Test name
Test status
Simulation time	62961460 ps
CPU time	1.59 seconds
Started	Feb 04 12:37:41 PM PST 24
Finished	Feb 04 12:37:50 PM PST 24
Peak memory	229664 kb
Host	smart-a73813dd-fe80-4bf2-8821-2f5700a75de0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642578371 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_rw.642578371
Directory	/workspace/6.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.699416142
Short name	T94
Test name
Test status
Simulation time	523129331 ps
CPU time	1.7 seconds
Started	Feb 04 12:37:35 PM PST 24
Finished	Feb 04 12:37:47 PM PST 24
Peak memory	229728 kb
Host	smart-a1a6dc3b-eb50-47a6-b856-6adcecf042c4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699416142 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_intr_test.699416142
Directory	/workspace/6.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.3678367478
Short name	T65
Test name
Test status
Simulation time	67717438 ps
CPU time	2.16 seconds
Started	Feb 04 12:37:18 PM PST 24
Finished	Feb 04 12:37:33 PM PST 24
Peak memory	237904 kb
Host	smart-809400ee-13db-49f0-a950-bca950f749d8
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678367478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_c trl_same_csr_outstanding.3678367478
Directory	/workspace/6.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.31556967
Short name	T143
Test name
Test status
Simulation time	101619026 ps
CPU time	3.48 seconds
Started	Feb 04 12:37:32 PM PST 24
Finished	Feb 04 12:37:48 PM PST 24
Peak memory	238144 kb
Host	smart-e85f7672-9dd3-4530-a384-9a3074c72cac
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31556967 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 7.otp_ctrl_csr_mem_rw_with_rand_reset.31556967
Directory	/workspace/7.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.1128240445
Short name	T50
Test name
Test status
Simulation time	55323291 ps
CPU time	1.57 seconds
Started	Feb 04 12:37:41 PM PST 24
Finished	Feb 04 12:37:49 PM PST 24
Peak memory	229708 kb
Host	smart-70235600-d429-41ff-b964-4feaf9d64837
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128240445 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_rw.1128240445
Directory	/workspace/7.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.2296439514
Short name	T112
Test name
Test status
Simulation time	629182900 ps
CPU time	1.49 seconds
Started	Feb 04 12:37:39 PM PST 24
Finished	Feb 04 12:37:47 PM PST 24
Peak memory	229724 kb
Host	smart-51dab512-c0a8-4276-92fe-ab285b1856cb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296439514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_intr_test.2296439514
Directory	/workspace/7.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.675871341
Short name	T141
Test name
Test status
Simulation time	81021392 ps
CPU time	2.57 seconds
Started	Feb 04 12:37:39 PM PST 24
Finished	Feb 04 12:37:48 PM PST 24
Peak memory	238016 kb
Host	smart-a89b495f-659f-431d-80e1-7fc3bb11a40b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675871341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ct rl_same_csr_outstanding.675871341
Directory	/workspace/7.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.3092064885
Short name	T2
Test name
Test status
Simulation time	1564931444 ps
CPU time	5.65 seconds
Started	Feb 04 12:37:33 PM PST 24
Finished	Feb 04 12:37:51 PM PST 24
Peak memory	243456 kb
Host	smart-f86f480c-e224-42f3-952d-8c3ac9a62360
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092064885 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_errors.3092064885
Directory	/workspace/7.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.2702861880
Short name	T24
Test name
Test status
Simulation time	18542946572 ps
CPU time	25.94 seconds
Started	Feb 04 12:37:26 PM PST 24
Finished	Feb 04 12:37:57 PM PST 24
Peak memory	241924 kb
Host	smart-2607cf5f-1419-44cf-a909-101b89b459a4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702861880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_in tg_err.2702861880
Directory	/workspace/7.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.625590401
Short name	T108
Test name
Test status
Simulation time	66897902 ps
CPU time	1.41 seconds
Started	Feb 04 12:37:40 PM PST 24
Finished	Feb 04 12:37:48 PM PST 24
Peak memory	229728 kb
Host	smart-b24f36fb-d4dc-4e6a-8231-55be6be55fe3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625590401 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_intr_test.625590401
Directory	/workspace/8.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.680694890
Short name	T30
Test name
Test status
Simulation time	235161331 ps
CPU time	1.98 seconds
Started	Feb 04 12:37:35 PM PST 24
Finished	Feb 04 12:37:47 PM PST 24
Peak memory	238016 kb
Host	smart-d9e10e59-65c5-4674-ac20-8577f75c2731
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680694890 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ct rl_same_csr_outstanding.680694890
Directory	/workspace/8.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.173484274
Short name	T17
Test name
Test status
Simulation time	137006090 ps
CPU time	2.87 seconds
Started	Feb 04 12:37:40 PM PST 24
Finished	Feb 04 12:37:49 PM PST 24
Peak memory	237980 kb
Host	smart-b177a1da-7fed-4812-935d-c9f460079ddc
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173484274 -assert nopostproc +UVM_TESTNAME= otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_mem_rw_with_rand_reset.173484274
Directory	/workspace/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.3039297457
Short name	T59
Test name
Test status
Simulation time	66533997 ps
CPU time	1.64 seconds
Started	Feb 04 12:37:20 PM PST 24
Finished	Feb 04 12:37:33 PM PST 24
Peak memory	229620 kb
Host	smart-bccf8c65-39ce-4e12-834b-5347371d4dc5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039297457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_rw.3039297457
Directory	/workspace/9.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.303516503
Short name	T92
Test name
Test status
Simulation time	585432720 ps
CPU time	1.71 seconds
Started	Feb 04 12:37:22 PM PST 24
Finished	Feb 04 12:37:33 PM PST 24
Peak memory	229676 kb
Host	smart-e7ba6463-8ae0-41c6-b983-cb0dfd986ba0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303516503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_intr_test.303516503
Directory	/workspace/9.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.901540377
Short name	T153
Test name
Test status
Simulation time	59979930 ps
CPU time	1.95 seconds
Started	Feb 04 12:37:20 PM PST 24
Finished	Feb 04 12:37:33 PM PST 24
Peak memory	237920 kb
Host	smart-c58f0391-0af7-4677-9361-6c2d51766951
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901540377 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ct rl_same_csr_outstanding.901540377
Directory	/workspace/9.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.2056617588
Short name	T116
Test name
Test status
Simulation time	811071357 ps
CPU time	3.16 seconds
Started	Feb 04 12:37:29 PM PST 24
Finished	Feb 04 12:37:43 PM PST 24
Peak memory	246156 kb
Host	smart-1ad80893-41b3-4698-884d-ecf01649c51f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056617588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_errors.2056617588
Directory	/workspace/9.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.2862683859
Short name	T138
Test name
Test status
Simulation time	1256127122 ps
CPU time	9.79 seconds
Started	Feb 04 12:37:32 PM PST 24
Finished	Feb 04 12:37:55 PM PST 24
Peak memory	240816 kb
Host	smart-c8ec68fa-af3f-4691-a9d7-28a6ce747383
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862683859 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_in tg_err.2862683859
Directory	/workspace/9.otp_ctrl_tl_intg_err/latest