Unified Coverage Report :: Module :: otp_ctrl_part_unbuf

Module : otp_ctrl_part_unbuf

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.82	98.49	96.36		64.71	94.57	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf	88.64	92.39	93.55		72.00	89.13	96.15
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf	92.35	100.00	97.06		64.71	100.00	100.00
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf	92.35	100.00	97.06		64.71	100.00	100.00
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf	97.01	100.00	97.06		88.00	100.00	100.00
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf	97.01	100.00	97.06		88.00	100.00	100.00

Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=65616,DigestOffset=56,StateWidth=10 )
Line Coverage for Module self-instances :

SCORE	LINE
88.64	92.39

tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		93	86	92.47
CONT_ASSIGN	138	1	1	100.00
ALWAYS	153	3	3	100.00
ALWAYS	164	68	61	89.71
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
153	1	1
154	1	1
156	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			==> MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	0	1
			MISSING_ELSE
224	0	1
225	0	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	0	1
			MISSING_ELSE
276	0	1
277	0	1
279	0	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
339	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=134651988,DigestOffset=480,StateWidth=10 )
Line Coverage for Module self-instances :

SCORE	LINE
97.01	100.00

tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=1024082004,DigestOffset=1136,StateWidth=10 )
Line Coverage for Module self-instances :

SCORE	LINE
97.01	100.00

tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=-1,DigestOffset=1608,StateWidth=10 )
Line Coverage for Module self-instances :

SCORE	LINE
92.35	100.00

tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=-1,DigestOffset=1648,StateWidth=10 )
Line Coverage for Module self-instances :

SCORE	LINE
92.35	100.00

tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=-1,DigestOffset=1608,StateWidth=10 )
Cond Coverage for Module self-instances :

SCORE	COND
92.35	97.06

tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	34	33	97.06
Logical	34	33	97.06
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T67,T66,T80

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T17,T40,T31

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T4,T9,T13
1	Covered	T25,T26,T27

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T77,T165,T166
1	Covered	T77,T165,T166

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T4,T9,T13
1	Covered	T4,T9,T13

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T8

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T12,T109
1	1	Covered	T1,T2,T8

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b10001111000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T8

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

---

Cond Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=65616,DigestOffset=56,StateWidth=10 )
Cond Coverage for Module self-instances :

SCORE	COND
88.64	93.55

tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	31	29	93.55
Logical	31	29	93.55
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T8,T9
1	Not Covered

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T4,T9,T13
1	Covered	T25,T26,T27

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T167,T165,T166
1	Covered	T167,T165,T166

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T4,T9,T13
1	Covered	T4,T9,T13

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T9

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T8,T9

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T8,T9
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T8,T9
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

---

Cond Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=134651988,DigestOffset=480,StateWidth=10 )
Cond Coverage for Module self-instances :

SCORE	COND
97.01	97.06

tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	34	33	97.06
Logical	34	33	97.06
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T64,T80,T168

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T40,T31,T104

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T4,T9,T13
1	Covered	T25,T26,T27

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T77,T78,T152
1	Covered	T77,T78,T152

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T4,T9,T13
1	Covered	T4,T9,T13

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T9
1	1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T9

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T9

---

Cond Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=1024082004,DigestOffset=1136,StateWidth=10 )
Cond Coverage for Module self-instances :

SCORE	COND
97.01	97.06

tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	34	33	97.06
Logical	34	33	97.06
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T169,T86,T170

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T17,T40,T31

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T4,T9,T13
1	Covered	T25,T26,T27

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T77,T167,T165
1	Covered	T77,T167,T165

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T4,T9,T13
1	Covered	T4,T9,T13

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00111101000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T9

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T9

---

Cond Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=-1,DigestOffset=1648,StateWidth=10 )
Cond Coverage for Module self-instances :

SCORE	COND
92.35	97.06

tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	34	33	97.06
Logical	34	33	97.06
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T80,T86

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T40,T31,T104

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T4,T9,T13
1	Covered	T25,T26,T27

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T77,T152,T167
1	Covered	T77,T152,T167

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T4,T9,T13
1	Covered	T4,T9,T13

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b11001010000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T12,T67

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T12,T67

---

FSM Coverage for Module : otp_ctrl_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T4,T9,T13
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T2,T3
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
IdleSt->ErrorSt	315	Covered	T4,T9,T13
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T64,T171,T172
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T64,T171,T172
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T1,T2,T12
ReadSt->ReadWaitSt	252	Covered	T1,T2,T3
ReadWaitSt->ErrorSt	276	Covered	T99,T157,T164
ReadWaitSt->IdleSt	270	Covered	T1,T2,T3
ResetSt->ErrorSt	315	Covered	T76,T77,T78
ResetSt->IdleSt	196	Not Covered
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	20	10	50.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T1,T2,T12
CheckFailError	317	Covered	T77,T78,T152
FsmStateError	289	Covered	T4,T9,T13
MacroEccCorrError	221	Covered	T13,T64,T17
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AccessError->CheckFailError	317	Not Covered
AccessError->FsmStateError	325	Covered	T110,T5,T100
AccessError->MacroEccCorrError	221	Not Covered
AccessError->NoError	235	Covered	T1,T2,T12
CheckFailError->AccessError	256	Not Covered
CheckFailError->FsmStateError	325	Not Covered
CheckFailError->MacroEccCorrError	221	Not Covered
CheckFailError->NoError	235	Covered	T77,T78,T152
FsmStateError->AccessError	256	Not Covered
FsmStateError->CheckFailError	317	Not Covered
FsmStateError->MacroEccCorrError	221	Not Covered
FsmStateError->NoError	235	Covered	T4,T9,T13
MacroEccCorrError->AccessError	256	Not Covered
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T64,T67,T66
MacroEccCorrError->NoError	235	Covered	T17,T40,T31
NoError->AccessError	256	Covered	T1,T2,T12
NoError->CheckFailError	317	Covered	T77,T78,T152
NoError->FsmStateError	289	Covered	T4,T9,T13
NoError->MacroEccCorrError	221	Covered	T13,T64,T17

---

Branch Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=65616,DigestOffset=56,StateWidth=10 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
88.64	89.13

tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		46	41	89.13
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	18	78.26
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00
IF	153	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T8,T9

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T8,T9

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T8
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T8,T9
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T2,T108,T5
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T12
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T8,T9
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T8,T9
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T25,T26,T27
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T4,T9,T13
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T4,T9,T110
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T4,T9,T110
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T4,T9,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T25,T26,T27

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T167,T165,T166
1	0	Covered	T167,T165,T166
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T4,T9,T13
1	0	Covered	T4,T9,T13
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	if ((otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}))

Branches:

-1-	Status	Tests
1	Covered	T13,T64,T17
0	Covered	T1,T2,T3

---

Branch Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=134651988,DigestOffset=480,StateWidth=10 + Info=1024082004,DigestOffset=1136,StateWidth=10 + Info=-1,DigestOffset=1608,StateWidth=10 + Info=-1,DigestOffset=1648,StateWidth=10 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
97.01	100.00

tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

SCORE	BRANCH
97.01	100.00

tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

SCORE	BRANCH
92.35	100.00

tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

SCORE	BRANCH
92.35	100.00

tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T64,T67,T66
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T64,T116,T171
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T1,T2,T108
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T12
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T17,T40,T31
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T99,T157,T164
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T25,T26,T27
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T4,T9,T13
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T4,T9,T17
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T4,T9,T17
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T4,T9,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T25,T26,T27

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T77,T78,T152
1	0	Covered	T77,T78,T152
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T4,T9,T13
1	0	Covered	T4,T9,T13
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : otp_ctrl_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	2147483647	2147483647	0	0
DigestKnown_A	2147483647	2147483647	0	0
DigestOffsetMustBeRepresentable_A	5545	5545	0	0
EccErrorState_A	2147483647	69918	0	0
ErrorKnown_A	2147483647	2147483647	0	0
FsmStateKnown_A	2147483647	2147483647	0	0
InitDoneKnown_A	2147483647	2147483647	0	0
InitReadLocksPartition_A	2147483647	1267758680	0	0
InitWriteLocksPartition_A	2147483647	1267758680	0	0
OffsetMustBeBlockAligned_A	5545	5545	0	0
OtpAddrKnown_A	2147483647	2147483647	0	0
OtpCmdKnown_A	2147483647	2147483647	0	0
OtpErrorState_A	2147483647	202	0	0
OtpReqKnown_A	2147483647	2147483647	0	0
OtpSizeKnown_A	2147483647	2147483647	0	0
OtpWdataKnown_A	2147483647	2147483647	0	0
ReadLockPropagation_A	2147483647	2147483647	0	0
SizeMustBeBlockAligned_A	5545	5545	0	0
TlulGntKnown_A	2147483647	2147483647	0	0
TlulRdataKnown_A	2147483647	2147483647	0	0
TlulReadOnReadLock_A	2147483647	36426	0	0
TlulRerrorKnown_A	2147483647	2147483647	0	0
TlulRvalidKnown_A	2147483647	2147483647	0	0
WriteLockPropagation_A	2147483647	10851558	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	2147483647	121100048	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	250990	245930	0	0
T2	217525	213465	0	0
T3	108890	106440	0	0
T4	144280	142935	0	0
T8	211390	207615	0	0
T9	132025	129915	0	0
T10	140200	137510	0	0
T11	70625	69135	0	0
T12	413955	408395	0	0
T13	70450	69080	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	250990	245930	0	0
T2	217525	213465	0	0
T3	108890	106440	0	0
T4	144280	142935	0	0
T8	211390	207615	0	0
T9	132025	129915	0	0
T10	140200	137510	0	0
T11	70625	69135	0	0
T12	413955	408395	0	0
T13	70450	69080	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5545	5545	0	0
T1	5	5	0	0
T2	5	5	0	0
T3	5	5	0	0
T4	5	5	0	0
T8	5	5	0	0
T9	5	5	0	0
T10	5	5	0	0
T11	5	5	0	0
T12	5	5	0	0
T13	5	5	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	69918	0	0
T15	866400	0	0	0
T48	46044	0	0	0
T56	100041	0	0	0
T77	52036	9648	0	0
T78	40832	3968	0	0
T86	57428	0	0	0
T152	0	4244	0	0
T165	0	12752	0	0
T166	0	6963	0	0
T167	8105	9144	0	0
T173	0	7251	0	0
T174	0	8307	0	0
T175	0	7641	0	0
T176	152528	0	0	0
T177	97472	0	0	0
T178	121560	0	0	0
T179	403292	0	0	0
T180	303232	0	0	0
T181	17393	0	0	0
T182	15899	0	0	0
T183	25665	0	0	0
T184	56149	0	0	0
T185	154939	0	0	0
T186	14234	0	0	0
T187	52304	0	0	0
T188	615861	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	250990	245930	0	0
T2	217525	213465	0	0
T3	108890	106440	0	0
T4	144280	142935	0	0
T8	211390	207615	0	0
T9	132025	129915	0	0
T10	140200	137510	0	0
T11	70625	69135	0	0
T12	413955	408395	0	0
T13	70450	69080	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	250990	245930	0	0
T2	217525	213465	0	0
T3	108890	106440	0	0
T4	144280	142935	0	0
T8	211390	207615	0	0
T9	132025	129915	0	0
T10	140200	137510	0	0
T11	70625	69135	0	0
T12	413955	408395	0	0
T13	70450	69080	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	250990	245930	0	0
T2	217525	213465	0	0
T3	108890	106440	0	0
T4	144280	142935	0	0
T8	211390	207615	0	0
T9	132025	129915	0	0
T10	140200	137510	0	0
T11	70625	69135	0	0
T12	413955	408395	0	0
T13	70450	69080	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1267758680	0	0
T1	250990	5390	0	0
T2	217525	4825	0	0
T3	108890	2773	0	0
T4	144280	76510	0	0
T8	211390	4290	0	0
T9	132025	66240	0	0
T10	140200	4440	0	0
T11	70625	1385	0	0
T12	413955	5690	0	0
T13	70450	20105	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1267758680	0	0
T1	250990	5390	0	0
T2	217525	4825	0	0
T3	108890	2773	0	0
T4	144280	76510	0	0
T8	211390	4290	0	0
T9	132025	66240	0	0
T10	140200	4440	0	0
T11	70625	1385	0	0
T12	413955	5690	0	0
T13	70450	20105	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5545	5545	0	0
T1	5	5	0	0
T2	5	5	0	0
T3	5	5	0	0
T4	5	5	0	0
T8	5	5	0	0
T9	5	5	0	0
T10	5	5	0	0
T11	5	5	0	0
T12	5	5	0	0
T13	5	5	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	250990	245930	0	0
T2	217525	213465	0	0
T3	108890	106440	0	0
T4	144280	142935	0	0
T8	211390	207615	0	0
T9	132025	129915	0	0
T10	140200	137510	0	0
T11	70625	69135	0	0
T12	413955	408395	0	0
T13	70450	69080	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	250990	245930	0	0
T2	217525	213465	0	0
T3	108890	106440	0	0
T4	144280	142935	0	0
T8	211390	207615	0	0
T9	132025	129915	0	0
T10	140200	137510	0	0
T11	70625	69135	0	0
T12	413955	408395	0	0
T13	70450	69080	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	202	0	0
T6	291118	0	0	0
T17	39889	0	0	0
T19	10102	0	0	0
T40	60132	0	0	0
T45	18588	0	0	0
T64	11400	1	0	0
T66	18254	0	0	0
T67	14706	0	0	0
T99	101208	1	0	0
T101	113056	0	0	0
T108	15642	0	0	0
T109	29550	0	0	0
T110	15519	0	0	0
T116	0	1	0	0
T145	22428	0	0	0
T164	0	3	0	0
T168	13609	1	0	0
T171	22274	1	0	0
T172	21304	1	0	0
T189	10075	1	0	0
T190	0	1	0	0
T191	0	1	0	0
T192	0	1	0	0
T193	0	1	0	0
T194	0	1	0	0
T195	0	1	0	0
T196	0	1	0	0
T197	0	1	0	0
T198	0	1	0	0
T199	0	1	0	0
T200	0	1	0	0
T201	0	1	0	0
T202	0	1	0	0
T203	13346	0	0	0
T204	42372	0	0	0
T205	6445	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	250990	245930	0	0
T2	217525	213465	0	0
T3	108890	106440	0	0
T4	144280	142935	0	0
T8	211390	207615	0	0
T9	132025	129915	0	0
T10	140200	137510	0	0
T11	70625	69135	0	0
T12	413955	408395	0	0
T13	70450	69080	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	250990	245930	0	0
T2	217525	213465	0	0
T3	108890	106440	0	0
T4	144280	142935	0	0
T8	211390	207615	0	0
T9	132025	129915	0	0
T10	140200	137510	0	0
T11	70625	69135	0	0
T12	413955	408395	0	0
T13	70450	69080	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	250990	245930	0	0
T2	217525	213465	0	0
T3	108890	106440	0	0
T4	144280	142935	0	0
T8	211390	207615	0	0
T9	132025	129915	0	0
T10	140200	137510	0	0
T11	70625	69135	0	0
T12	413955	408395	0	0
T13	70450	69080	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	250990	27079	0	0
T2	217525	7216	0	0
T3	108890	0	0	0
T4	144280	65224	0	0
T5	0	1504079	0	0
T8	211390	3087	0	0
T9	132025	0	0	0
T10	140200	0	0	0
T11	70625	0	0	0
T12	413955	77149	0	0
T13	70450	0	0	0
T31	0	12091	0	0
T40	0	37599	0	0
T96	0	40727	0	0
T108	0	3731	0	0
T109	0	54363	0	0
T110	0	37772	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5545	5545	0	0
T1	5	5	0	0
T2	5	5	0	0
T3	5	5	0	0
T4	5	5	0	0
T8	5	5	0	0
T9	5	5	0	0
T10	5	5	0	0
T11	5	5	0	0
T12	5	5	0	0
T13	5	5	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	250990	245930	0	0
T2	217525	213465	0	0
T3	108890	106440	0	0
T4	144280	142935	0	0
T8	211390	207615	0	0
T9	132025	129915	0	0
T10	140200	137510	0	0
T11	70625	69135	0	0
T12	413955	408395	0	0
T13	70450	69080	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	250990	245930	0	0
T2	217525	213465	0	0
T3	108890	106440	0	0
T4	144280	142935	0	0
T8	211390	207615	0	0
T9	132025	129915	0	0
T10	140200	137510	0	0
T11	70625	69135	0	0
T12	413955	408395	0	0
T13	70450	69080	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	36426	0	0
T1	250990	31	0	0
T2	217525	5	0	0
T3	108890	0	0	0
T4	144280	8	0	0
T5	0	352	0	0
T8	211390	0	0	0
T9	132025	7	0	0
T10	140200	0	0	0
T11	70625	0	0	0
T12	413955	12	0	0
T13	70450	0	0	0
T17	0	1	0	0
T31	0	19	0	0
T40	0	25	0	0
T96	0	9	0	0
T97	0	7	0	0
T99	0	8	0	0
T109	0	11	0	0
T110	0	34	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	250990	245930	0	0
T2	217525	213465	0	0
T3	108890	106440	0	0
T4	144280	142935	0	0
T8	211390	207615	0	0
T9	132025	129915	0	0
T10	140200	137510	0	0
T11	70625	69135	0	0
T12	413955	408395	0	0
T13	70450	69080	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	250990	245930	0	0
T2	217525	213465	0	0
T3	108890	106440	0	0
T4	144280	142935	0	0
T8	211390	207615	0	0
T9	132025	129915	0	0
T10	140200	137510	0	0
T11	70625	69135	0	0
T12	413955	408395	0	0
T13	70450	69080	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	10851558	0	0
T1	50198	6706	0	0
T2	43505	1143	0	0
T3	21778	0	0	0
T4	28856	0	0	0
T5	205008	154115	0	0
T6	0	200886	0	0
T8	42278	0	0	0
T9	26405	0	0	0
T10	28040	0	0	0
T11	14125	0	0	0
T12	82791	25157	0	0
T13	14090	0	0	0
T20	0	23022	0	0
T31	137146	13959	0	0
T40	60132	15839	0	0
T66	18254	0	0	0
T80	14312	0	0	0
T95	12588	0	0	0
T96	237882	58307	0	0
T97	38548	0	0	0
T98	25656	0	0	0
T99	202416	0	0	0
T100	171486	0	0	0
T101	0	12997	0	0
T102	0	16240	0	0
T103	0	20246	0	0
T104	0	12205	0	0
T105	0	16094	0	0
T115	0	11875	0	0
T206	0	6801	0	0
T207	0	13261	0	0
T208	0	23659	0	0
T209	0	6362	0	0
T210	0	7002	0	0
T211	0	10514	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	121100048	0	0
T1	200792	167882	0	0
T2	174020	139012	0	0
T3	87112	0	0	0
T4	144280	13589	0	0
T5	0	1189468	0	0
T6	0	382954	0	0
T8	211390	0	0	0
T9	132025	7365	0	0
T10	140200	0	0	0
T11	70625	0	0	0
T12	413955	255491	0	0
T13	70450	3413	0	0
T17	39889	30865	0	0
T18	5797	0	0	0
T20	0	66060	0	0
T31	0	169962	0	0
T40	0	162025	0	0
T64	11400	3581	0	0
T67	0	6110	0	0
T76	0	4288	0	0
T96	0	286573	0	0
T100	0	3415	0	0
T109	0	41069	0	0
T110	0	5363	0	0
T116	0	2565	0	0
T204	0	2563	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	250990	245930	0	0
T2	217525	213465	0	0
T3	108890	106440	0	0
T4	144280	142935	0	0
T8	211390	207615	0	0
T9	132025	129915	0	0
T10	140200	137510	0	0
T11	70625	69135	0	0
T12	413955	408395	0	0
T13	70450	69080	0	0