Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.64	92.39	93.55		72.00	89.13	96.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.91	94.96	93.55	97.87	72.00	89.83	97.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.24	96.15	86.96	87.79		93.10	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	94.47	100.00		97.87		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.01	100.00	97.06		88.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.86	100.00	97.06	97.87	88.00	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.24	96.15	86.96	87.79		93.10	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	94.47	100.00		97.87		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.01	100.00	97.06		88.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.86	100.00	97.06	97.87	88.00	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.24	96.15	86.96	87.79		93.10	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	94.47	100.00		97.87		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		92	85	92.39
CONT_ASSIGN	138	1	1	100.00
ALWAYS	153	3	3	100.00
ALWAYS	164	67	60	89.55
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
153	1	1
154	1	1
156	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			==> MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	0	1
			MISSING_ELSE
224	0	1
225	0	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	0	1
			MISSING_ELSE
276	0	1
277	0	1
279	0	1
			MISSING_ELSE
288	1	1
289		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
339	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	31	29	93.55
Logical	31	29	93.55
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T8,T9
1	Not Covered

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T4,T9,T13
1	Covered	T25,T26,T27

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T167,T165,T166
1	Covered	T167,T165,T166

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T4,T9,T13
1	Covered	T4,T9,T13

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T9

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T8,T9

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T8,T9
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T8,T9
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

---

FSM Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	14	11	78.57
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T4,T9,T13
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T8
ReadWaitSt	252	Covered	T2,T8,T9
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
IdleSt->ErrorSt	315	Covered	T4,T9,T13
IdleSt->ReadSt	236	Covered	T1,T2,T8
InitSt->ErrorSt	315	Covered	T212
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T213,T214,T215
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T1,T2,T12
ReadSt->ReadWaitSt	252	Covered	T2,T8,T9
ReadWaitSt->ErrorSt	276	Not Covered
ReadWaitSt->IdleSt	270	Covered	T2,T8,T9
ResetSt->ErrorSt	315	Covered	T76,T77,T78
ResetSt->IdleSt	196	Not Covered
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	4	80.00	(Not included in score)
Transitions	11	7	63.64
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T1,T2,T12
CheckFailError	317	Covered	T167,T165,T166
FsmStateError	289	Covered	T4,T9,T13
MacroEccCorrError	221	Not Covered
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T6,T204,T146
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T1,T2,T12
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T167,T165,T166
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T4,T9,T13
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Not Covered
MacroEccCorrError->NoError	235	Not Covered
NoError->AccessError	256	Covered	T1,T2,T12
NoError->CheckFailError	317	Covered	T167,T165,T166
NoError->FsmStateError	289	Covered	T4,T9,T13
NoError->MacroEccCorrError	221	Not Covered

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		46	41	89.13
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	18	78.26
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00
IF	153	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T8,T9

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T8,T9

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T8
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T8,T9
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T2,T108,T5
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T12
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T8,T9
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T8,T9
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T25,T26,T27
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T4,T9,T13
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T4,T9,T110
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T4,T9,T110
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T4,T9,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T25,T26,T27

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T167,T165,T166
1	0	Covered	T167,T165,T166
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T4,T9,T13
1	0	Covered	T4,T9,T13
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	if ((otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}))

Branches:

-1-	Status	Tests
1	Covered	T13,T64,T17
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	1379487533	1378600612	0	0
DigestKnown_A	1379487533	1378600612	0	0
DigestOffsetMustBeRepresentable_A	1109	1109	0	0
EccErrorState_A	1379487533	13111	0	0
ErrorKnown_A	1379487533	1378600612	0	0
FsmStateKnown_A	1379487533	1378600612	0	0
InitDoneKnown_A	1379487533	1378600612	0	0
InitReadLocksPartition_A	1379487533	253185806	0	0
InitWriteLocksPartition_A	1379487533	253185806	0	0
OffsetMustBeBlockAligned_A	1109	1109	0	0
OtpAddrKnown_A	1379487533	1378600612	0	0
OtpCmdKnown_A	1379487533	1378600612	0	0
OtpErrorState_A	1379487533	0	0	0
OtpReqKnown_A	1379487533	1378600612	0	0
OtpSizeKnown_A	1379487533	1378600612	0	0
OtpWdataKnown_A	1379487533	1378600612	0	0
ReadLockPropagation_A	1379487533	716778731	0	0
SizeMustBeBlockAligned_A	1109	1109	0	0
TlulGntKnown_A	1379487533	1378600612	0	0
TlulRdataKnown_A	1379487533	1378600612	0	0
TlulReadOnReadLock_A	1379487533	7074	0	0
TlulRerrorKnown_A	1379487533	1378600612	0	0
TlulRvalidKnown_A	1379487533	1378600612	0	0
WriteLockPropagation_A	1379487533	2573808	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	1379487533	28976390	0	0
u_state_regs_A	1379487533	1378600612	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	1378600612	0	0
T1	50198	49186	0	0
T2	43505	42693	0	0
T3	21778	21288	0	0
T4	28856	28587	0	0
T8	42278	41523	0	0
T9	26405	25983	0	0
T10	28040	27502	0	0
T11	14125	13827	0	0
T12	82791	81679	0	0
T13	14090	13816	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	1378600612	0	0
T1	50198	49186	0	0
T2	43505	42693	0	0
T3	21778	21288	0	0
T4	28856	28587	0	0
T8	42278	41523	0	0
T9	26405	25983	0	0
T10	28040	27502	0	0
T11	14125	13827	0	0
T12	82791	81679	0	0
T13	14090	13816	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1109	1109	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	13111	0	0
T56	100041	0	0	0
T165	0	3188	0	0
T166	0	2321	0	0
T167	8105	2286	0	0
T174	0	2769	0	0
T175	0	2547	0	0
T181	17393	0	0	0
T182	15899	0	0	0
T183	25665	0	0	0
T184	56149	0	0	0
T185	154939	0	0	0
T186	14234	0	0	0
T187	52304	0	0	0
T188	615861	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	1378600612	0	0
T1	50198	49186	0	0
T2	43505	42693	0	0
T3	21778	21288	0	0
T4	28856	28587	0	0
T8	42278	41523	0	0
T9	26405	25983	0	0
T10	28040	27502	0	0
T11	14125	13827	0	0
T12	82791	81679	0	0
T13	14090	13816	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	1378600612	0	0
T1	50198	49186	0	0
T2	43505	42693	0	0
T3	21778	21288	0	0
T4	28856	28587	0	0
T8	42278	41523	0	0
T9	26405	25983	0	0
T10	28040	27502	0	0
T11	14125	13827	0	0
T12	82791	81679	0	0
T13	14090	13816	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	1378600612	0	0
T1	50198	49186	0	0
T2	43505	42693	0	0
T3	21778	21288	0	0
T4	28856	28587	0	0
T8	42278	41523	0	0
T9	26405	25983	0	0
T10	28040	27502	0	0
T11	14125	13827	0	0
T12	82791	81679	0	0
T13	14090	13816	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	253185806	0	0
T1	50198	670	0	0
T2	43505	557	0	0
T3	21778	352	0	0
T4	28856	15200	0	0
T8	42278	552	0	0
T9	26405	13112	0	0
T10	28040	684	0	0
T11	14125	175	0	0
T12	82791	696	0	0
T13	14090	3919	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	253185806	0	0
T1	50198	670	0	0
T2	43505	557	0	0
T3	21778	352	0	0
T4	28856	15200	0	0
T8	42278	552	0	0
T9	26405	13112	0	0
T10	28040	684	0	0
T11	14125	175	0	0
T12	82791	696	0	0
T13	14090	3919	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1109	1109	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	1378600612	0	0
T1	50198	49186	0	0
T2	43505	42693	0	0
T3	21778	21288	0	0
T4	28856	28587	0	0
T8	42278	41523	0	0
T9	26405	25983	0	0
T10	28040	27502	0	0
T11	14125	13827	0	0
T12	82791	81679	0	0
T13	14090	13816	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	1378600612	0	0
T1	50198	49186	0	0
T2	43505	42693	0	0
T3	21778	21288	0	0
T4	28856	28587	0	0
T8	42278	41523	0	0
T9	26405	25983	0	0
T10	28040	27502	0	0
T11	14125	13827	0	0
T12	82791	81679	0	0
T13	14090	13816	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	1378600612	0	0
T1	50198	49186	0	0
T2	43505	42693	0	0
T3	21778	21288	0	0
T4	28856	28587	0	0
T8	42278	41523	0	0
T9	26405	25983	0	0
T10	28040	27502	0	0
T11	14125	13827	0	0
T12	82791	81679	0	0
T13	14090	13816	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	1378600612	0	0
T1	50198	49186	0	0
T2	43505	42693	0	0
T3	21778	21288	0	0
T4	28856	28587	0	0
T8	42278	41523	0	0
T9	26405	25983	0	0
T10	28040	27502	0	0
T11	14125	13827	0	0
T12	82791	81679	0	0
T13	14090	13816	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	1378600612	0	0
T1	50198	49186	0	0
T2	43505	42693	0	0
T3	21778	21288	0	0
T4	28856	28587	0	0
T8	42278	41523	0	0
T9	26405	25983	0	0
T10	28040	27502	0	0
T11	14125	13827	0	0
T12	82791	81679	0	0
T13	14090	13816	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	716778731	0	0
T1	50198	6081	0	0
T2	43505	778	0	0
T3	21778	0	0	0
T4	28856	15437	0	0
T5	0	212834	0	0
T8	42278	1034	0	0
T9	26405	0	0	0
T10	28040	0	0	0
T11	14125	0	0	0
T12	82791	11226	0	0
T13	14090	0	0	0
T40	0	9692	0	0
T108	0	834	0	0
T109	0	14493	0	0
T110	0	7610	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1109	1109	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	1378600612	0	0
T1	50198	49186	0	0
T2	43505	42693	0	0
T3	21778	21288	0	0
T4	28856	28587	0	0
T8	42278	41523	0	0
T9	26405	25983	0	0
T10	28040	27502	0	0
T11	14125	13827	0	0
T12	82791	81679	0	0
T13	14090	13816	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	1378600612	0	0
T1	50198	49186	0	0
T2	43505	42693	0	0
T3	21778	21288	0	0
T4	28856	28587	0	0
T8	42278	41523	0	0
T9	26405	25983	0	0
T10	28040	27502	0	0
T11	14125	13827	0	0
T12	82791	81679	0	0
T13	14090	13816	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	7074	0	0
T1	50198	7	0	0
T2	43505	1	0	0
T3	21778	0	0	0
T4	28856	2	0	0
T5	0	79	0	0
T8	42278	0	0	0
T9	26405	2	0	0
T10	28040	0	0	0
T11	14125	0	0	0
T12	82791	1	0	0
T13	14090	0	0	0
T31	0	5	0	0
T40	0	5	0	0
T109	0	2	0	0
T110	0	3	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	1378600612	0	0
T1	50198	49186	0	0
T2	43505	42693	0	0
T3	21778	21288	0	0
T4	28856	28587	0	0
T8	42278	41523	0	0
T9	26405	25983	0	0
T10	28040	27502	0	0
T11	14125	13827	0	0
T12	82791	81679	0	0
T13	14090	13816	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	1378600612	0	0
T1	50198	49186	0	0
T2	43505	42693	0	0
T3	21778	21288	0	0
T4	28856	28587	0	0
T8	42278	41523	0	0
T9	26405	25983	0	0
T10	28040	27502	0	0
T11	14125	13827	0	0
T12	82791	81679	0	0
T13	14090	13816	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	2573808	0	0
T5	102504	49956	0	0
T6	0	31005	0	0
T20	0	2229	0	0
T31	68573	3909	0	0
T40	60132	9245	0	0
T66	18254	0	0	0
T95	6294	0	0	0
T96	118941	16988	0	0
T97	19274	0	0	0
T98	12828	0	0	0
T99	101208	0	0	0
T100	85743	0	0	0
T102	0	3352	0	0
T103	0	5098	0	0
T104	0	12205	0	0
T105	0	1804	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	28976390	0	0
T1	50198	42251	0	0
T2	43505	35008	0	0
T3	21778	0	0	0
T4	28856	4609	0	0
T8	42278	0	0	0
T9	26405	0	0	0
T10	28040	0	0	0
T11	14125	0	0	0
T12	82791	41489	0	0
T13	14090	3413	0	0
T17	0	30865	0	0
T40	0	43364	0	0
T67	0	3083	0	0
T109	0	5047	0	0
T110	0	2690	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	1378600612	0	0
T1	50198	49186	0	0
T2	43505	42693	0	0
T3	21778	21288	0	0
T4	28856	28587	0	0
T8	42278	41523	0	0
T9	26405	25983	0	0
T10	28040	27502	0	0
T11	14125	13827	0	0
T12	82791	81679	0	0
T13	14090	13816	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		90	90	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	67	67	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	34	33	97.06
Logical	34	33	97.06
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T64,T80,T168

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T40,T31,T104

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T4,T9,T13
1	Covered	T25,T26,T27

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T77,T78,T152
1	Covered	T77,T78,T152

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T4,T9,T13
1	Covered	T4,T9,T13

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T9
1	1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T9

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T9

---

FSM Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T4,T9,T13
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T2,T3
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
IdleSt->ErrorSt	315	Covered	T4,T9,T13
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T213,T214,T215
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T171,T172,T189
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T1,T12,T109
ReadSt->ReadWaitSt	252	Covered	T1,T2,T3
ReadWaitSt->ErrorSt	276	Covered	T164,T200,T216
ReadWaitSt->IdleSt	270	Covered	T1,T2,T3
ResetSt->ErrorSt	315	Covered	T76,T77,T78
ResetSt->IdleSt	196	Not Covered
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T1,T12,T109
CheckFailError	317	Covered	T77,T78,T152
FsmStateError	289	Covered	T4,T9,T13
MacroEccCorrError	221	Covered	T64,T40,T31
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T110,T100,T204
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T1,T12,T109
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T77,T78,T152
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T4,T9,T13
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T64,T80,T168
MacroEccCorrError->NoError	235	Covered	T40,T31,T104
NoError->AccessError	256	Covered	T1,T12,T109
NoError->CheckFailError	317	Covered	T77,T78,T152
NoError->FsmStateError	289	Covered	T4,T9,T13
NoError->MacroEccCorrError	221	Covered	T64,T40,T31

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T64,T80,T168
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T171,T172,T189
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T2,T5,T6
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T12,T109
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T40,T31,T104
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T164,T200,T216
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T25,T26,T27
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T4,T9,T13
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T4,T9,T17
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T4,T9,T17
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T4,T9,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T25,T26,T27

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T77,T78,T152
1	0	Covered	T77,T78,T152
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T4,T9,T13
1	0	Covered	T4,T9,T13
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	1379487533	1378600612	0	0
DigestKnown_A	1379487533	1378600612	0	0
DigestOffsetMustBeRepresentable_A	1109	1109	0	0
EccErrorState_A	1379487533	19162	0	0
ErrorKnown_A	1379487533	1378600612	0	0
FsmStateKnown_A	1379487533	1378600612	0	0
InitDoneKnown_A	1379487533	1378600612	0	0
InitReadLocksPartition_A	1379487533	253369933	0	0
InitWriteLocksPartition_A	1379487533	253369933	0	0
OffsetMustBeBlockAligned_A	1109	1109	0	0
OtpAddrKnown_A	1379487533	1378600612	0	0
OtpCmdKnown_A	1379487533	1378600612	0	0
OtpErrorState_A	1379487533	68	0	0
OtpReqKnown_A	1379487533	1378600612	0	0
OtpSizeKnown_A	1379487533	1378600612	0	0
OtpWdataKnown_A	1379487533	1378600612	0	0
ReadLockPropagation_A	1379487533	703219979	0	0
SizeMustBeBlockAligned_A	1109	1109	0	0
TlulGntKnown_A	1379487533	1378600612	0	0
TlulRdataKnown_A	1379487533	1378600612	0	0
TlulReadOnReadLock_A	1379487533	7244	0	0
TlulRerrorKnown_A	1379487533	1378600612	0	0
TlulRvalidKnown_A	1379487533	1378600612	0	0
WriteLockPropagation_A	1379487533	2887458	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	1379487533	30516703	0	0
u_state_regs_A	1379487533	1378600612	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	1378600612	0	0
T1	50198	49186	0	0
T2	43505	42693	0	0
T3	21778	21288	0	0
T4	28856	28587	0	0
T8	42278	41523	0	0
T9	26405	25983	0	0
T10	28040	27502	0	0
T11	14125	13827	0	0
T12	82791	81679	0	0
T13	14090	13816	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	1378600612	0	0
T1	50198	49186	0	0
T2	43505	42693	0	0
T3	21778	21288	0	0
T4	28856	28587	0	0
T8	42278	41523	0	0
T9	26405	25983	0	0
T10	28040	27502	0	0
T11	14125	13827	0	0
T12	82791	81679	0	0
T13	14090	13816	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1109	1109	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	19162	0	0
T15	216600	0	0	0
T48	11511	0	0	0
T77	13009	2412	0	0
T78	10208	3968	0	0
T86	14357	0	0	0
T152	0	2122	0	0
T165	0	3188	0	0
T167	0	2286	0	0
T173	0	2417	0	0
T174	0	2769	0	0
T176	38132	0	0	0
T177	24368	0	0	0
T178	30390	0	0	0
T179	100823	0	0	0
T180	75808	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	1378600612	0	0
T1	50198	49186	0	0
T2	43505	42693	0	0
T3	21778	21288	0	0
T4	28856	28587	0	0
T8	42278	41523	0	0
T9	26405	25983	0	0
T10	28040	27502	0	0
T11	14125	13827	0	0
T12	82791	81679	0	0
T13	14090	13816	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	1378600612	0	0
T1	50198	49186	0	0
T2	43505	42693	0	0
T3	21778	21288	0	0
T4	28856	28587	0	0
T8	42278	41523	0	0
T9	26405	25983	0	0
T10	28040	27502	0	0
T11	14125	13827	0	0
T12	82791	81679	0	0
T13	14090	13816	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	1378600612	0	0
T1	50198	49186	0	0
T2	43505	42693	0	0
T3	21778	21288	0	0
T4	28856	28587	0	0
T8	42278	41523	0	0
T9	26405	25983	0	0
T10	28040	27502	0	0
T11	14125	13827	0	0
T12	82791	81679	0	0
T13	14090	13816	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	253369933	0	0
T1	50198	874	0	0
T2	43505	761	0	0
T3	21778	471	0	0
T4	28856	15251	0	0
T8	42278	705	0	0
T9	26405	13180	0	0
T10	28040	786	0	0
T11	14125	226	0	0
T12	82791	917	0	0
T13	14090	3970	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	253369933	0	0
T1	50198	874	0	0
T2	43505	761	0	0
T3	21778	471	0	0
T4	28856	15251	0	0
T8	42278	705	0	0
T9	26405	13180	0	0
T10	28040	786	0	0
T11	14125	226	0	0
T12	82791	917	0	0
T13	14090	3970	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1109	1109	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	1378600612	0	0
T1	50198	49186	0	0
T2	43505	42693	0	0
T3	21778	21288	0	0
T4	28856	28587	0	0
T8	42278	41523	0	0
T9	26405	25983	0	0
T10	28040	27502	0	0
T11	14125	13827	0	0
T12	82791	81679	0	0
T13	14090	13816	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	1378600612	0	0
T1	50198	49186	0	0
T2	43505	42693	0	0
T3	21778	21288	0	0
T4	28856	28587	0	0
T8	42278	41523	0	0
T9	26405	25983	0	0
T10	28040	27502	0	0
T11	14125	13827	0	0
T12	82791	81679	0	0
T13	14090	13816	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	68	0	0
T6	145559	0	0	0
T101	56528	0	0	0
T145	11214	0	0	0
T164	0	2	0	0
T168	13609	0	0	0
T171	11137	1	0	0
T172	10652	1	0	0
T189	10075	1	0	0
T193	0	1	0	0
T194	0	1	0	0
T196	0	1	0	0
T197	0	1	0	0
T200	0	1	0	0
T202	0	1	0	0
T203	13346	0	0	0
T204	42372	0	0	0
T205	6445	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	1378600612	0	0
T1	50198	49186	0	0
T2	43505	42693	0	0
T3	21778	21288	0	0
T4	28856	28587	0	0
T8	42278	41523	0	0
T9	26405	25983	0	0
T10	28040	27502	0	0
T11	14125	13827	0	0
T12	82791	81679	0	0
T13	14090	13816	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	1378600612	0	0
T1	50198	49186	0	0
T2	43505	42693	0	0
T3	21778	21288	0	0
T4	28856	28587	0	0
T8	42278	41523	0	0
T9	26405	25983	0	0
T10	28040	27502	0	0
T11	14125	13827	0	0
T12	82791	81679	0	0
T13	14090	13816	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	1378600612	0	0
T1	50198	49186	0	0
T2	43505	42693	0	0
T3	21778	21288	0	0
T4	28856	28587	0	0
T8	42278	41523	0	0
T9	26405	25983	0	0
T10	28040	27502	0	0
T11	14125	13827	0	0
T12	82791	81679	0	0
T13	14090	13816	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	703219979	0	0
T1	50198	4950	0	0
T2	43505	325	0	0
T3	21778	0	0	0
T4	28856	15937	0	0
T5	0	294602	0	0
T8	42278	1028	0	0
T9	26405	0	0	0
T10	28040	0	0	0
T11	14125	0	0	0
T12	82791	22684	0	0
T13	14090	0	0	0
T40	0	5121	0	0
T108	0	832	0	0
T109	0	14464	0	0
T110	0	7475	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1109	1109	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	1378600612	0	0
T1	50198	49186	0	0
T2	43505	42693	0	0
T3	21778	21288	0	0
T4	28856	28587	0	0
T8	42278	41523	0	0
T9	26405	25983	0	0
T10	28040	27502	0	0
T11	14125	13827	0	0
T12	82791	81679	0	0
T13	14090	13816	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	1378600612	0	0
T1	50198	49186	0	0
T2	43505	42693	0	0
T3	21778	21288	0	0
T4	28856	28587	0	0
T8	42278	41523	0	0
T9	26405	25983	0	0
T10	28040	27502	0	0
T11	14125	13827	0	0
T12	82791	81679	0	0
T13	14090	13816	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	7244	0	0
T1	50198	3	0	0
T2	43505	0	0	0
T3	21778	0	0	0
T4	28856	2	0	0
T5	0	67	0	0
T8	42278	0	0	0
T9	26405	2	0	0
T10	28040	0	0	0
T11	14125	0	0	0
T12	82791	3	0	0
T13	14090	0	0	0
T17	0	1	0	0
T40	0	2	0	0
T96	0	6	0	0
T109	0	5	0	0
T110	0	8	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	1378600612	0	0
T1	50198	49186	0	0
T2	43505	42693	0	0
T3	21778	21288	0	0
T4	28856	28587	0	0
T8	42278	41523	0	0
T9	26405	25983	0	0
T10	28040	27502	0	0
T11	14125	13827	0	0
T12	82791	81679	0	0
T13	14090	13816	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	1378600612	0	0
T1	50198	49186	0	0
T2	43505	42693	0	0
T3	21778	21288	0	0
T4	28856	28587	0	0
T8	42278	41523	0	0
T9	26405	25983	0	0
T10	28040	27502	0	0
T11	14125	13827	0	0
T12	82791	81679	0	0
T13	14090	13816	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	2887458	0	0
T1	50198	2811	0	0
T2	43505	1143	0	0
T3	21778	0	0	0
T4	28856	0	0	0
T5	0	20055	0	0
T6	0	5721	0	0
T8	42278	0	0	0
T9	26405	0	0	0
T10	28040	0	0	0
T11	14125	0	0	0
T12	82791	10700	0	0
T13	14090	0	0	0
T20	0	8407	0	0
T40	0	6594	0	0
T96	0	14166	0	0
T101	0	10084	0	0
T102	0	3352	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	30516703	0	0
T1	50198	42064	0	0
T2	43505	34838	0	0
T3	21778	0	0	0
T4	28856	0	0	0
T5	0	389238	0	0
T8	42278	0	0	0
T9	26405	2472	0	0
T10	28040	0	0	0
T11	14125	0	0	0
T12	82791	71674	0	0
T13	14090	0	0	0
T31	0	52685	0	0
T40	0	32766	0	0
T96	0	90365	0	0
T109	0	5030	0	0
T110	0	2673	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	1378600612	0	0
T1	50198	49186	0	0
T2	43505	42693	0	0
T3	21778	21288	0	0
T4	28856	28587	0	0
T8	42278	41523	0	0
T9	26405	25983	0	0
T10	28040	27502	0	0
T11	14125	13827	0	0
T12	82791	81679	0	0
T13	14090	13816	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		90	90	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	67	67	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	34	33	97.06
Logical	34	33	97.06
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T169,T86,T170

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T17,T40,T31

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T4,T9,T13
1	Covered	T25,T26,T27

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T77,T167,T165
1	Covered	T77,T167,T165

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T4,T9,T13
1	Covered	T4,T9,T13

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00111101000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T9

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T9

---

FSM Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T4,T9,T13
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T4
ReadWaitSt	252	Covered	T1,T2,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
IdleSt->ErrorSt	315	Covered	T4,T9,T13
IdleSt->ReadSt	236	Covered	T1,T2,T4
InitSt->ErrorSt	315	Covered	T213,T214,T215
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T64,T116,T171
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T1,T2,T12
ReadSt->ReadWaitSt	252	Covered	T1,T2,T4
ReadWaitSt->ErrorSt	276	Covered	T201,T158,T217
ReadWaitSt->IdleSt	270	Covered	T1,T2,T4
ResetSt->ErrorSt	315	Covered	T76,T77,T78
ResetSt->IdleSt	196	Not Covered
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T1,T2,T12
CheckFailError	317	Covered	T77,T167,T165
FsmStateError	289	Covered	T4,T9,T13
MacroEccCorrError	221	Covered	T17,T40,T31
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T110,T5,T100
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T1,T2,T12
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T77,T167,T165
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T4,T9,T13
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T99,T169,T86
MacroEccCorrError->NoError	235	Covered	T17,T40,T31
NoError->AccessError	256	Covered	T1,T2,T12
NoError->CheckFailError	317	Covered	T77,T167,T165
NoError->FsmStateError	289	Covered	T4,T9,T13
NoError->MacroEccCorrError	221	Covered	T17,T40,T31

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T169,T86,T170
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T64,T116,T168
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T1,T2,T108
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T12
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T17,T40,T31
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T201,T158,T217
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T25,T26,T27
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T4,T9,T13
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T4,T110,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T4,T110,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T4,T9,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T25,T26,T27

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T77,T167,T165
1	0	Covered	T77,T167,T165
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T4,T9,T13
1	0	Covered	T4,T9,T13
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	1379487533	1378600612	0	0
DigestKnown_A	1379487533	1378600612	0	0
DigestOffsetMustBeRepresentable_A	1109	1109	0	0
EccErrorState_A	1379487533	15619	0	0
ErrorKnown_A	1379487533	1378600612	0	0
FsmStateKnown_A	1379487533	1378600612	0	0
InitDoneKnown_A	1379487533	1378600612	0	0
InitReadLocksPartition_A	1379487533	253552702	0	0
InitWriteLocksPartition_A	1379487533	253552702	0	0
OffsetMustBeBlockAligned_A	1109	1109	0	0
OtpAddrKnown_A	1379487533	1378600612	0	0
OtpCmdKnown_A	1379487533	1378600612	0	0
OtpErrorState_A	1379487533	57	0	0
OtpReqKnown_A	1379487533	1378600612	0	0
OtpSizeKnown_A	1379487533	1378600612	0	0
OtpWdataKnown_A	1379487533	1378600612	0	0
ReadLockPropagation_A	1379487533	706729073	0	0
SizeMustBeBlockAligned_A	1109	1109	0	0
TlulGntKnown_A	1379487533	1378600612	0	0
TlulRdataKnown_A	1379487533	1378600612	0	0
TlulReadOnReadLock_A	1379487533	7686	0	0
TlulRerrorKnown_A	1379487533	1378600612	0	0
TlulRvalidKnown_A	1379487533	1378600612	0	0
WriteLockPropagation_A	1379487533	1649223	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	1379487533	20175010	0	0
u_state_regs_A	1379487533	1378600612	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	1378600612	0	0
T1	50198	49186	0	0
T2	43505	42693	0	0
T3	21778	21288	0	0
T4	28856	28587	0	0
T8	42278	41523	0	0
T9	26405	25983	0	0
T10	28040	27502	0	0
T11	14125	13827	0	0
T12	82791	81679	0	0
T13	14090	13816	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	1378600612	0	0
T1	50198	49186	0	0
T2	43505	42693	0	0
T3	21778	21288	0	0
T4	28856	28587	0	0
T8	42278	41523	0	0
T9	26405	25983	0	0
T10	28040	27502	0	0
T11	14125	13827	0	0
T12	82791	81679	0	0
T13	14090	13816	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1109	1109	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	15619	0	0
T15	216600	0	0	0
T48	11511	0	0	0
T77	13009	2412	0	0
T78	10208	0	0	0
T86	14357	0	0	0
T165	0	3188	0	0
T167	0	2286	0	0
T173	0	2417	0	0
T174	0	2769	0	0
T175	0	2547	0	0
T176	38132	0	0	0
T177	24368	0	0	0
T178	30390	0	0	0
T179	100823	0	0	0
T180	75808	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	1378600612	0	0
T1	50198	49186	0	0
T2	43505	42693	0	0
T3	21778	21288	0	0
T4	28856	28587	0	0
T8	42278	41523	0	0
T9	26405	25983	0	0
T10	28040	27502	0	0
T11	14125	13827	0	0
T12	82791	81679	0	0
T13	14090	13816	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	1378600612	0	0
T1	50198	49186	0	0
T2	43505	42693	0	0
T3	21778	21288	0	0
T4	28856	28587	0	0
T8	42278	41523	0	0
T9	26405	25983	0	0
T10	28040	27502	0	0
T11	14125	13827	0	0
T12	82791	81679	0	0
T13	14090	13816	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	1378600612	0	0
T1	50198	49186	0	0
T2	43505	42693	0	0
T3	21778	21288	0	0
T4	28856	28587	0	0
T8	42278	41523	0	0
T9	26405	25983	0	0
T10	28040	27502	0	0
T11	14125	13827	0	0
T12	82791	81679	0	0
T13	14090	13816	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	253552702	0	0
T1	50198	1078	0	0
T2	43505	965	0	0
T3	21778	565	0	0
T4	28856	15302	0	0
T8	42278	858	0	0
T9	26405	13248	0	0
T10	28040	888	0	0
T11	14125	277	0	0
T12	82791	1138	0	0
T13	14090	4021	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	253552702	0	0
T1	50198	1078	0	0
T2	43505	965	0	0
T3	21778	565	0	0
T4	28856	15302	0	0
T8	42278	858	0	0
T9	26405	13248	0	0
T10	28040	888	0	0
T11	14125	277	0	0
T12	82791	1138	0	0
T13	14090	4021	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1109	1109	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	1378600612	0	0
T1	50198	49186	0	0
T2	43505	42693	0	0
T3	21778	21288	0	0
T4	28856	28587	0	0
T8	42278	41523	0	0
T9	26405	25983	0	0
T10	28040	27502	0	0
T11	14125	13827	0	0
T12	82791	81679	0	0
T13	14090	13816	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	1378600612	0	0
T1	50198	49186	0	0
T2	43505	42693	0	0
T3	21778	21288	0	0
T4	28856	28587	0	0
T8	42278	41523	0	0
T9	26405	25983	0	0
T10	28040	27502	0	0
T11	14125	13827	0	0
T12	82791	81679	0	0
T13	14090	13816	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	57	0	0
T17	39889	0	0	0
T19	10102	0	0	0
T40	60132	0	0	0
T45	18588	0	0	0
T64	11400	1	0	0
T66	18254	0	0	0
T67	14706	0	0	0
T108	15642	0	0	0
T109	29550	0	0	0
T110	15519	0	0	0
T116	0	1	0	0
T168	0	1	0	0
T190	0	1	0	0
T191	0	1	0	0
T192	0	1	0	0
T195	0	1	0	0
T198	0	1	0	0
T199	0	1	0	0
T201	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	1378600612	0	0
T1	50198	49186	0	0
T2	43505	42693	0	0
T3	21778	21288	0	0
T4	28856	28587	0	0
T8	42278	41523	0	0
T9	26405	25983	0	0
T10	28040	27502	0	0
T11	14125	13827	0	0
T12	82791	81679	0	0
T13	14090	13816	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	1378600612	0	0
T1	50198	49186	0	0
T2	43505	42693	0	0
T3	21778	21288	0	0
T4	28856	28587	0	0
T8	42278	41523	0	0
T9	26405	25983	0	0
T10	28040	27502	0	0
T11	14125	13827	0	0
T12	82791	81679	0	0
T13	14090	13816	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	1378600612	0	0
T1	50198	49186	0	0
T2	43505	42693	0	0
T3	21778	21288	0	0
T4	28856	28587	0	0
T8	42278	41523	0	0
T9	26405	25983	0	0
T10	28040	27502	0	0
T11	14125	13827	0	0
T12	82791	81679	0	0
T13	14090	13816	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	706729073	0	0
T1	50198	4444	0	0
T2	43505	1582	0	0
T3	21778	0	0	0
T4	28856	15420	0	0
T5	0	349735	0	0
T8	42278	0	0	0
T9	26405	0	0	0
T10	28040	0	0	0
T11	14125	0	0	0
T12	82791	15491	0	0
T13	14090	0	0	0
T40	0	6232	0	0
T96	0	22935	0	0
T108	0	407	0	0
T109	0	9370	0	0
T110	0	7608	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1109	1109	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	1378600612	0	0
T1	50198	49186	0	0
T2	43505	42693	0	0
T3	21778	21288	0	0
T4	28856	28587	0	0
T8	42278	41523	0	0
T9	26405	25983	0	0
T10	28040	27502	0	0
T11	14125	13827	0	0
T12	82791	81679	0	0
T13	14090	13816	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	1378600612	0	0
T1	50198	49186	0	0
T2	43505	42693	0	0
T3	21778	21288	0	0
T4	28856	28587	0	0
T8	42278	41523	0	0
T9	26405	25983	0	0
T10	28040	27502	0	0
T11	14125	13827	0	0
T12	82791	81679	0	0
T13	14090	13816	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	7686	0	0
T1	50198	4	0	0
T2	43505	1	0	0
T3	21778	0	0	0
T4	28856	2	0	0
T5	0	74	0	0
T8	42278	0	0	0
T9	26405	0	0	0
T10	28040	0	0	0
T11	14125	0	0	0
T12	82791	4	0	0
T13	14090	0	0	0
T31	0	6	0	0
T40	0	4	0	0
T96	0	2	0	0
T109	0	1	0	0
T110	0	14	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	1378600612	0	0
T1	50198	49186	0	0
T2	43505	42693	0	0
T3	21778	21288	0	0
T4	28856	28587	0	0
T8	42278	41523	0	0
T9	26405	25983	0	0
T10	28040	27502	0	0
T11	14125	13827	0	0
T12	82791	81679	0	0
T13	14090	13816	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	1378600612	0	0
T1	50198	49186	0	0
T2	43505	42693	0	0
T3	21778	21288	0	0
T4	28856	28587	0	0
T8	42278	41523	0	0
T9	26405	25983	0	0
T10	28040	27502	0	0
T11	14125	13827	0	0
T12	82791	81679	0	0
T13	14090	13816	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	1649223	0	0
T5	102504	26951	0	0
T6	0	49874	0	0
T20	76588	6125	0	0
T31	68573	2508	0	0
T80	14312	0	0	0
T95	6294	0	0	0
T96	118941	13482	0	0
T97	19274	0	0	0
T98	12828	0	0	0
T99	101208	0	0	0
T100	85743	0	0	0
T101	0	2913	0	0
T102	0	3092	0	0
T103	0	8691	0	0
T105	0	3953	0	0
T208	0	23659	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	20175010	0	0
T1	50198	41877	0	0
T2	43505	34668	0	0
T3	21778	0	0	0
T4	28856	0	0	0
T5	0	287257	0	0
T8	42278	0	0	0
T9	26405	2455	0	0
T10	28040	0	0	0
T11	14125	0	0	0
T12	82791	0	0	0
T13	14090	0	0	0
T20	0	66060	0	0
T31	0	58732	0	0
T64	0	3581	0	0
T96	0	106285	0	0
T100	0	3415	0	0
T116	0	2565	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1379487533	1378600612	0	0
T1	50198	49186	0	0
T2	43505	42693	0	0
T3	21778	21288	0	0
T4	28856	28587	0	0
T8	42278	41523	0	0
T9	26405	25983	0	0
T10	28040	27502	0	0
T11	14125	13827	0	0
T12	82791	81679	0	0
T13	14090	13816	0	0