Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.26	96.15	86.96	87.90		93.10	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1587414446	18198850	0	0
check_regwen_rd_A	1587414446	4603	0	0
check_timeout_rd_A	1587414446	4689	0	0
check_trigger_regwen_rd_A	1587414446	4508	0	0
consistency_check_period_rd_A	1587414446	5005	0	0
creator_sw_cfg_read_lock_rd_A	1587414446	4688	0	0
direct_access_address_rd_A	1587414446	3421	0	0
direct_access_wdata_0_rd_A	1587414446	2748	0	0
direct_access_wdata_1_rd_A	1587414446	3228	0	0
integrity_check_period_rd_A	1587414446	4298	0	0
intr_enable_rd_A	1587414446	5029	0	0
owner_sw_cfg_read_lock_rd_A	1587414446	4219	0	0
rot_creator_auth_codesign_read_lock_rd_A	1587414446	4521	0	0
rot_creator_auth_state_read_lock_rd_A	1587414446	4195	0	0
vendor_test_read_lock_rd_A	1587414446	4516	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1587414446	18198850	0	0
T6	333137	379165	0	0
T7	306405	327053	0	0
T8	39803	0	0	0
T15	0	60067	0	0
T31	15778	0	0	0
T33	0	244458	0	0
T40	71090	0	0	0
T80	14252	0	0	0
T92	17060	0	0	0
T93	110231	0	0	0
T128	0	44084	0	0
T129	0	161096	0	0
T130	0	395544	0	0
T141	21968	0	0	0
T182	26016	0	0	0
T200	0	205221	0	0
T232	0	93259	0	0
T240	0	46466	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1587414446	4603	0	0
T7	306405	347	0	0
T8	39803	0	0	0
T15	0	54	0	0
T16	99017	0	0	0
T31	15778	0	0	0
T33	0	114	0	0
T94	141418	0	0	0
T183	4241	0	0	0
T184	48710	0	0	0
T215	0	347	0	0
T230	0	285	0	0
T235	10392	0	0	0
T261	112325	0	0	0
T278	0	373	0	0
T286	0	253	0	0
T288	0	132	0	0
T314	0	443	0	0
T317	0	28	0	0
T318	16437	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1587414446	4689	0	0
T7	306405	329	0	0
T8	39803	0	0	0
T15	0	85	0	0
T16	99017	0	0	0
T31	15778	0	0	0
T33	0	171	0	0
T94	141418	0	0	0
T183	4241	0	0	0
T184	48710	0	0	0
T215	0	362	0	0
T230	0	255	0	0
T235	10392	0	0	0
T261	112325	0	0	0
T278	0	363	0	0
T286	0	395	0	0
T288	0	147	0	0
T314	0	502	0	0
T317	0	34	0	0
T318	16437	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1587414446	4508	0	0
T7	306405	313	0	0
T8	39803	0	0	0
T15	0	42	0	0
T16	99017	0	0	0
T31	15778	0	0	0
T33	0	100	0	0
T94	141418	0	0	0
T183	4241	0	0	0
T184	48710	0	0	0
T215	0	305	0	0
T230	0	310	0	0
T235	10392	0	0	0
T261	112325	0	0	0
T278	0	365	0	0
T286	0	310	0	0
T288	0	111	0	0
T314	0	354	0	0
T317	0	21	0	0
T318	16437	0	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1587414446	5005	0	0
T7	306405	416	0	0
T8	39803	0	0	0
T15	0	93	0	0
T16	99017	0	0	0
T31	15778	0	0	0
T33	0	152	0	0
T94	141418	0	0	0
T183	4241	0	0	0
T184	48710	0	0	0
T215	0	365	0	0
T230	0	281	0	0
T235	10392	0	0	0
T261	112325	0	0	0
T278	0	355	0	0
T286	0	443	0	0
T288	0	137	0	0
T314	0	480	0	0
T317	0	56	0	0
T318	16437	0	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1587414446	4688	0	0
T7	306405	349	0	0
T8	39803	0	0	0
T15	0	90	0	0
T16	99017	0	0	0
T31	15778	0	0	0
T33	0	128	0	0
T94	141418	0	0	0
T183	4241	0	0	0
T184	48710	0	0	0
T215	0	252	0	0
T230	0	260	0	0
T235	10392	0	0	0
T261	112325	0	0	0
T278	0	364	0	0
T286	0	334	0	0
T288	0	129	0	0
T314	0	490	0	0
T317	0	31	0	0
T318	16437	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1587414446	3421	0	0
T7	306405	412	0	0
T8	39803	0	0	0
T15	0	79	0	0
T16	99017	0	0	0
T31	15778	0	0	0
T33	0	118	0	0
T94	141418	0	0	0
T183	4241	0	0	0
T184	48710	0	0	0
T215	0	287	0	0
T230	0	309	0	0
T235	10392	0	0	0
T261	112325	0	0	0
T278	0	430	0	0
T286	0	349	0	0
T288	0	145	0	0
T314	0	370	0	0
T317	0	14	0	0
T318	16437	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1587414446	2748	0	0
T7	306405	392	0	0
T8	39803	0	0	0
T15	0	30	0	0
T16	99017	0	0	0
T31	15778	0	0	0
T33	0	69	0	0
T94	141418	0	0	0
T183	4241	0	0	0
T184	48710	0	0	0
T215	0	276	0	0
T230	0	259	0	0
T235	10392	0	0	0
T261	112325	0	0	0
T278	0	336	0	0
T286	0	316	0	0
T288	0	110	0	0
T314	0	337	0	0
T317	0	5	0	0
T318	16437	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1587414446	3228	0	0
T7	306405	303	0	0
T8	39803	0	0	0
T15	0	84	0	0
T16	99017	0	0	0
T31	15778	0	0	0
T33	0	95	0	0
T94	141418	0	0	0
T183	4241	0	0	0
T184	48710	0	0	0
T215	0	276	0	0
T230	0	294	0	0
T235	10392	0	0	0
T261	112325	0	0	0
T278	0	397	0	0
T286	0	295	0	0
T288	0	125	0	0
T314	0	378	0	0
T317	0	22	0	0
T318	16437	0	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1587414446	4298	0	0
T7	306405	274	0	0
T8	39803	0	0	0
T15	0	42	0	0
T16	99017	0	0	0
T31	15778	0	0	0
T33	0	128	0	0
T94	141418	0	0	0
T183	4241	0	0	0
T184	48710	0	0	0
T215	0	251	0	0
T230	0	302	0	0
T235	10392	0	0	0
T261	112325	0	0	0
T278	0	321	0	0
T286	0	319	0	0
T288	0	178	0	0
T314	0	326	0	0
T317	0	25	0	0
T318	16437	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1587414446	5029	0	0
T7	306405	246	0	0
T8	39803	0	0	0
T15	0	88	0	0
T16	99017	0	0	0
T31	15778	0	0	0
T33	0	109	0	0
T94	141418	0	0	0
T183	4241	0	0	0
T184	48710	0	0	0
T215	0	212	0	0
T235	10392	0	0	0
T261	112325	0	0	0
T278	0	354	0	0
T314	0	394	0	0
T318	16437	0	0	0
T319	0	17	0	0
T320	0	13	0	0
T321	0	51	0	0
T322	0	15	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1587414446	4219	0	0
T7	306405	284	0	0
T8	39803	0	0	0
T15	0	75	0	0
T16	99017	0	0	0
T31	15778	0	0	0
T33	0	113	0	0
T94	141418	0	0	0
T183	4241	0	0	0
T184	48710	0	0	0
T215	0	311	0	0
T230	0	273	0	0
T235	10392	0	0	0
T261	112325	0	0	0
T278	0	333	0	0
T286	0	281	0	0
T288	0	116	0	0
T314	0	298	0	0
T317	0	14	0	0
T318	16437	0	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1587414446	4521	0	0
T7	306405	330	0	0
T8	39803	0	0	0
T15	0	89	0	0
T16	99017	0	0	0
T31	15778	0	0	0
T33	0	177	0	0
T94	141418	0	0	0
T183	4241	0	0	0
T184	48710	0	0	0
T215	0	352	0	0
T230	0	271	0	0
T235	10392	0	0	0
T261	112325	0	0	0
T278	0	391	0	0
T286	0	351	0	0
T288	0	128	0	0
T314	0	387	0	0
T317	0	22	0	0
T318	16437	0	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1587414446	4195	0	0
T7	306405	279	0	0
T8	39803	0	0	0
T15	0	53	0	0
T16	99017	0	0	0
T31	15778	0	0	0
T33	0	91	0	0
T94	141418	0	0	0
T183	4241	0	0	0
T184	48710	0	0	0
T215	0	324	0	0
T230	0	278	0	0
T235	10392	0	0	0
T261	112325	0	0	0
T278	0	350	0	0
T286	0	238	0	0
T288	0	110	0	0
T314	0	388	0	0
T317	0	20	0	0
T318	16437	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1587414446	4516	0	0
T7	306405	327	0	0
T8	39803	0	0	0
T15	0	90	0	0
T16	99017	0	0	0
T31	15778	0	0	0
T33	0	119	0	0
T94	141418	0	0	0
T183	4241	0	0	0
T184	48710	0	0	0
T215	0	370	0	0
T230	0	302	0	0
T235	10392	0	0	0
T261	112325	0	0	0
T278	0	489	0	0
T286	0	317	0	0
T288	0	134	0	0
T314	0	364	0	0
T317	0	41	0	0
T318	16437	0	0	0