Unified Coverage Report :: Module :: otp_ctrl

Module : otp_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.13	96.15	86.96	87.26		93.10	97.18

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	92.26	96.15	86.96	87.90		93.10	97.18

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.26	96.15	86.96	87.90		93.10	97.18

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.84	91.65	90.25	89.67	73.30	91.86	96.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
core_tlul_assert_device	100.00	100.00				100.00	100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
gen_alert_tx[2].u_prim_alert_sender	100.00			100.00
gen_alert_tx[3].u_prim_alert_sender	100.00			100.00
gen_alert_tx[4].u_prim_alert_sender	77.78			77.78
gen_bufs[0].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
gen_bufs[0].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[10].u_prim_mubi8_sender_read_lock	79.17	37.50				100.00	100.00
gen_bufs[10].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[1].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
gen_bufs[1].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[2].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
gen_bufs[2].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[3].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
gen_bufs[3].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[4].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
gen_bufs[4].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[5].u_prim_mubi8_sender_read_lock	79.17	37.50				100.00	100.00
gen_bufs[5].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[6].u_prim_mubi8_sender_read_lock	79.17	37.50				100.00	100.00
gen_bufs[6].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[7].u_prim_mubi8_sender_read_lock	79.17	37.50				100.00	100.00
gen_bufs[7].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[8].u_prim_mubi8_sender_read_lock	79.17	37.50				100.00	100.00
gen_bufs[8].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[9].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
gen_bufs[9].u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_partitions[0].gen_unbuffered.u_part_unbuf	90.91	94.96	93.55	97.87	72.00	89.83	97.22
gen_partitions[10].gen_lifecycle.u_part_buf	69.67	72.35	75.00	69.91	40.43	74.63	85.71
gen_partitions[1].gen_unbuffered.u_part_unbuf	96.86	100.00	97.06	97.87	88.00	98.25	100.00
gen_partitions[2].gen_unbuffered.u_part_unbuf	96.86	100.00	97.06	97.87	88.00	98.25	100.00
gen_partitions[3].gen_unbuffered.u_part_unbuf	92.98	100.00	97.06	97.87	64.71	98.25	100.00
gen_partitions[4].gen_unbuffered.u_part_unbuf	92.98	100.00	97.06	97.87	64.71	98.25	100.00
gen_partitions[5].gen_buffered.u_part_buf	83.31	84.06	85.42	93.85	69.44	80.72	86.36
gen_partitions[6].gen_buffered.u_part_buf	79.94	83.57	81.25	95.40	58.33	74.70	86.36
gen_partitions[7].gen_buffered.u_part_buf	88.03	93.95	86.54	94.30	70.21	87.50	95.65
gen_partitions[8].gen_buffered.u_part_buf	87.93	93.95	86.54	93.73	70.21	87.50	95.65
gen_partitions[9].gen_buffered.u_part_buf	88.29	93.95	86.54	93.73	72.34	87.50	95.65
otp_ctrl_core_csr_assert	100.00						100.00
prim_tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_arb	94.45	92.31	92.16			100.00	93.33
u_intr_error	100.00	100.00	100.00			100.00	100.00
u_intr_operation_done	100.00	100.00	100.00			100.00	100.00
u_keygmr_key_valid	100.00	100.00				100.00
u_otp	96.25	91.86	94.82	100.00	100.00	90.83	100.00
u_otp_arb	95.90	98.07	91.77			100.00	93.75
u_otp_ctrl_dai	89.44	84.75	89.71	100.00	87.72	87.25	87.23
u_otp_ctrl_kdi	96.51	99.26	96.86	100.00	90.91	94.68	97.37
u_otp_ctrl_lci	100.00	100.00	100.00	100.00	100.00	100.00	100.00
u_otp_ctrl_lfsr_timer	97.85	100.00	96.25	90.87	100.00	100.00	100.00
u_otp_ctrl_scrmbl	96.62	81.50	100.00	100.00	100.00	98.21	100.00
u_otp_init_sync	100.00	100.00				100.00
u_otp_rsp_fifo	94.70	100.00	78.79			100.00	100.00
u_part_sel_idx	74.36	65.65	89.08			88.89	53.85
u_prim_edn_req	92.19	100.00	93.75			100.00	75.00
u_prim_lc_sender_otp_broadcast_valid	100.00	100.00				100.00
u_prim_lc_sender_rma_token_valid	100.00	100.00				100.00
u_prim_lc_sender_secrets_valid	100.00	100.00				100.00
u_prim_lc_sender_test_tokens_valid	100.00	100.00				100.00
u_prim_lc_sync_check_byp_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_creator_seed_sw_rw_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_dft_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_escalate_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_owner_seed_sw_rw_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_seed_hw_rd_en	100.00	100.00				100.00	100.00
u_reg_core	99.06	99.65	95.67	100.00		100.00	100.00
u_scrmbl_mtx	68.55	75.00	71.37			84.09	43.75
u_tlul_adapter_sram	91.72	89.54	84.55			92.77	100.00
u_tlul_lc_gate	96.93	100.00	100.00		100.00	97.14	87.50

Line Coverage for Module : otp_ctrl

	Line No.	Total	Covered	Percent
TOTAL		156	150	96.15
CONT_ASSIGN	246	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
ALWAYS	279	14	13	92.86
ALWAYS	303	3	3	100.00
ALWAYS	319	11	10	90.91
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	381	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	389	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	399	1	1	100.00
ALWAYS	402	5	5	100.00
ALWAYS	429	19	19	100.00
CONT_ASSIGN	483	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
ALWAYS	494	9	9	100.00
ALWAYS	516	10	10	100.00
CONT_ASSIGN	580	1	1	100.00
CONT_ASSIGN	588	1	1	100.00
CONT_ASSIGN	635	1	1	100.00
CONT_ASSIGN	637	1	1	100.00
CONT_ASSIGN	760	1	1	100.00
CONT_ASSIGN	761	1	1	100.00
CONT_ASSIGN	762	1	1	100.00
CONT_ASSIGN	792	1	1	100.00
CONT_ASSIGN	794	1	1	100.00
ALWAYS	871	2	2	100.00
ALWAYS	929	2	2	100.00
ALWAYS	956	4	4	100.00
CONT_ASSIGN	983	1	1	100.00
ALWAYS	986	3	3	100.00
CONT_ASSIGN	1038	1	1	100.00
CONT_ASSIGN	1040	1	1	100.00
CONT_ASSIGN	1074	1	0	0.00
CONT_ASSIGN	1125	1	0	0.00
CONT_ASSIGN	1180	1	1	100.00
CONT_ASSIGN	1180	1	1	100.00
CONT_ASSIGN	1180	1	1	100.00
CONT_ASSIGN	1180	1	1	100.00
CONT_ASSIGN	1180	1	1	100.00
CONT_ASSIGN	1235	1	1	100.00
CONT_ASSIGN	1235	1	0	0.00
CONT_ASSIGN	1235	1	1	100.00
CONT_ASSIGN	1235	1	1	100.00
CONT_ASSIGN	1235	1	1	100.00
CONT_ASSIGN	1295	1	1	100.00
CONT_ASSIGN	1307	1	0	0.00
CONT_ASSIGN	1331	1	1	100.00
ALWAYS	1343	2	2	100.00
CONT_ASSIGN	1357	1	1	100.00
ALWAYS	1385	9	9	100.00
CONT_ASSIGN	1416	1	1	100.00
CONT_ASSIGN	1417	1	1	100.00
CONT_ASSIGN	1419	1	1	100.00
CONT_ASSIGN	1421	1	1	100.00
CONT_ASSIGN	1425	1	1	100.00
CONT_ASSIGN	1427	1	1	100.00
CONT_ASSIGN	1429	1	1	100.00
CONT_ASSIGN	1434	1	1	100.00
CONT_ASSIGN	1436	1	1	100.00
CONT_ASSIGN	1438	1	1	100.00
CONT_ASSIGN	1470	1	1	100.00
CONT_ASSIGN	1472	1	1	100.00
CONT_ASSIGN	1476	1	1	100.00
CONT_ASSIGN	1480	1	1	100.00
CONT_ASSIGN	1484	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
246	1	1
248	10	10
279	1	1
280	1	1
281	1	1
282	1	1
283	1	1
284	1	1
287	0	1
			MISSING_ELSE
292	1	1
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
303	1	1
304	1	1
306	1	1
319	1	1
324	1	1
325	1	1
329	1	1
330	1	1
331	1	1
332	1	1
			MISSING_ELSE
			MISSING_ELSE
336	1	1
337	1	1
338	1	1
339	0	1
			MISSING_ELSE
			MISSING_ELSE
377	1	1
381	1	1
385	1	1
389	1	1
390	1	1
398	1	1
399	1	1
402	1	1
403	1	1
405	1	1
407	1	1
408	1	1
429	1	1
430	1	1
431	1	1
433	1	1
435	1	1
438	1	1
440	1	1
443	1	1
444	1	1
			MISSING_ELSE
448	1	1
450	1	1
454	1	1
457	1	1
459	1	1
464	1	1
465	1	1
			MISSING_ELSE
467	1	1
468	1	1
			MISSING_ELSE
473	1	1
483	1	1
491	1	1
494	1	1
495	1	1
496	1	1
497	1	1
498	1	1
500	1	1
501	1	1
502	1	1
503	1	1
516	1	1
518	1	1
520	1	1
522	1	1
524	1	1
533	1	1
535	1	1
536	1	1
537	1	1
538	1	1
580	1	1
588	1	1
635	1	1
637	1	1
760	1	1
761	1	1
762	1	1
792	1	1
794	1	1
871	1	1
872	1	1
929	1	1
930	1	1
956	1	1
957	1	1
958	1	1
959	1	1
983	1	1
986	1	1
987	1	1
989	1	1
1038	1	1
1040	1	1
1074	0	1
1125	0	1
1180	5	5
1235	4	5
1295	1	1
1307	0	1
1331	1	1
1343	1	1
1344	1	1
1357	1	1
1385	1	1
1386	1	1
1387	1	1
1388	1	1
1390	1	1
1391	1	1
1392	1	1
1393	1	1
1394	1	1
1416	1	1
1417	1	1
1419	1	1
1421	1	1
1425	1	1
1427	1	1
1429	1	1
1434	1	1
1436	1	1
1438	1	1
1470	1	1
1472	1	1
1476	1	1
1480	1	1
1484	1	1

---

Cond Coverage for Module : otp_ctrl

	Total	Covered	Percent
Conditions	115	100	86.96
Logical	115	100	86.96
Non-Logical	0	0
Event	0	0

 LINE       248
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b00001000000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[1].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       248
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b00111101000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[2].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       248
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b10001111000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[3].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       248
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11001010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[4].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T15
1	1	Covered	T1,T2,T3

 LINE       248
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11001111000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[5].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T15
1	1	Covered	T6,T7,T15

 LINE       248
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011000000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[6].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T15
1	1	Covered	T6,T7,T15

 LINE       248
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[7].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T15
1	1	Covered	T6,T7,T15

 LINE       248
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011111000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[8].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T15
1	1	Covered	T6,T7,T15

 LINE       248
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11101010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[9].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T15
1	1	Covered	T6,T7,T15

 LINE       248
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11110101000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[10].PartEnd))
             -------------------1------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T6,T7,T15

 LINE       283
 EXPRESSION (tlul_part_sel_oh != '0)
            ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       292
 EXPRESSION (((|part_tlul_gnt)) | tlul_oob_err_q)
             ---------1--------   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       293
 EXPRESSION (((|part_tlul_rvalid)) | tlul_oob_err_q)
             ----------1----------   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       377
 EXPRESSION ((reg2hw.direct_access_regwen.qe && ((!reg2hw.direct_access_regwen.q))) ? 1'b0 : direct_access_regwen_q)
             -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       377
 SUB-EXPRESSION (reg2hw.direct_access_regwen.qe && ((!reg2hw.direct_access_regwen.q)))
                 ---------------1--------------    -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       381
 EXPRESSION (reg2hw.direct_access_cmd.digest.qe | reg2hw.direct_access_cmd.wr.qe | reg2hw.direct_access_cmd.rd.qe)
             -----------------1----------------   ---------------2--------------   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       398
 EXPRESSION (lci_prog_idle & dai_prog_idle)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       431
 EXPRESSION (fatal_bus_integ_error_q | ((|intg_error)))
             -----------1-----------   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T28,T29,T30
1	0	Not Covered

 LINE       440
 EXPRESSION (part_error[k] == MacroError)
            --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       444
 EXPRESSION (part_error[k] == MacroEccUncorrError)
            -------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T12,T14

 LINE       464
 EXPRESSION (fatal_macro_error_q || fatal_check_error_q)
             ---------1---------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T13,T44
1	0	Covered	T10,T12,T14

 LINE       473
 EXPRESSION (chk_timeout | lfsr_fsm_err | scrmbl_fsm_err | ((|part_fsm_err)))
             -----1-----   ------2-----   -------3------   --------4--------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T10,T12,T14
0	0	1	0	Covered	T28,T29,T30
0	1	0	0	Covered	T28,T29,T30
1	0	0	0	Covered	T23,T65,T6

 LINE       522
 EXPRESSION (direct_access_regwen_q & dai_idle)
             -----------1----------   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       588
 SUB-EXPRESSION (reg2hw.alert_test.recov_prim_otp_alert.q & reg2hw.alert_test.recov_prim_otp_alert.qe)
                 --------------------1-------------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T127,T183
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T127,T183

 LINE       588
 SUB-EXPRESSION (reg2hw.alert_test.fatal_prim_otp_alert.q & reg2hw.alert_test.fatal_prim_otp_alert.qe)
                 --------------------1-------------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T127,T183
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T127,T183

 LINE       588
 SUB-EXPRESSION (reg2hw.alert_test.fatal_bus_integ_error.q & reg2hw.alert_test.fatal_bus_integ_error.qe)
                 --------------------1--------------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T127,T183
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T127,T183

 LINE       588
 SUB-EXPRESSION (reg2hw.alert_test.fatal_check_error.q & reg2hw.alert_test.fatal_check_error.qe)
                 ------------------1------------------   -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T127,T183
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T127,T183

 LINE       588
 SUB-EXPRESSION (reg2hw.alert_test.fatal_macro_error.q & reg2hw.alert_test.fatal_macro_error.qe)
                 ------------------1------------------   -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T127,T183
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T127,T183

 LINE       635
 EXPRESSION (reg2hw.check_trigger.integrity.q & reg2hw.check_trigger.integrity.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T9

 LINE       637
 EXPRESSION (reg2hw.check_trigger.consistency.q & reg2hw.check_trigger.consistency.qe)
             -----------------1----------------   -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       760
 EXPRESSION (otp_prim_ready & otp_rsp_fifo_ready)
             -------1------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       761
 EXPRESSION (otp_arb_valid & otp_rsp_fifo_ready)
             ------1------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       762
 EXPRESSION (otp_prim_ready & otp_prim_valid)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       872
 EXPRESSION (otp_rvalid & otp_fifo_valid)
             -----1----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       1416
 EXPRESSION (part_digest[Secret1Idx] != '0)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1434
 EXPRESSION ((part_digest[Secret0Idx] != '0) ? On : Off)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       1434
 SUB-EXPRESSION (part_digest[Secret0Idx] != '0)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       1436
 EXPRESSION ((part_digest[Secret2Idx] != '0) ? On : Off)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1436
 SUB-EXPRESSION (part_digest[Secret2Idx] != '0)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1438
 EXPRESSION ((part_digest[Secret2Idx] != '0) ? On : Off)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1438
 SUB-EXPRESSION (part_digest[Secret2Idx] != '0)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Toggle Coverage for Module : otp_ctrl

	Total	Covered	Percent
Totals	155	141	90.97
Total Bits	11096	9682	87.26
Total Bits 0->1	5548	4841	87.26
Total Bits 1->0	5548	4841	87.26

Ports	155	141	90.97
Port Bits	11096	9682	87.26
Port Bits 0->1	5548	4841	87.26
Port Bits 1->0	5548	4841	87.26

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_o.edn_req	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
edn_i.edn_fips	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
edn_i.edn_ack	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
core_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T12,T44	Yes	T4,T12,T44	INPUT
core_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
core_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
core_tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_error	Yes	Yes	T1,T3,T9	Yes	T1,T3,T9	OUTPUT
core_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
prim_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
prim_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
prim_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
prim_tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T12,T5	Yes	T1,T5,T44	INPUT
prim_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
prim_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
prim_tl_i.a_mask[3:0]	Yes	Yes	T1,T12,T5	Yes	T1,T11,T5	INPUT
prim_tl_i.a_address[31:0]	Yes	Yes	T1,T12,T5	Yes	T1,T12,T5	INPUT
prim_tl_i.a_source[7:0]	Yes	Yes	T1,T3,T9	Yes	T1,T3,T9	INPUT
prim_tl_i.a_size[1:0]	Yes	Yes	T1,T12,T5	Yes	T1,T12,T5	INPUT
prim_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
prim_tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
prim_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
prim_tl_o.a_ready	Yes	Yes	T1,T11,T5	Yes	T1,T11,T5	OUTPUT
prim_tl_o.d_error	Yes	Yes	T11,T5,T127	Yes	T5,T103,T6	OUTPUT
prim_tl_o.d_user.data_intg[6:0]	Yes	Yes	T5,T103,T6	Yes	T5,T103,T6	OUTPUT
prim_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
prim_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_data[31:0]	Yes	Yes	T11,T5,T127	Yes	T5,T103,T6	OUTPUT
prim_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_source[7:0]	Yes	Yes	T2,T3,T9	Yes	T2,T3,T9	OUTPUT
prim_tl_o.d_size[1:0]	Yes	Yes	T6,T7,T15	Yes	T6,T7,T15	OUTPUT
prim_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
prim_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
intr_otp_operation_done_o	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
intr_otp_error_o	Yes	Yes	T1,T4,T14	Yes	T1,T4,T14	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T9,T10,T11	Yes	T9,T10,T11	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T11,T127,T183	Yes	T11,T127,T183	INPUT
alert_rx_i[2].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[3].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T11,T127,T183	Yes	T11,T127,T183	INPUT
alert_rx_i[3].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[3].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[4].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[4].ack_p	Yes	Yes	T11,T127,T183	Yes	T11,T127,T183	INPUT
alert_rx_i[4].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[4].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T9,T10,T11	Yes	T9,T10,T11	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T11,T127,T183	Yes	T11,T127,T183	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T11,T127,T183	Yes	T11,T127,T183	OUTPUT
alert_tx_o[4].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[4].alert_p	Yes	Yes	T11,T127,T183	Yes	T11,T127,T183	OUTPUT
obs_ctrl_i.obmen[3:0]	No	No		No		INPUT
obs_ctrl_i.obmsl[3:0]	No	No		No		INPUT
obs_ctrl_i.obgsl[3:0]	No	No		No		INPUT
otp_obs_o[7:0]	Unreachable	Unreachable		Unreachable		OUTPUT
otp_ast_pwr_seq_o.pwr_seq[1:0]	No	No		No		OUTPUT
otp_ast_pwr_seq_h_i.pwr_seq_h[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T13,T23	INPUT
pwr_otp_i.otp_init	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwr_otp_o.otp_idle	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwr_otp_o.otp_done	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
lc_otp_vendor_test_i.ctrl[31:0]	No	No		No		INPUT
lc_otp_vendor_test_o.status[31:0]	No	No		No		OUTPUT
lc_otp_program_i.count[383:0]	Yes	Yes	T6,T98,T15	Yes	T15,T239,T130	INPUT
lc_otp_program_i.state[319:0]	Yes	Yes	T238,T130,T240	Yes	T239,T130,T240	INPUT
lc_otp_program_i.req	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
lc_otp_program_o.ack	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
lc_otp_program_o.err	Yes	Yes	T6,T15,T238	Yes	T6,T15,T238	OUTPUT
lc_creator_seed_sw_rw_en_i[3:0]	Yes	Yes	T1,T9,T4	Yes	T1,T9,T4	INPUT
lc_owner_seed_sw_rw_en_i[3:0]	Yes	Yes	T1,T3,T9	Yes	T1,T3,T9	INPUT
lc_seed_hw_rd_en_i[3:0]	Yes	Yes	T1,T4,T10	Yes	T1,T3,T9	INPUT
lc_dft_en_i[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T11,T5	INPUT
lc_escalate_en_i[3:0]	Yes	Yes	T9,T13,T66	Yes	T9,T13,T66	INPUT
lc_check_byp_en_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
otp_lc_data_o.rma_token[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.rma_token_valid[3:0]	Yes	Yes	T1,T4,T23	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.test_exit_token[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.test_unlock_token[127:0]	Yes	Yes	T1,T40,T94	Yes	T1,T3,T40	OUTPUT
otp_lc_data_o.test_tokens_valid[3:0]	Yes	Yes	T1,T4,T5	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.secrets_valid[3:0]	Yes	Yes	T1,T4,T23	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[14:0]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[16:15]	No	No		No		OUTPUT
otp_lc_data_o.count[28:17]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[29]	No	No		No		OUTPUT
otp_lc_data_o.count[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[32:31]	No	No		No		OUTPUT
otp_lc_data_o.count[54:33]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[55]	No	No		No		OUTPUT
otp_lc_data_o.count[61:56]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[62]	No	No		No		OUTPUT
otp_lc_data_o.count[64:63]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[65]	No	No		No		OUTPUT
otp_lc_data_o.count[78:66]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[79]	No	No		No		OUTPUT
otp_lc_data_o.count[85:80]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[86]	No	No		No		OUTPUT
otp_lc_data_o.count[88:87]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[89]	No	No		No		OUTPUT
otp_lc_data_o.count[100:90]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[102:101]	No	No		No		OUTPUT
otp_lc_data_o.count[104:103]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[105]	No	No		No		OUTPUT
otp_lc_data_o.count[115:106]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[116]	No	No		No		OUTPUT
otp_lc_data_o.count[134:117]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[135]	No	No		No		OUTPUT
otp_lc_data_o.count[137:136]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[138]	No	No		No		OUTPUT
otp_lc_data_o.count[142:139]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[143]	No	No		No		OUTPUT
otp_lc_data_o.count[150:144]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[151]	No	No		No		OUTPUT
otp_lc_data_o.count[158:152]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[159]	No	No		No		OUTPUT
otp_lc_data_o.count[165:160]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[166]	No	No		No		OUTPUT
otp_lc_data_o.count[171:167]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[172]	No	No		No		OUTPUT
otp_lc_data_o.count[174:173]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[175]	No	No		No		OUTPUT
otp_lc_data_o.count[176]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[177]	No	No		No		OUTPUT
otp_lc_data_o.count[185:178]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[187:186]	No	No		No		OUTPUT
otp_lc_data_o.count[188]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[189]	No	No		No		OUTPUT
otp_lc_data_o.count[194:190]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[195]	No	No		No		OUTPUT
otp_lc_data_o.count[202:196]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[203]	No	No		No		OUTPUT
otp_lc_data_o.count[207:204]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[208]	No	No		No		OUTPUT
otp_lc_data_o.count[215:209]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[216]	No	No		No		OUTPUT
otp_lc_data_o.count[217]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[219:218]	No	No		No		OUTPUT
otp_lc_data_o.count[225:220]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[226]	No	No		No		OUTPUT
otp_lc_data_o.count[228:227]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[229]	No	No		No		OUTPUT
otp_lc_data_o.count[232:230]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[233]	No	No		No		OUTPUT
otp_lc_data_o.count[237:234]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[238]	No	No		No		OUTPUT
otp_lc_data_o.count[240:239]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[241]	No	No		No		OUTPUT
otp_lc_data_o.count[254:242]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[255]	No	No		No		OUTPUT
otp_lc_data_o.count[257:256]	Yes	Yes	T1,T4,T23	Yes	T1,T4,T23	OUTPUT
otp_lc_data_o.count[258]	No	No		No		OUTPUT
otp_lc_data_o.count[266:259]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[267]	No	No		No		OUTPUT
otp_lc_data_o.count[284:268]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[286:285]	No	No		No		OUTPUT
otp_lc_data_o.count[301:287]	Yes	Yes	T1,T4,*T23	Yes	T1,T4,T23	OUTPUT
otp_lc_data_o.count[304:302]	No	No		No		OUTPUT
otp_lc_data_o.count[324:305]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[325]	No	No		No		OUTPUT
otp_lc_data_o.count[327:326]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[328]	No	No		No		OUTPUT
otp_lc_data_o.count[330:329]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[331]	No	No		No		OUTPUT
otp_lc_data_o.count[335:332]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[336]	No	No		No		OUTPUT
otp_lc_data_o.count[343:337]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[344]	No	No		No		OUTPUT
otp_lc_data_o.count[345]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[346]	No	No		No		OUTPUT
otp_lc_data_o.count[366:347]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[367]	No	No		No		OUTPUT
otp_lc_data_o.count[371:368]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[372]	No	No		No		OUTPUT
otp_lc_data_o.count[375:373]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[376]	No	No		No		OUTPUT
otp_lc_data_o.count[383:377]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[5:0]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[6]	No	No		No		OUTPUT
otp_lc_data_o.state[12:7]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[13]	No	No		No		OUTPUT
otp_lc_data_o.state[14]	Yes	Yes	*T1,*T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[16:15]	No	No		No		OUTPUT
otp_lc_data_o.state[18:17]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[20:19]	No	No		No		OUTPUT
otp_lc_data_o.state[21]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[22]	No	No		No		OUTPUT
otp_lc_data_o.state[34:23]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[35]	No	No		No		OUTPUT
otp_lc_data_o.state[42:36]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[43]	No	No		No		OUTPUT
otp_lc_data_o.state[47:44]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[48]	No	No		No		OUTPUT
otp_lc_data_o.state[52:49]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[53]	No	No		No		OUTPUT
otp_lc_data_o.state[65:54]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[66]	No	No		No		OUTPUT
otp_lc_data_o.state[68:67]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[69]	No	No		No		OUTPUT
otp_lc_data_o.state[73:70]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[74]	No	No		No		OUTPUT
otp_lc_data_o.state[83:75]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[84]	No	No		No		OUTPUT
otp_lc_data_o.state[87:85]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[88]	No	No		No		OUTPUT
otp_lc_data_o.state[103:89]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[104]	No	No		No		OUTPUT
otp_lc_data_o.state[110:105]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[111]	No	No		No		OUTPUT
otp_lc_data_o.state[123:112]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[124]	No	No		No		OUTPUT
otp_lc_data_o.state[126:125]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[127]	No	No		No		OUTPUT
otp_lc_data_o.state[131:128]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[133:132]	No	No		No		OUTPUT
otp_lc_data_o.state[134]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[135]	No	No		No		OUTPUT
otp_lc_data_o.state[141:136]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[142]	No	No		No		OUTPUT
otp_lc_data_o.state[146:143]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[147]	No	No		No		OUTPUT
otp_lc_data_o.state[151:148]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[153:152]	No	No		No		OUTPUT
otp_lc_data_o.state[156:154]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[157]	No	No		No		OUTPUT
otp_lc_data_o.state[163:158]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[164]	No	No		No		OUTPUT
otp_lc_data_o.state[165]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[166]	No	No		No		OUTPUT
otp_lc_data_o.state[177:167]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[178]	No	No		No		OUTPUT
otp_lc_data_o.state[183:179]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[184]	No	No		No		OUTPUT
otp_lc_data_o.state[186:185]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[188:187]	No	No		No		OUTPUT
otp_lc_data_o.state[199:189]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[200]	No	No		No		OUTPUT
otp_lc_data_o.state[206:201]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[207]	No	No		No		OUTPUT
otp_lc_data_o.state[214:208]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[215]	No	No		No		OUTPUT
otp_lc_data_o.state[219:216]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[220]	No	No		No		OUTPUT
otp_lc_data_o.state[226:221]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[227]	No	No		No		OUTPUT
otp_lc_data_o.state[230:228]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[231]	No	No		No		OUTPUT
otp_lc_data_o.state[234:232]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[235]	No	No		No		OUTPUT
otp_lc_data_o.state[236]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[237]	No	No		No		OUTPUT
otp_lc_data_o.state[241:238]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[242]	No	No		No		OUTPUT
otp_lc_data_o.state[243]	Yes	Yes	*T1,*T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[244]	No	No		No		OUTPUT
otp_lc_data_o.state[246:245]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[247]	No	No		No		OUTPUT
otp_lc_data_o.state[250:248]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[251]	No	No		No		OUTPUT
otp_lc_data_o.state[256:252]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[257]	No	No		No		OUTPUT
otp_lc_data_o.state[277:258]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[278]	No	No		No		OUTPUT
otp_lc_data_o.state[294:279]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[295]	No	No		No		OUTPUT
otp_lc_data_o.state[301:296]	Yes	Yes	T1,*T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[302]	No	No		No		OUTPUT
otp_lc_data_o.state[316:303]	Yes	Yes	T1,*T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[317]	No	No		No		OUTPUT
otp_lc_data_o.state[319:318]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.error	Yes	Yes	T9,T10,T12	Yes	T9,T10,T12	OUTPUT
otp_lc_data_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_keymgr_key_o.owner_seed_valid	No	No		No		OUTPUT
otp_keymgr_key_o.owner_seed[255:0]	No	No		No		OUTPUT
otp_keymgr_key_o.creator_seed_valid	No	No		No		OUTPUT
otp_keymgr_key_o.creator_seed[255:0]	No	No		No		OUTPUT
otp_keymgr_key_o.creator_root_key_share1_valid	Yes	Yes	T1,T4,T23	Yes	T1,T2,T3	OUTPUT
otp_keymgr_key_o.creator_root_key_share1[255:0]	Yes	Yes	T1,T4,T10	Yes	T1,T9,T4	OUTPUT
otp_keymgr_key_o.creator_root_key_share0_valid	Yes	Yes	T1,T4,T23	Yes	T1,T2,T3	OUTPUT
otp_keymgr_key_o.creator_root_key_share0[255:0]	Yes	Yes	T182,T97,T98	Yes	T97,T102,T142	OUTPUT
flash_otp_key_i.addr_req	Yes	Yes	T1,T3,T9	Yes	T1,T3,T9	INPUT
flash_otp_key_i.data_req	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
flash_otp_key_o.seed_valid	Yes	Yes	T1,T5,T22	Yes	T1,T5,T22	OUTPUT
flash_otp_key_o.rand_key[127:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
flash_otp_key_o.key[127:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
flash_otp_key_o.addr_ack	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
flash_otp_key_o.data_ack	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
sram_otp_key_i[0].req	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
sram_otp_key_i[1].req	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
sram_otp_key_i[2].req	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
sram_otp_key_i[3].req	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
sram_otp_key_o[0].seed_valid	Yes	Yes	T1,T5,T22	Yes	T1,T5,T22	OUTPUT
sram_otp_key_o[0].nonce[127:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
sram_otp_key_o[0].key[127:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
sram_otp_key_o[0].ack	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
sram_otp_key_o[1].seed_valid	Yes	Yes	T1,T5,T22	Yes	T1,T5,T22	OUTPUT
sram_otp_key_o[1].nonce[127:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
sram_otp_key_o[1].key[127:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
sram_otp_key_o[1].ack	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
sram_otp_key_o[2].seed_valid	Yes	Yes	T1,T5,T22	Yes	T1,T5,T22	OUTPUT
sram_otp_key_o[2].nonce[127:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
sram_otp_key_o[2].key[127:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
sram_otp_key_o[2].ack	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
sram_otp_key_o[3].seed_valid	Yes	Yes	T1,T5,T22	Yes	T1,T5,T22	OUTPUT
sram_otp_key_o[3].nonce[127:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
sram_otp_key_o[3].key[127:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
sram_otp_key_o[3].ack	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otbn_otp_key_i.req	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
otbn_otp_key_o.seed_valid	Yes	Yes	T1,T5,T22	Yes	T1,T5,T22	OUTPUT
otbn_otp_key_o.nonce[63:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otbn_otp_key_o.key[127:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otbn_otp_key_o.ack	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_broadcast_o.hw_cfg0_data.device_id[255:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_broadcast_o.hw_cfg0_data.manuf_state[255:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_broadcast_o.hw_cfg0_data.hw_cfg0_digest[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_broadcast_o.hw_cfg1_data.en_sram_ifetch[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_broadcast_o.hw_cfg1_data.en_csrng_sw_app_read[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_broadcast_o.hw_cfg1_data.unallocated[47:0]	Yes	Yes	T5,T40,T93	Yes	T5,T40,T93	OUTPUT
otp_broadcast_o.hw_cfg1_data.hw_cfg1_digest[63:0]	Yes	Yes	T1,T3,T22	Yes	T1,T2,T3	OUTPUT
otp_broadcast_o.valid[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_ext_voltage_h_io	No	No		No		INOUT
scan_en_i	Yes	Yes	T1,T9,T4	Yes	T1,T4,T23	INPUT
scan_rst_ni	Yes	Yes	T1,T2,T9	Yes	T1,T3,T4	INPUT
scanmode_i[3:0]	Yes	Yes	T1,T4,T14	Yes	T1,T3,T9	INPUT
cio_test_o[7:0]	No	No		No		OUTPUT
cio_test_en_o[7:0]	Yes	Yes	T5,T103,T6	Yes	T11,T5,T127	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : otp_ctrl

	Line No.	Total	Covered	Percent
Branches		29	27	93.10
TERNARY	377	2	1	50.00
TERNARY	1434	2	2	100.00
TERNARY	1436	2	2	100.00
TERNARY	1438	2	2	100.00
IF	282	3	2	66.67
IF	303	2	2	100.00
IF	329	2	2	100.00
IF	336	2	2	100.00
IF	402	2	2	100.00
IF	443	2	2	100.00
IF	464	2	2	100.00
IF	467	2	2	100.00
IF	494	2	2	100.00
IF	986	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	377	((reg2hw.direct_access_regwen.qe && (!reg2hw.direct_access_regwen.q))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1434	((part_digest[Secret0Idx] != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1436	((part_digest[Secret2Idx] != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1438	((part_digest[Secret2Idx] != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	282	if (tlul_req)
-2-:	283	if ((tlul_part_sel_oh != '0))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Not Covered
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	303	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	329	if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_creator_seed_sw_rw_en))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	336	if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_owner_seed_sw_rw_en))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	402	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	443	if (otp_ctrl_part_pkg::PartInfo[k].integrity)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((fatal_macro_error_q || fatal_check_error_q))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	467	if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_escalate_en[k]))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	494	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	986	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : otp_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	71	71	100.00	69	97.18
Cover properties	0	0		0
Cover sequences	0	0		0
Total	71	71	100.00	69	97.18

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnown_A	1584582250	1583735421	0	0
CoreTlOutKnown_A	1584582250	1583735421	0	0
CreatorRootKeyShare0Size_A	1127	1127	0	0
CreatorRootKeyShare1Size_A	1127	1127	0	0
ErrorCodeWidth_A	1127	1127	0	0
FlashAddrKeySeedSize_A	1127	1127	0	0
FlashDataKeySeedSize_A	1127	1127	0	0
FlashOtpKeyRspKnown_A	1584582250	1583735421	0	0
FpvSecCmCntCnstyCheck_A	1584582250	50	0	0
FpvSecCmCntDaiCheck_A	1584582250	50	0	0
FpvSecCmCntIntegCheck_A	1584582250	50	0	0
FpvSecCmCntKdiEntropyCheck_A	1584582250	50	0	0
FpvSecCmCntKdiSeedCheck_A	1584582250	50	0	0
FpvSecCmCntLciCheck_A	1584582250	50	0	0
FpvSecCmCntScrmblCheck_A	1584582250	50	0	0
FpvSecCmCtrlDaiFsmCheck_A	1584582250	50	0	0
FpvSecCmCtrlKdiFsmCheck_A	1584582250	50	0	0
FpvSecCmCtrlLciFsmCheck_A	1584582250	50	0	0
FpvSecCmCtrlLfsrTimerFsmCheck_A	1584582250	50	0	0
FpvSecCmCtrlScrambleFsmCheck_A	1584582250	50	0	0
FpvSecCmDoubleLfsrCheck_A	1584582250	50	0	0
FpvSecCmRegWeOnehotCheck_A	1584582250	50	0	0
FpvSecCmTlLcGateFsm_A	1584582250	50	0	0
IntrOtpErrorKnown_A	1584582250	1583735421	0	0
IntrOtpOperationDoneKnown_A	1584582250	1583735421	0	0
LcOtpProgramRspKnown_A	1584582250	1583735421	0	0
LcSeedHwRdEnStable0_A	1584582250	2195	0	0
LcSeedHwRdEnStable1_A	1584582250	2195	0	0
LcSeedHwRdEnStable2_A	1584582250	0	0	0
LcSeedHwRdEnStable3_A	1584582250	0	0	0
LcStateSize_A	1127	1127	0	0
LcTransitionCntSize_A	1127	1127	0	0
OtpAstPwrSeqKnown_A	1584582250	1583735421	0	0
OtpBroadcastKnown_A	1584582250	1583735421	0	0
OtpErrorCode0_A	1127	1127	0	0
OtpErrorCode1_A	1127	1127	0	0
OtpErrorCode2_A	1127	1127	0	0
OtpErrorCode3_A	1127	1127	0	0
OtpErrorCode4_A	1127	1127	0	0
OtpIfWidth_A	1127	1127	0	0
OtpKeymgrKeyKnown_A	1584582250	1583735421	0	0
OtpLcDataKnown_A	1584582250	1583735421	0	0
OtpOtgnKeyKnown_A	1584582250	1583735421	0	0
OtpRespFifoUnderflow_A	1584582250	1436500	0	0
OtpSramKeyKnown_A	1584582250	1583735421	0	0
PartSelMustBeOnehot_A	1584582250	1583735421	0	0
PrimTlOutKnown_A	1584582250	1583735421	0	0
PwrOtpInitRspKnown_A	1584582250	1583735421	0	0
RmaTokenSize_A	1127	1127	0	0
SramDataKeySeedSize_A	1127	1127	0	0
TestExitTokenSize_A	1127	1127	0	0
TestUnlockTokenSize_A	1127	1127	0	0
gen_partitions[0].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	1584582250	50	0	0
gen_partitions[10].gen_lifecycle.FpvSecCmCntPartLcCheck_A	1584582250	50	0	0
gen_partitions[10].gen_lifecycle.FpvSecCmCtrlPartLcFsmCheck_A	1584582250	50	0	0
gen_partitions[1].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	1584582250	50	0	0
gen_partitions[2].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	1584582250	50	0	0
gen_partitions[3].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	1584582250	50	0	0
gen_partitions[4].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	1584582250	50	0	0
gen_partitions[5].gen_buffered.FpvSecCmCntPartBufCheck_A	1584582250	50	0	0
gen_partitions[5].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	1584582250	50	0	0
gen_partitions[6].gen_buffered.FpvSecCmCntPartBufCheck_A	1584582250	50	0	0
gen_partitions[6].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	1584582250	50	0	0
gen_partitions[7].gen_buffered.FpvSecCmCntPartBufCheck_A	1584582250	50	0	0
gen_partitions[7].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	1584582250	50	0	0
gen_partitions[8].gen_buffered.FpvSecCmCntPartBufCheck_A	1584582250	50	0	0
gen_partitions[8].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	1584582250	50	0	0
gen_partitions[9].gen_buffered.FpvSecCmCntPartBufCheck_A	1584582250	50	0	0
gen_partitions[9].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	1584582250	50	0	0
gen_reg_we_assert_generic.FpvSecCmPrimFsmCheck_A	1584582250	50	0	0
gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A	1584582250	50	0	0

AlertTxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

CoreTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

CreatorRootKeyShare0Size_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127	1127	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

CreatorRootKeyShare1Size_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127	1127	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

ErrorCodeWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127	1127	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

FlashAddrKeySeedSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127	1127	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

FlashDataKeySeedSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127	1127	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

FlashOtpKeyRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

FpvSecCmCntCnstyCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

FpvSecCmCntDaiCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

FpvSecCmCntIntegCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

FpvSecCmCntKdiEntropyCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

FpvSecCmCntKdiSeedCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

FpvSecCmCntLciCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

FpvSecCmCntScrmblCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

FpvSecCmCtrlDaiFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

FpvSecCmCtrlKdiFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

FpvSecCmCtrlLciFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

FpvSecCmCtrlLfsrTimerFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

FpvSecCmCtrlScrambleFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

FpvSecCmDoubleLfsrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

FpvSecCmTlLcGateFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

IntrOtpErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

IntrOtpOperationDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

LcOtpProgramRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

LcSeedHwRdEnStable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	2195	0	0
T1	187260	12	0	0
T2	11915	1	0	0
T3	13072	1	0	0
T4	44826	3	0	0
T9	83429	0	0	0
T10	11172	0	0	0
T11	4848	0	0	0
T12	15054	0	0	0
T13	14393	1	0	0
T14	12081	0	0	0
T22	0	9	0	0
T23	0	3	0	0
T40	0	10	0	0
T93	0	4	0	0
T104	0	1	0	0

LcSeedHwRdEnStable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	2195	0	0
T1	187260	12	0	0
T2	11915	1	0	0
T3	13072	1	0	0
T4	44826	3	0	0
T9	83429	0	0	0
T10	11172	0	0	0
T11	4848	0	0	0
T12	15054	0	0	0
T13	14393	1	0	0
T14	12081	0	0	0
T22	0	9	0	0
T23	0	3	0	0
T40	0	10	0	0
T93	0	4	0	0
T104	0	1	0	0

LcSeedHwRdEnStable2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	0	0	0

LcSeedHwRdEnStable3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	0	0	0

LcStateSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127	1127	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

LcTransitionCntSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127	1127	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

OtpAstPwrSeqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

OtpBroadcastKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

OtpErrorCode0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127	1127	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

OtpErrorCode1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127	1127	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

OtpErrorCode2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127	1127	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

OtpErrorCode3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127	1127	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

OtpErrorCode4_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127	1127	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

OtpIfWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127	1127	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

OtpKeymgrKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

OtpLcDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

OtpOtgnKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

OtpRespFifoUnderflow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1436500	0	0
T1	187260	6066	0	0
T2	11915	250	0	0
T3	13072	242	0	0
T4	44826	862	0	0
T9	83429	136	0	0
T10	11172	200	0	0
T11	4848	55	0	0
T12	15054	211	0	0
T13	14393	169	0	0
T14	12081	173	0	0

OtpSramKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

PartSelMustBeOnehot_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

PrimTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

PwrOtpInitRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

RmaTokenSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127	1127	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

SramDataKeySeedSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127	1127	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

TestExitTokenSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127	1127	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

TestUnlockTokenSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127	1127	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

gen_partitions[0].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

gen_partitions[10].gen_lifecycle.FpvSecCmCntPartLcCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

gen_partitions[10].gen_lifecycle.FpvSecCmCtrlPartLcFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

gen_partitions[1].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

gen_partitions[2].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

gen_partitions[3].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

gen_partitions[4].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

gen_partitions[5].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

gen_partitions[5].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

gen_partitions[6].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

gen_partitions[6].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

gen_partitions[7].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

gen_partitions[7].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

gen_partitions[8].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

gen_partitions[8].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

gen_partitions[9].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

gen_partitions[9].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

gen_reg_we_assert_generic.FpvSecCmPrimFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		156	150	96.15
CONT_ASSIGN	246	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
ALWAYS	279	14	13	92.86
ALWAYS	303	3	3	100.00
ALWAYS	319	11	10	90.91
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	381	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	389	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	399	1	1	100.00
ALWAYS	402	5	5	100.00
ALWAYS	429	19	19	100.00
CONT_ASSIGN	483	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
ALWAYS	494	9	9	100.00
ALWAYS	516	10	10	100.00
CONT_ASSIGN	580	1	1	100.00
CONT_ASSIGN	588	1	1	100.00
CONT_ASSIGN	635	1	1	100.00
CONT_ASSIGN	637	1	1	100.00
CONT_ASSIGN	760	1	1	100.00
CONT_ASSIGN	761	1	1	100.00
CONT_ASSIGN	762	1	1	100.00
CONT_ASSIGN	792	1	1	100.00
CONT_ASSIGN	794	1	1	100.00
ALWAYS	871	2	2	100.00
ALWAYS	929	2	2	100.00
ALWAYS	956	4	4	100.00
CONT_ASSIGN	983	1	1	100.00
ALWAYS	986	3	3	100.00
CONT_ASSIGN	1038	1	1	100.00
CONT_ASSIGN	1040	1	1	100.00
CONT_ASSIGN	1074	1	0	0.00
CONT_ASSIGN	1125	1	0	0.00
CONT_ASSIGN	1180	1	1	100.00
CONT_ASSIGN	1180	1	1	100.00
CONT_ASSIGN	1180	1	1	100.00
CONT_ASSIGN	1180	1	1	100.00
CONT_ASSIGN	1180	1	1	100.00
CONT_ASSIGN	1235	1	1	100.00
CONT_ASSIGN	1235	1	0	0.00
CONT_ASSIGN	1235	1	1	100.00
CONT_ASSIGN	1235	1	1	100.00
CONT_ASSIGN	1235	1	1	100.00
CONT_ASSIGN	1295	1	1	100.00
CONT_ASSIGN	1307	1	0	0.00
CONT_ASSIGN	1331	1	1	100.00
ALWAYS	1343	2	2	100.00
CONT_ASSIGN	1357	1	1	100.00
ALWAYS	1385	9	9	100.00
CONT_ASSIGN	1416	1	1	100.00
CONT_ASSIGN	1417	1	1	100.00
CONT_ASSIGN	1419	1	1	100.00
CONT_ASSIGN	1421	1	1	100.00
CONT_ASSIGN	1425	1	1	100.00
CONT_ASSIGN	1427	1	1	100.00
CONT_ASSIGN	1429	1	1	100.00
CONT_ASSIGN	1434	1	1	100.00
CONT_ASSIGN	1436	1	1	100.00
CONT_ASSIGN	1438	1	1	100.00
CONT_ASSIGN	1470	1	1	100.00
CONT_ASSIGN	1472	1	1	100.00
CONT_ASSIGN	1476	1	1	100.00
CONT_ASSIGN	1480	1	1	100.00
CONT_ASSIGN	1484	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
246	1	1
248	10	10
279	1	1
280	1	1
281	1	1
282	1	1
283	1	1
284	1	1
287	0	1
			MISSING_ELSE
292	1	1
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
303	1	1
304	1	1
306	1	1
319	1	1
324	1	1
325	1	1
329	1	1
330	1	1
331	1	1
332	1	1
			MISSING_ELSE
			MISSING_ELSE
336	1	1
337	1	1
338	1	1
339	0	1
			MISSING_ELSE
			MISSING_ELSE
377	1	1
381	1	1
385	1	1
389	1	1
390	1	1
398	1	1
399	1	1
402	1	1
403	1	1
405	1	1
407	1	1
408	1	1
429	1	1
430	1	1
431	1	1
433	1	1
435	1	1
438	1	1
440	1	1
443	1	1
444	1	1
			MISSING_ELSE
448	1	1
450	1	1
454	1	1
457	1	1
459	1	1
464	1	1
465	1	1
			MISSING_ELSE
467	1	1
468	1	1
			MISSING_ELSE
473	1	1
483	1	1
491	1	1
494	1	1
495	1	1
496	1	1
497	1	1
498	1	1
500	1	1
501	1	1
502	1	1
503	1	1
516	1	1
518	1	1
520	1	1
522	1	1
524	1	1
533	1	1
535	1	1
536	1	1
537	1	1
538	1	1
580	1	1
588	1	1
635	1	1
637	1	1
760	1	1
761	1	1
762	1	1
792	1	1
794	1	1
871	1	1
872	1	1
929	1	1
930	1	1
956	1	1
957	1	1
958	1	1
959	1	1
983	1	1
986	1	1
987	1	1
989	1	1
1038	1	1
1040	1	1
1074	0	1
1125	0	1
1180	5	5
1235	4	5
1295	1	1
1307	0	1
1331	1	1
1343	1	1
1344	1	1
1357	1	1
1385	1	1
1386	1	1
1387	1	1
1388	1	1
1390	1	1
1391	1	1
1392	1	1
1393	1	1
1394	1	1
1416	1	1
1417	1	1
1419	1	1
1421	1	1
1425	1	1
1427	1	1
1429	1	1
1434	1	1
1436	1	1
1438	1	1
1470	1	1
1472	1	1
1476	1	1
1480	1	1
1484	1	1

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	115	100	86.96
Logical	115	100	86.96
Non-Logical	0	0
Event	0	0

 LINE       248
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b00001000000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[1].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       248
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b00111101000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[2].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       248
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b10001111000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[3].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       248
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11001010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[4].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T15
1	1	Covered	T1,T2,T3

 LINE       248
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11001111000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[5].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T15
1	1	Covered	T6,T7,T15

 LINE       248
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011000000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[6].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T15
1	1	Covered	T6,T7,T15

 LINE       248
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[7].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T15
1	1	Covered	T6,T7,T15

 LINE       248
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011111000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[8].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T15
1	1	Covered	T6,T7,T15

 LINE       248
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11101010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[9].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T15
1	1	Covered	T6,T7,T15

 LINE       248
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11110101000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[10].PartEnd))
             -------------------1------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T6,T7,T15

 LINE       283
 EXPRESSION (tlul_part_sel_oh != '0)
            ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       292
 EXPRESSION (((|part_tlul_gnt)) | tlul_oob_err_q)
             ---------1--------   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       293
 EXPRESSION (((|part_tlul_rvalid)) | tlul_oob_err_q)
             ----------1----------   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       377
 EXPRESSION ((reg2hw.direct_access_regwen.qe && ((!reg2hw.direct_access_regwen.q))) ? 1'b0 : direct_access_regwen_q)
             -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       377
 SUB-EXPRESSION (reg2hw.direct_access_regwen.qe && ((!reg2hw.direct_access_regwen.q)))
                 ---------------1--------------    -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       381
 EXPRESSION (reg2hw.direct_access_cmd.digest.qe | reg2hw.direct_access_cmd.wr.qe | reg2hw.direct_access_cmd.rd.qe)
             -----------------1----------------   ---------------2--------------   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       398
 EXPRESSION (lci_prog_idle & dai_prog_idle)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       431
 EXPRESSION (fatal_bus_integ_error_q | ((|intg_error)))
             -----------1-----------   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T28,T29,T30
1	0	Not Covered

 LINE       440
 EXPRESSION (part_error[k] == MacroError)
            --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       444
 EXPRESSION (part_error[k] == MacroEccUncorrError)
            -------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T12,T14

 LINE       464
 EXPRESSION (fatal_macro_error_q || fatal_check_error_q)
             ---------1---------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T13,T44
1	0	Covered	T10,T12,T14

 LINE       473
 EXPRESSION (chk_timeout | lfsr_fsm_err | scrmbl_fsm_err | ((|part_fsm_err)))
             -----1-----   ------2-----   -------3------   --------4--------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T10,T12,T14
0	0	1	0	Covered	T28,T29,T30
0	1	0	0	Covered	T28,T29,T30
1	0	0	0	Covered	T23,T65,T6

 LINE       522
 EXPRESSION (direct_access_regwen_q & dai_idle)
             -----------1----------   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       588
 SUB-EXPRESSION (reg2hw.alert_test.recov_prim_otp_alert.q & reg2hw.alert_test.recov_prim_otp_alert.qe)
                 --------------------1-------------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T127,T183
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T127,T183

 LINE       588
 SUB-EXPRESSION (reg2hw.alert_test.fatal_prim_otp_alert.q & reg2hw.alert_test.fatal_prim_otp_alert.qe)
                 --------------------1-------------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T127,T183
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T127,T183

 LINE       588
 SUB-EXPRESSION (reg2hw.alert_test.fatal_bus_integ_error.q & reg2hw.alert_test.fatal_bus_integ_error.qe)
                 --------------------1--------------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T127,T183
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T127,T183

 LINE       588
 SUB-EXPRESSION (reg2hw.alert_test.fatal_check_error.q & reg2hw.alert_test.fatal_check_error.qe)
                 ------------------1------------------   -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T127,T183
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T127,T183

 LINE       588
 SUB-EXPRESSION (reg2hw.alert_test.fatal_macro_error.q & reg2hw.alert_test.fatal_macro_error.qe)
                 ------------------1------------------   -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T127,T183
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T127,T183

 LINE       635
 EXPRESSION (reg2hw.check_trigger.integrity.q & reg2hw.check_trigger.integrity.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T9

 LINE       637
 EXPRESSION (reg2hw.check_trigger.consistency.q & reg2hw.check_trigger.consistency.qe)
             -----------------1----------------   -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       760
 EXPRESSION (otp_prim_ready & otp_rsp_fifo_ready)
             -------1------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       761
 EXPRESSION (otp_arb_valid & otp_rsp_fifo_ready)
             ------1------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       762
 EXPRESSION (otp_prim_ready & otp_prim_valid)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       872
 EXPRESSION (otp_rvalid & otp_fifo_valid)
             -----1----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       1416
 EXPRESSION (part_digest[Secret1Idx] != '0)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1434
 EXPRESSION ((part_digest[Secret0Idx] != '0) ? On : Off)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       1434
 SUB-EXPRESSION (part_digest[Secret0Idx] != '0)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       1436
 EXPRESSION ((part_digest[Secret2Idx] != '0) ? On : Off)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1436
 SUB-EXPRESSION (part_digest[Secret2Idx] != '0)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1438
 EXPRESSION ((part_digest[Secret2Idx] != '0) ? On : Off)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1438
 SUB-EXPRESSION (part_digest[Secret2Idx] != '0)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	151	140	92.72
Total Bits	10992	9662	87.90
Total Bits 0->1	5496	4831	87.90
Total Bits 1->0	5496	4831	87.90

Ports	151	140	92.72
Port Bits	10992	9662	87.90
Port Bits 0->1	5496	4831	87.90
Port Bits 1->0	5496	4831	87.90

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_o.edn_req	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
edn_i.edn_fips	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
edn_i.edn_ack	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
core_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T12,T44	Yes	T4,T12,T44	INPUT
core_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
core_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
core_tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_error	Yes	Yes	T1,T3,T9	Yes	T1,T3,T9	OUTPUT
core_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
prim_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
prim_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
prim_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
prim_tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T12,T5	Yes	T1,T5,T44	INPUT
prim_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
prim_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
prim_tl_i.a_mask[3:0]	Yes	Yes	T1,T12,T5	Yes	T1,T11,T5	INPUT
prim_tl_i.a_address[31:0]	Yes	Yes	T1,T12,T5	Yes	T1,T12,T5	INPUT
prim_tl_i.a_source[7:0]	Yes	Yes	T1,T3,T9	Yes	T1,T3,T9	INPUT
prim_tl_i.a_size[1:0]	Yes	Yes	T1,T12,T5	Yes	T1,T12,T5	INPUT
prim_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
prim_tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
prim_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
prim_tl_o.a_ready	Yes	Yes	T1,T11,T5	Yes	T1,T11,T5	OUTPUT
prim_tl_o.d_error	Yes	Yes	T11,T5,T127	Yes	T5,T103,T6	OUTPUT
prim_tl_o.d_user.data_intg[0]	Excluded	Excluded	*T5,*T103,*T6	Excluded	T5,T103,T6	OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
prim_tl_o.d_user.data_intg[1]	Yes	Yes	*T5,*T103,*T6	Yes	T5,T103,T6	OUTPUT
prim_tl_o.d_user.data_intg[2]	Excluded	Excluded	*T5,*T103,*T6	Excluded	T5,T103,T6	OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
prim_tl_o.d_user.data_intg[3]	Yes	Yes	*T5,*T103,*T6	Yes	T5,T103,T6	OUTPUT
prim_tl_o.d_user.data_intg[4]	Excluded	Excluded	*T5,*T103,*T6	Excluded	T5,T103,T6	OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
prim_tl_o.d_user.data_intg[5]	Yes	Yes	*T5,*T6,*T7	Yes	T5,T6,T7	OUTPUT
prim_tl_o.d_user.data_intg[6]	Excluded	Excluded	T5,T103,T6	Excluded	T5,T103,T6	OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
prim_tl_o.d_user.rsp_intg[5:0]	Excluded	Excluded	*T1,*T2,*T3	Excluded	T1,T2,T3	OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
prim_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_data[31:0]	Yes	Yes	T11,T5,T127	Yes	T5,T103,T6	OUTPUT
prim_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_source[7:0]	Yes	Yes	T2,T3,T9	Yes	T2,T3,T9	OUTPUT
prim_tl_o.d_size[1:0]	Yes	Yes	T6,T7,T15	Yes	T6,T7,T15	OUTPUT
prim_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
prim_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
intr_otp_operation_done_o	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
intr_otp_error_o	Yes	Yes	T1,T4,T14	Yes	T1,T4,T14	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T9,T10,T11	Yes	T9,T10,T11	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T11,T127,T183	Yes	T11,T127,T183	INPUT
alert_rx_i[2].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[3].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T11,T127,T183	Yes	T11,T127,T183	INPUT
alert_rx_i[3].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[3].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[4].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[4].ack_p	Yes	Yes	T11,T127,T183	Yes	T11,T127,T183	INPUT
alert_rx_i[4].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[4].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T9,T10,T11	Yes	T9,T10,T11	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T11,T127,T183	Yes	T11,T127,T183	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T11,T127,T183	Yes	T11,T127,T183	OUTPUT
alert_tx_o[4].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[4].alert_p	Yes	Yes	T11,T127,T183	Yes	T11,T127,T183	OUTPUT
obs_ctrl_i.obmen[3:0]	No	No		No		INPUT
obs_ctrl_i.obmsl[3:0]	No	No		No		INPUT
obs_ctrl_i.obgsl[3:0]	No	No		No		INPUT
otp_obs_o[7:0]	Unreachable	Unreachable		Unreachable		OUTPUT
otp_ast_pwr_seq_o.pwr_seq[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
otp_ast_pwr_seq_h_i.pwr_seq_h[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T13,T23	INPUT
pwr_otp_i.otp_init	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwr_otp_o.otp_idle	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwr_otp_o.otp_done	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
lc_otp_vendor_test_i.ctrl[31:0]	No	No		No		INPUT
lc_otp_vendor_test_o.status[31:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
lc_otp_program_i.count[383:0]	Yes	Yes	T6,T98,T15	Yes	T15,T239,T130	INPUT
lc_otp_program_i.state[319:0]	Yes	Yes	T238,T130,T240	Yes	T239,T130,T240	INPUT
lc_otp_program_i.req	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
lc_otp_program_o.ack	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
lc_otp_program_o.err	Yes	Yes	T6,T15,T238	Yes	T6,T15,T238	OUTPUT
lc_creator_seed_sw_rw_en_i[3:0]	Yes	Yes	T1,T9,T4	Yes	T1,T9,T4	INPUT
lc_owner_seed_sw_rw_en_i[3:0]	Yes	Yes	T1,T3,T9	Yes	T1,T3,T9	INPUT
lc_seed_hw_rd_en_i[3:0]	Yes	Yes	T1,T4,T10	Yes	T1,T3,T9	INPUT
lc_dft_en_i[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T11,T5	INPUT
lc_escalate_en_i[3:0]	Yes	Yes	T9,T13,T66	Yes	T9,T13,T66	INPUT
lc_check_byp_en_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
otp_lc_data_o.rma_token[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.rma_token_valid[3:0]	Yes	Yes	T1,T4,T23	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.test_exit_token[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.test_unlock_token[127:0]	Yes	Yes	T1,T40,T94	Yes	T1,T3,T40	OUTPUT
otp_lc_data_o.test_tokens_valid[3:0]	Yes	Yes	T1,T4,T5	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.secrets_valid[3:0]	Yes	Yes	T1,T4,T23	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[14:0]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[16:15]	No	No		No		OUTPUT
otp_lc_data_o.count[28:17]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[29]	No	No		No		OUTPUT
otp_lc_data_o.count[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[32:31]	No	No		No		OUTPUT
otp_lc_data_o.count[54:33]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[55]	No	No		No		OUTPUT
otp_lc_data_o.count[61:56]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[62]	No	No		No		OUTPUT
otp_lc_data_o.count[64:63]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[65]	No	No		No		OUTPUT
otp_lc_data_o.count[78:66]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[79]	No	No		No		OUTPUT
otp_lc_data_o.count[85:80]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[86]	No	No		No		OUTPUT
otp_lc_data_o.count[88:87]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[89]	No	No		No		OUTPUT
otp_lc_data_o.count[100:90]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[102:101]	No	No		No		OUTPUT
otp_lc_data_o.count[104:103]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[105]	No	No		No		OUTPUT
otp_lc_data_o.count[115:106]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[116]	No	No		No		OUTPUT
otp_lc_data_o.count[134:117]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[135]	No	No		No		OUTPUT
otp_lc_data_o.count[137:136]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[138]	No	No		No		OUTPUT
otp_lc_data_o.count[142:139]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[143]	No	No		No		OUTPUT
otp_lc_data_o.count[150:144]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[151]	No	No		No		OUTPUT
otp_lc_data_o.count[158:152]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[159]	No	No		No		OUTPUT
otp_lc_data_o.count[165:160]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[166]	No	No		No		OUTPUT
otp_lc_data_o.count[171:167]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[172]	No	No		No		OUTPUT
otp_lc_data_o.count[174:173]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[175]	No	No		No		OUTPUT
otp_lc_data_o.count[176]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[177]	No	No		No		OUTPUT
otp_lc_data_o.count[185:178]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[187:186]	No	No		No		OUTPUT
otp_lc_data_o.count[188]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[189]	No	No		No		OUTPUT
otp_lc_data_o.count[194:190]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[195]	No	No		No		OUTPUT
otp_lc_data_o.count[202:196]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[203]	No	No		No		OUTPUT
otp_lc_data_o.count[207:204]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[208]	No	No		No		OUTPUT
otp_lc_data_o.count[215:209]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[216]	No	No		No		OUTPUT
otp_lc_data_o.count[217]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[219:218]	No	No		No		OUTPUT
otp_lc_data_o.count[225:220]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[226]	No	No		No		OUTPUT
otp_lc_data_o.count[228:227]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[229]	No	No		No		OUTPUT
otp_lc_data_o.count[232:230]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[233]	No	No		No		OUTPUT
otp_lc_data_o.count[237:234]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[238]	No	No		No		OUTPUT
otp_lc_data_o.count[240:239]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[241]	No	No		No		OUTPUT
otp_lc_data_o.count[254:242]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[255]	No	No		No		OUTPUT
otp_lc_data_o.count[257:256]	Yes	Yes	T1,T4,T23	Yes	T1,T4,T23	OUTPUT
otp_lc_data_o.count[258]	No	No		No		OUTPUT
otp_lc_data_o.count[266:259]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[267]	No	No		No		OUTPUT
otp_lc_data_o.count[284:268]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[286:285]	No	No		No		OUTPUT
otp_lc_data_o.count[301:287]	Yes	Yes	T1,T4,*T23	Yes	T1,T4,T23	OUTPUT
otp_lc_data_o.count[304:302]	No	No		No		OUTPUT
otp_lc_data_o.count[324:305]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[325]	No	No		No		OUTPUT
otp_lc_data_o.count[327:326]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[328]	No	No		No		OUTPUT
otp_lc_data_o.count[330:329]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[331]	No	No		No		OUTPUT
otp_lc_data_o.count[335:332]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[336]	No	No		No		OUTPUT
otp_lc_data_o.count[343:337]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[344]	No	No		No		OUTPUT
otp_lc_data_o.count[345]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[346]	No	No		No		OUTPUT
otp_lc_data_o.count[366:347]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[367]	No	No		No		OUTPUT
otp_lc_data_o.count[371:368]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[372]	No	No		No		OUTPUT
otp_lc_data_o.count[375:373]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[376]	No	No		No		OUTPUT
otp_lc_data_o.count[383:377]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[5:0]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[6]	No	No		No		OUTPUT
otp_lc_data_o.state[12:7]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[13]	No	No		No		OUTPUT
otp_lc_data_o.state[14]	Yes	Yes	*T1,*T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[16:15]	No	No		No		OUTPUT
otp_lc_data_o.state[18:17]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[20:19]	No	No		No		OUTPUT
otp_lc_data_o.state[21]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[22]	No	No		No		OUTPUT
otp_lc_data_o.state[34:23]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[35]	No	No		No		OUTPUT
otp_lc_data_o.state[42:36]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[43]	No	No		No		OUTPUT
otp_lc_data_o.state[47:44]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[48]	No	No		No		OUTPUT
otp_lc_data_o.state[52:49]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[53]	No	No		No		OUTPUT
otp_lc_data_o.state[65:54]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[66]	No	No		No		OUTPUT
otp_lc_data_o.state[68:67]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[69]	No	No		No		OUTPUT
otp_lc_data_o.state[73:70]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[74]	No	No		No		OUTPUT
otp_lc_data_o.state[83:75]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[84]	No	No		No		OUTPUT
otp_lc_data_o.state[87:85]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[88]	No	No		No		OUTPUT
otp_lc_data_o.state[103:89]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[104]	No	No		No		OUTPUT
otp_lc_data_o.state[110:105]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[111]	No	No		No		OUTPUT
otp_lc_data_o.state[123:112]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[124]	No	No		No		OUTPUT
otp_lc_data_o.state[126:125]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[127]	No	No		No		OUTPUT
otp_lc_data_o.state[131:128]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[133:132]	No	No		No		OUTPUT
otp_lc_data_o.state[134]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[135]	No	No		No		OUTPUT
otp_lc_data_o.state[141:136]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[142]	No	No		No		OUTPUT
otp_lc_data_o.state[146:143]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[147]	No	No		No		OUTPUT
otp_lc_data_o.state[151:148]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[153:152]	No	No		No		OUTPUT
otp_lc_data_o.state[156:154]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[157]	No	No		No		OUTPUT
otp_lc_data_o.state[163:158]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[164]	No	No		No		OUTPUT
otp_lc_data_o.state[165]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[166]	No	No		No		OUTPUT
otp_lc_data_o.state[177:167]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[178]	No	No		No		OUTPUT
otp_lc_data_o.state[183:179]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[184]	No	No		No		OUTPUT
otp_lc_data_o.state[186:185]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[188:187]	No	No		No		OUTPUT
otp_lc_data_o.state[199:189]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[200]	No	No		No		OUTPUT
otp_lc_data_o.state[206:201]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[207]	No	No		No		OUTPUT
otp_lc_data_o.state[214:208]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[215]	No	No		No		OUTPUT
otp_lc_data_o.state[219:216]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[220]	No	No		No		OUTPUT
otp_lc_data_o.state[226:221]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[227]	No	No		No		OUTPUT
otp_lc_data_o.state[230:228]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[231]	No	No		No		OUTPUT
otp_lc_data_o.state[234:232]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[235]	No	No		No		OUTPUT
otp_lc_data_o.state[236]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[237]	No	No		No		OUTPUT
otp_lc_data_o.state[241:238]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[242]	No	No		No		OUTPUT
otp_lc_data_o.state[243]	Yes	Yes	*T1,*T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[244]	No	No		No		OUTPUT
otp_lc_data_o.state[246:245]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[247]	No	No		No		OUTPUT
otp_lc_data_o.state[250:248]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[251]	No	No		No		OUTPUT
otp_lc_data_o.state[256:252]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[257]	No	No		No		OUTPUT
otp_lc_data_o.state[277:258]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[278]	No	No		No		OUTPUT
otp_lc_data_o.state[294:279]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[295]	No	No		No		OUTPUT
otp_lc_data_o.state[301:296]	Yes	Yes	T1,*T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[302]	No	No		No		OUTPUT
otp_lc_data_o.state[316:303]	Yes	Yes	T1,*T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[317]	No	No		No		OUTPUT
otp_lc_data_o.state[319:318]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.error	Yes	Yes	T9,T10,T12	Yes	T9,T10,T12	OUTPUT
otp_lc_data_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_keymgr_key_o.owner_seed_valid	No	No		No		OUTPUT
otp_keymgr_key_o.owner_seed[255:0]	No	No		No		OUTPUT
otp_keymgr_key_o.creator_seed_valid	No	No		No		OUTPUT
otp_keymgr_key_o.creator_seed[255:0]	No	No		No		OUTPUT
otp_keymgr_key_o.creator_root_key_share1_valid	Yes	Yes	T1,T4,T23	Yes	T1,T2,T3	OUTPUT
otp_keymgr_key_o.creator_root_key_share1[255:0]	Yes	Yes	T1,T4,T10	Yes	T1,T9,T4	OUTPUT
otp_keymgr_key_o.creator_root_key_share0_valid	Yes	Yes	T1,T4,T23	Yes	T1,T2,T3	OUTPUT
otp_keymgr_key_o.creator_root_key_share0[255:0]	Yes	Yes	T182,T97,T98	Yes	T97,T102,T142	OUTPUT
flash_otp_key_i.addr_req	Yes	Yes	T1,T3,T9	Yes	T1,T3,T9	INPUT
flash_otp_key_i.data_req	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
flash_otp_key_o.seed_valid	Yes	Yes	T1,T5,T22	Yes	T1,T5,T22	OUTPUT
flash_otp_key_o.rand_key[127:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
flash_otp_key_o.key[127:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
flash_otp_key_o.addr_ack	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
flash_otp_key_o.data_ack	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
sram_otp_key_i[0].req	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
sram_otp_key_i[1].req	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
sram_otp_key_i[2].req	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
sram_otp_key_i[3].req	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
sram_otp_key_o[0].seed_valid	Yes	Yes	T1,T5,T22	Yes	T1,T5,T22	OUTPUT
sram_otp_key_o[0].nonce[127:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
sram_otp_key_o[0].key[127:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
sram_otp_key_o[0].ack	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
sram_otp_key_o[1].seed_valid	Yes	Yes	T1,T5,T22	Yes	T1,T5,T22	OUTPUT
sram_otp_key_o[1].nonce[127:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
sram_otp_key_o[1].key[127:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
sram_otp_key_o[1].ack	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
sram_otp_key_o[2].seed_valid	Yes	Yes	T1,T5,T22	Yes	T1,T5,T22	OUTPUT
sram_otp_key_o[2].nonce[127:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
sram_otp_key_o[2].key[127:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
sram_otp_key_o[2].ack	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
sram_otp_key_o[3].seed_valid	Yes	Yes	T1,T5,T22	Yes	T1,T5,T22	OUTPUT
sram_otp_key_o[3].nonce[127:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
sram_otp_key_o[3].key[127:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
sram_otp_key_o[3].ack	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otbn_otp_key_i.req	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
otbn_otp_key_o.seed_valid	Yes	Yes	T1,T5,T22	Yes	T1,T5,T22	OUTPUT
otbn_otp_key_o.nonce[63:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otbn_otp_key_o.key[127:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otbn_otp_key_o.ack	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_broadcast_o.hw_cfg0_data.device_id[255:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_broadcast_o.hw_cfg0_data.manuf_state[255:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_broadcast_o.hw_cfg0_data.hw_cfg0_digest[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_broadcast_o.hw_cfg1_data.en_sram_ifetch[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_broadcast_o.hw_cfg1_data.en_csrng_sw_app_read[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_broadcast_o.hw_cfg1_data.unallocated[47:0]	Yes	Yes	T5,T40,T93	Yes	T5,T40,T93	OUTPUT
otp_broadcast_o.hw_cfg1_data.hw_cfg1_digest[63:0]	Yes	Yes	T1,T3,T22	Yes	T1,T2,T3	OUTPUT
otp_broadcast_o.valid[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_ext_voltage_h_io	No	No		No		INOUT
scan_en_i	Yes	Yes	T1,T9,T4	Yes	T1,T4,T23	INPUT
scan_rst_ni	Yes	Yes	T1,T2,T9	Yes	T1,T3,T4	INPUT
scanmode_i[3:0]	Yes	Yes	T1,T4,T14	Yes	T1,T3,T9	INPUT
cio_test_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
cio_test_en_o[7:0]	Yes	Yes	T5,T103,T6	Yes	T11,T5,T127	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
Branches		29	27	93.10
TERNARY	377	2	1	50.00
TERNARY	1434	2	2	100.00
TERNARY	1436	2	2	100.00
TERNARY	1438	2	2	100.00
IF	282	3	2	66.67
IF	303	2	2	100.00
IF	329	2	2	100.00
IF	336	2	2	100.00
IF	402	2	2	100.00
IF	443	2	2	100.00
IF	464	2	2	100.00
IF	467	2	2	100.00
IF	494	2	2	100.00
IF	986	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	377	((reg2hw.direct_access_regwen.qe && (!reg2hw.direct_access_regwen.q))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1434	((part_digest[Secret0Idx] != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1436	((part_digest[Secret2Idx] != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1438	((part_digest[Secret2Idx] != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	282	if (tlul_req)
-2-:	283	if ((tlul_part_sel_oh != '0))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Not Covered
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	303	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	329	if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_creator_seed_sw_rw_en))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	336	if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_owner_seed_sw_rw_en))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	402	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	443	if (otp_ctrl_part_pkg::PartInfo[k].integrity)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((fatal_macro_error_q || fatal_check_error_q))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	467	if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_escalate_en[k]))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	494	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	986	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	71	71	100.00	69	97.18
Cover properties	0	0		0
Cover sequences	0	0		0
Total	71	71	100.00	69	97.18

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnown_A	1584582250	1583735421	0	0
CoreTlOutKnown_A	1584582250	1583735421	0	0
CreatorRootKeyShare0Size_A	1127	1127	0	0
CreatorRootKeyShare1Size_A	1127	1127	0	0
ErrorCodeWidth_A	1127	1127	0	0
FlashAddrKeySeedSize_A	1127	1127	0	0
FlashDataKeySeedSize_A	1127	1127	0	0
FlashOtpKeyRspKnown_A	1584582250	1583735421	0	0
FpvSecCmCntCnstyCheck_A	1584582250	50	0	0
FpvSecCmCntDaiCheck_A	1584582250	50	0	0
FpvSecCmCntIntegCheck_A	1584582250	50	0	0
FpvSecCmCntKdiEntropyCheck_A	1584582250	50	0	0
FpvSecCmCntKdiSeedCheck_A	1584582250	50	0	0
FpvSecCmCntLciCheck_A	1584582250	50	0	0
FpvSecCmCntScrmblCheck_A	1584582250	50	0	0
FpvSecCmCtrlDaiFsmCheck_A	1584582250	50	0	0
FpvSecCmCtrlKdiFsmCheck_A	1584582250	50	0	0
FpvSecCmCtrlLciFsmCheck_A	1584582250	50	0	0
FpvSecCmCtrlLfsrTimerFsmCheck_A	1584582250	50	0	0
FpvSecCmCtrlScrambleFsmCheck_A	1584582250	50	0	0
FpvSecCmDoubleLfsrCheck_A	1584582250	50	0	0
FpvSecCmRegWeOnehotCheck_A	1584582250	50	0	0
FpvSecCmTlLcGateFsm_A	1584582250	50	0	0
IntrOtpErrorKnown_A	1584582250	1583735421	0	0
IntrOtpOperationDoneKnown_A	1584582250	1583735421	0	0
LcOtpProgramRspKnown_A	1584582250	1583735421	0	0
LcSeedHwRdEnStable0_A	1584582250	2195	0	0
LcSeedHwRdEnStable1_A	1584582250	2195	0	0
LcSeedHwRdEnStable2_A	1584582250	0	0	0
LcSeedHwRdEnStable3_A	1584582250	0	0	0
LcStateSize_A	1127	1127	0	0
LcTransitionCntSize_A	1127	1127	0	0
OtpAstPwrSeqKnown_A	1584582250	1583735421	0	0
OtpBroadcastKnown_A	1584582250	1583735421	0	0
OtpErrorCode0_A	1127	1127	0	0
OtpErrorCode1_A	1127	1127	0	0
OtpErrorCode2_A	1127	1127	0	0
OtpErrorCode3_A	1127	1127	0	0
OtpErrorCode4_A	1127	1127	0	0
OtpIfWidth_A	1127	1127	0	0
OtpKeymgrKeyKnown_A	1584582250	1583735421	0	0
OtpLcDataKnown_A	1584582250	1583735421	0	0
OtpOtgnKeyKnown_A	1584582250	1583735421	0	0
OtpRespFifoUnderflow_A	1584582250	1436500	0	0
OtpSramKeyKnown_A	1584582250	1583735421	0	0
PartSelMustBeOnehot_A	1584582250	1583735421	0	0
PrimTlOutKnown_A	1584582250	1583735421	0	0
PwrOtpInitRspKnown_A	1584582250	1583735421	0	0
RmaTokenSize_A	1127	1127	0	0
SramDataKeySeedSize_A	1127	1127	0	0
TestExitTokenSize_A	1127	1127	0	0
TestUnlockTokenSize_A	1127	1127	0	0
gen_partitions[0].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	1584582250	50	0	0
gen_partitions[10].gen_lifecycle.FpvSecCmCntPartLcCheck_A	1584582250	50	0	0
gen_partitions[10].gen_lifecycle.FpvSecCmCtrlPartLcFsmCheck_A	1584582250	50	0	0
gen_partitions[1].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	1584582250	50	0	0
gen_partitions[2].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	1584582250	50	0	0
gen_partitions[3].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	1584582250	50	0	0
gen_partitions[4].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	1584582250	50	0	0
gen_partitions[5].gen_buffered.FpvSecCmCntPartBufCheck_A	1584582250	50	0	0
gen_partitions[5].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	1584582250	50	0	0
gen_partitions[6].gen_buffered.FpvSecCmCntPartBufCheck_A	1584582250	50	0	0
gen_partitions[6].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	1584582250	50	0	0
gen_partitions[7].gen_buffered.FpvSecCmCntPartBufCheck_A	1584582250	50	0	0
gen_partitions[7].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	1584582250	50	0	0
gen_partitions[8].gen_buffered.FpvSecCmCntPartBufCheck_A	1584582250	50	0	0
gen_partitions[8].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	1584582250	50	0	0
gen_partitions[9].gen_buffered.FpvSecCmCntPartBufCheck_A	1584582250	50	0	0
gen_partitions[9].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	1584582250	50	0	0
gen_reg_we_assert_generic.FpvSecCmPrimFsmCheck_A	1584582250	50	0	0
gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A	1584582250	50	0	0

AlertTxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

CoreTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

CreatorRootKeyShare0Size_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127	1127	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

CreatorRootKeyShare1Size_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127	1127	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

ErrorCodeWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127	1127	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

FlashAddrKeySeedSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127	1127	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

FlashDataKeySeedSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127	1127	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

FlashOtpKeyRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

FpvSecCmCntCnstyCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

FpvSecCmCntDaiCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

FpvSecCmCntIntegCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

FpvSecCmCntKdiEntropyCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

FpvSecCmCntKdiSeedCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

FpvSecCmCntLciCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

FpvSecCmCntScrmblCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

FpvSecCmCtrlDaiFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

FpvSecCmCtrlKdiFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

FpvSecCmCtrlLciFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

FpvSecCmCtrlLfsrTimerFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

FpvSecCmCtrlScrambleFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

FpvSecCmDoubleLfsrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

FpvSecCmTlLcGateFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

IntrOtpErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

IntrOtpOperationDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

LcOtpProgramRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

LcSeedHwRdEnStable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	2195	0	0
T1	187260	12	0	0
T2	11915	1	0	0
T3	13072	1	0	0
T4	44826	3	0	0
T9	83429	0	0	0
T10	11172	0	0	0
T11	4848	0	0	0
T12	15054	0	0	0
T13	14393	1	0	0
T14	12081	0	0	0
T22	0	9	0	0
T23	0	3	0	0
T40	0	10	0	0
T93	0	4	0	0
T104	0	1	0	0

LcSeedHwRdEnStable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	2195	0	0
T1	187260	12	0	0
T2	11915	1	0	0
T3	13072	1	0	0
T4	44826	3	0	0
T9	83429	0	0	0
T10	11172	0	0	0
T11	4848	0	0	0
T12	15054	0	0	0
T13	14393	1	0	0
T14	12081	0	0	0
T22	0	9	0	0
T23	0	3	0	0
T40	0	10	0	0
T93	0	4	0	0
T104	0	1	0	0

LcSeedHwRdEnStable2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	0	0	0

LcSeedHwRdEnStable3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	0	0	0

LcStateSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127	1127	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

LcTransitionCntSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127	1127	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

OtpAstPwrSeqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

OtpBroadcastKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

OtpErrorCode0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127	1127	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

OtpErrorCode1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127	1127	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

OtpErrorCode2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127	1127	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

OtpErrorCode3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127	1127	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

OtpErrorCode4_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127	1127	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

OtpIfWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127	1127	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

OtpKeymgrKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

OtpLcDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

OtpOtgnKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

OtpRespFifoUnderflow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1436500	0	0
T1	187260	6066	0	0
T2	11915	250	0	0
T3	13072	242	0	0
T4	44826	862	0	0
T9	83429	136	0	0
T10	11172	200	0	0
T11	4848	55	0	0
T12	15054	211	0	0
T13	14393	169	0	0
T14	12081	173	0	0

OtpSramKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

PartSelMustBeOnehot_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

PrimTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

PwrOtpInitRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

RmaTokenSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127	1127	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

SramDataKeySeedSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127	1127	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

TestExitTokenSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127	1127	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

TestUnlockTokenSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127	1127	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

gen_partitions[0].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

gen_partitions[10].gen_lifecycle.FpvSecCmCntPartLcCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

gen_partitions[10].gen_lifecycle.FpvSecCmCtrlPartLcFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

gen_partitions[1].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

gen_partitions[2].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

gen_partitions[3].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

gen_partitions[4].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

gen_partitions[5].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

gen_partitions[5].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

gen_partitions[6].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

gen_partitions[6].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

gen_partitions[7].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

gen_partitions[7].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

gen_partitions[8].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

gen_partitions[8].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

gen_partitions[9].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

gen_partitions[9].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

gen_reg_we_assert_generic.FpvSecCmPrimFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0

gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	50	0	0
T28	151181	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T71	83584	0	0	0
T96	60851	0	0	0
T97	120318	0	0	0
T100	27547	0	0	0
T137	15305	0	0	0
T175	14659	0	0	0
T176	31353	0	0	0
T177	16302	0	0	0
T241	0	10	0	0
T242	0	10	0	0
T243	28973	0	0	0