Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

43210445

1

T1

1639

T2

518

T3

37798

full_word

13143889

1

T1

357

T2

211

T3

25027

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	56354004	1			T1	1996		T2	729		T3	62825
auto[TlIntgErrCmd]	118	1			T264	9		T265	8		T266	11
auto[TlIntgErrData]	115	1			T264	7		T265	3		T266	7
auto[TlIntgErrBoth]	97	1			T264	4		T265	9		T266	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11397476

1

T1

1745

T2

473

T3

53099

auto[1]

44956858

1

T1

251

T2

256

T3

9726

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6834439	1			T1	1505		T2	364		T3	31423
auto[TlIntgErrNone]	partial	auto[1]	36375703	1			T1	134		T2	154		T3	6375
auto[TlIntgErrNone]	full_word	auto[0]	4562896	1			T1	240		T2	109		T3	21676
auto[TlIntgErrNone]	full_word	auto[1]	8580966	1			T1	117		T2	102		T3	3351
auto[TlIntgErrCmd]	partial	auto[0]	48	1			T264	2		T265	4		T266	5
auto[TlIntgErrCmd]	partial	auto[1]	58	1			T264	7		T265	3		T266	4
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T356	1		T271	1		T357	2
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T265	1		T266	2		T350	1
auto[TlIntgErrData]	partial	auto[0]	50	1			T265	2		T266	3		T350	5
auto[TlIntgErrData]	partial	auto[1]	59	1			T264	6		T266	3		T350	3
auto[TlIntgErrData]	full_word	auto[0]	2	1			T264	1		T353	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	4	1			T265	1		T266	1		T353	1
auto[TlIntgErrBoth]	partial	auto[0]	33	1			T265	4		T266	1		T350	3
auto[TlIntgErrBoth]	partial	auto[1]	55	1			T264	3		T265	5		T266	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T350	1		T356	1		T273	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T264	1		T348	1		T358	1