Assert Coverage for Module :
otp_ctrl_core_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1325056266 |
15324950 |
0 |
0 |
T7 |
306432 |
542784 |
0 |
0 |
T13 |
0 |
116729 |
0 |
0 |
T14 |
0 |
394164 |
0 |
0 |
T15 |
29475 |
0 |
0 |
0 |
T17 |
0 |
316583 |
0 |
0 |
T33 |
0 |
865508 |
0 |
0 |
T64 |
73457 |
0 |
0 |
0 |
T97 |
50689 |
0 |
0 |
0 |
T101 |
40320 |
0 |
0 |
0 |
T106 |
29615 |
0 |
0 |
0 |
T107 |
16038 |
0 |
0 |
0 |
T135 |
31392 |
0 |
0 |
0 |
T139 |
0 |
250566 |
0 |
0 |
T235 |
5296 |
0 |
0 |
0 |
T247 |
0 |
83187 |
0 |
0 |
T250 |
29419 |
0 |
0 |
0 |
T257 |
0 |
103351 |
0 |
0 |
T275 |
0 |
172495 |
0 |
0 |
T276 |
0 |
82807 |
0 |
0 |
check_regwen_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1325056266 |
5044 |
0 |
0 |
T17 |
358371 |
328 |
0 |
0 |
T30 |
11234 |
0 |
0 |
0 |
T40 |
11964 |
0 |
0 |
0 |
T139 |
238588 |
0 |
0 |
0 |
T169 |
41332 |
0 |
0 |
0 |
T209 |
67670 |
0 |
0 |
0 |
T261 |
8805 |
0 |
0 |
0 |
T283 |
0 |
239 |
0 |
0 |
T291 |
0 |
225 |
0 |
0 |
T292 |
0 |
205 |
0 |
0 |
T295 |
0 |
279 |
0 |
0 |
T324 |
0 |
129 |
0 |
0 |
T325 |
0 |
398 |
0 |
0 |
T327 |
0 |
75 |
0 |
0 |
T331 |
0 |
45 |
0 |
0 |
T332 |
0 |
64 |
0 |
0 |
T333 |
36188 |
0 |
0 |
0 |
T334 |
23639 |
0 |
0 |
0 |
T335 |
14905 |
0 |
0 |
0 |
check_timeout_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1325056266 |
4801 |
0 |
0 |
T17 |
358371 |
326 |
0 |
0 |
T30 |
11234 |
0 |
0 |
0 |
T40 |
11964 |
0 |
0 |
0 |
T139 |
238588 |
0 |
0 |
0 |
T169 |
41332 |
0 |
0 |
0 |
T209 |
67670 |
0 |
0 |
0 |
T261 |
8805 |
0 |
0 |
0 |
T283 |
0 |
227 |
0 |
0 |
T291 |
0 |
144 |
0 |
0 |
T292 |
0 |
149 |
0 |
0 |
T295 |
0 |
418 |
0 |
0 |
T324 |
0 |
190 |
0 |
0 |
T325 |
0 |
569 |
0 |
0 |
T327 |
0 |
37 |
0 |
0 |
T331 |
0 |
61 |
0 |
0 |
T332 |
0 |
45 |
0 |
0 |
T333 |
36188 |
0 |
0 |
0 |
T334 |
23639 |
0 |
0 |
0 |
T335 |
14905 |
0 |
0 |
0 |
check_trigger_regwen_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1325056266 |
4908 |
0 |
0 |
T17 |
358371 |
288 |
0 |
0 |
T30 |
11234 |
0 |
0 |
0 |
T40 |
11964 |
0 |
0 |
0 |
T139 |
238588 |
0 |
0 |
0 |
T169 |
41332 |
0 |
0 |
0 |
T209 |
67670 |
0 |
0 |
0 |
T261 |
8805 |
0 |
0 |
0 |
T283 |
0 |
185 |
0 |
0 |
T291 |
0 |
133 |
0 |
0 |
T292 |
0 |
190 |
0 |
0 |
T295 |
0 |
438 |
0 |
0 |
T324 |
0 |
194 |
0 |
0 |
T325 |
0 |
381 |
0 |
0 |
T327 |
0 |
41 |
0 |
0 |
T331 |
0 |
60 |
0 |
0 |
T332 |
0 |
44 |
0 |
0 |
T333 |
36188 |
0 |
0 |
0 |
T334 |
23639 |
0 |
0 |
0 |
T335 |
14905 |
0 |
0 |
0 |
consistency_check_period_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1325056266 |
5409 |
0 |
0 |
T17 |
358371 |
453 |
0 |
0 |
T30 |
11234 |
0 |
0 |
0 |
T40 |
11964 |
0 |
0 |
0 |
T139 |
238588 |
0 |
0 |
0 |
T169 |
41332 |
0 |
0 |
0 |
T209 |
67670 |
0 |
0 |
0 |
T261 |
8805 |
0 |
0 |
0 |
T283 |
0 |
167 |
0 |
0 |
T291 |
0 |
184 |
0 |
0 |
T292 |
0 |
195 |
0 |
0 |
T295 |
0 |
378 |
0 |
0 |
T324 |
0 |
219 |
0 |
0 |
T325 |
0 |
600 |
0 |
0 |
T327 |
0 |
87 |
0 |
0 |
T331 |
0 |
71 |
0 |
0 |
T332 |
0 |
66 |
0 |
0 |
T333 |
36188 |
0 |
0 |
0 |
T334 |
23639 |
0 |
0 |
0 |
T335 |
14905 |
0 |
0 |
0 |
creator_sw_cfg_read_lock_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1325056266 |
4471 |
0 |
0 |
T17 |
358371 |
304 |
0 |
0 |
T30 |
11234 |
0 |
0 |
0 |
T40 |
11964 |
0 |
0 |
0 |
T139 |
238588 |
0 |
0 |
0 |
T169 |
41332 |
0 |
0 |
0 |
T209 |
67670 |
0 |
0 |
0 |
T261 |
8805 |
0 |
0 |
0 |
T283 |
0 |
232 |
0 |
0 |
T291 |
0 |
158 |
0 |
0 |
T292 |
0 |
241 |
0 |
0 |
T295 |
0 |
315 |
0 |
0 |
T324 |
0 |
178 |
0 |
0 |
T325 |
0 |
506 |
0 |
0 |
T327 |
0 |
66 |
0 |
0 |
T331 |
0 |
35 |
0 |
0 |
T332 |
0 |
47 |
0 |
0 |
T333 |
36188 |
0 |
0 |
0 |
T334 |
23639 |
0 |
0 |
0 |
T335 |
14905 |
0 |
0 |
0 |
direct_access_address_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1325056266 |
3672 |
0 |
0 |
T17 |
358371 |
392 |
0 |
0 |
T30 |
11234 |
0 |
0 |
0 |
T40 |
11964 |
0 |
0 |
0 |
T139 |
238588 |
0 |
0 |
0 |
T169 |
41332 |
0 |
0 |
0 |
T209 |
67670 |
0 |
0 |
0 |
T261 |
8805 |
0 |
0 |
0 |
T283 |
0 |
191 |
0 |
0 |
T291 |
0 |
149 |
0 |
0 |
T292 |
0 |
229 |
0 |
0 |
T295 |
0 |
412 |
0 |
0 |
T324 |
0 |
219 |
0 |
0 |
T325 |
0 |
515 |
0 |
0 |
T327 |
0 |
85 |
0 |
0 |
T331 |
0 |
84 |
0 |
0 |
T332 |
0 |
37 |
0 |
0 |
T333 |
36188 |
0 |
0 |
0 |
T334 |
23639 |
0 |
0 |
0 |
T335 |
14905 |
0 |
0 |
0 |
direct_access_wdata_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1325056266 |
2655 |
0 |
0 |
T17 |
358371 |
252 |
0 |
0 |
T30 |
11234 |
0 |
0 |
0 |
T40 |
11964 |
0 |
0 |
0 |
T139 |
238588 |
0 |
0 |
0 |
T169 |
41332 |
0 |
0 |
0 |
T209 |
67670 |
0 |
0 |
0 |
T261 |
8805 |
0 |
0 |
0 |
T283 |
0 |
168 |
0 |
0 |
T291 |
0 |
123 |
0 |
0 |
T292 |
0 |
177 |
0 |
0 |
T295 |
0 |
311 |
0 |
0 |
T324 |
0 |
110 |
0 |
0 |
T325 |
0 |
373 |
0 |
0 |
T327 |
0 |
32 |
0 |
0 |
T331 |
0 |
34 |
0 |
0 |
T332 |
0 |
35 |
0 |
0 |
T333 |
36188 |
0 |
0 |
0 |
T334 |
23639 |
0 |
0 |
0 |
T335 |
14905 |
0 |
0 |
0 |
direct_access_wdata_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1325056266 |
3173 |
0 |
0 |
T17 |
358371 |
306 |
0 |
0 |
T30 |
11234 |
0 |
0 |
0 |
T40 |
11964 |
0 |
0 |
0 |
T139 |
238588 |
0 |
0 |
0 |
T169 |
41332 |
0 |
0 |
0 |
T209 |
67670 |
0 |
0 |
0 |
T261 |
8805 |
0 |
0 |
0 |
T283 |
0 |
236 |
0 |
0 |
T291 |
0 |
117 |
0 |
0 |
T292 |
0 |
231 |
0 |
0 |
T295 |
0 |
407 |
0 |
0 |
T324 |
0 |
170 |
0 |
0 |
T325 |
0 |
407 |
0 |
0 |
T327 |
0 |
42 |
0 |
0 |
T331 |
0 |
56 |
0 |
0 |
T332 |
0 |
49 |
0 |
0 |
T333 |
36188 |
0 |
0 |
0 |
T334 |
23639 |
0 |
0 |
0 |
T335 |
14905 |
0 |
0 |
0 |
integrity_check_period_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1325056266 |
4805 |
0 |
0 |
T17 |
358371 |
330 |
0 |
0 |
T30 |
11234 |
0 |
0 |
0 |
T40 |
11964 |
0 |
0 |
0 |
T139 |
238588 |
0 |
0 |
0 |
T169 |
41332 |
0 |
0 |
0 |
T209 |
67670 |
0 |
0 |
0 |
T261 |
8805 |
0 |
0 |
0 |
T283 |
0 |
191 |
0 |
0 |
T291 |
0 |
116 |
0 |
0 |
T292 |
0 |
219 |
0 |
0 |
T295 |
0 |
366 |
0 |
0 |
T324 |
0 |
204 |
0 |
0 |
T325 |
0 |
457 |
0 |
0 |
T327 |
0 |
62 |
0 |
0 |
T331 |
0 |
56 |
0 |
0 |
T332 |
0 |
42 |
0 |
0 |
T333 |
36188 |
0 |
0 |
0 |
T334 |
23639 |
0 |
0 |
0 |
T335 |
14905 |
0 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1325056266 |
5972 |
0 |
0 |
T17 |
358371 |
402 |
0 |
0 |
T30 |
11234 |
0 |
0 |
0 |
T40 |
11964 |
0 |
0 |
0 |
T74 |
0 |
5 |
0 |
0 |
T139 |
238588 |
0 |
0 |
0 |
T144 |
0 |
26 |
0 |
0 |
T169 |
41332 |
0 |
0 |
0 |
T209 |
67670 |
0 |
0 |
0 |
T261 |
8805 |
0 |
0 |
0 |
T283 |
0 |
223 |
0 |
0 |
T324 |
0 |
170 |
0 |
0 |
T325 |
0 |
488 |
0 |
0 |
T328 |
0 |
5 |
0 |
0 |
T331 |
0 |
91 |
0 |
0 |
T333 |
36188 |
0 |
0 |
0 |
T334 |
23639 |
0 |
0 |
0 |
T335 |
14905 |
0 |
0 |
0 |
T336 |
0 |
67 |
0 |
0 |
T337 |
0 |
43 |
0 |
0 |
owner_sw_cfg_read_lock_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1325056266 |
4264 |
0 |
0 |
T17 |
358371 |
288 |
0 |
0 |
T30 |
11234 |
0 |
0 |
0 |
T40 |
11964 |
0 |
0 |
0 |
T139 |
238588 |
0 |
0 |
0 |
T169 |
41332 |
0 |
0 |
0 |
T209 |
67670 |
0 |
0 |
0 |
T261 |
8805 |
0 |
0 |
0 |
T283 |
0 |
140 |
0 |
0 |
T291 |
0 |
94 |
0 |
0 |
T292 |
0 |
178 |
0 |
0 |
T295 |
0 |
410 |
0 |
0 |
T324 |
0 |
167 |
0 |
0 |
T325 |
0 |
507 |
0 |
0 |
T327 |
0 |
57 |
0 |
0 |
T331 |
0 |
58 |
0 |
0 |
T332 |
0 |
51 |
0 |
0 |
T333 |
36188 |
0 |
0 |
0 |
T334 |
23639 |
0 |
0 |
0 |
T335 |
14905 |
0 |
0 |
0 |
rot_creator_auth_codesign_read_lock_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1325056266 |
4648 |
0 |
0 |
T17 |
358371 |
371 |
0 |
0 |
T30 |
11234 |
0 |
0 |
0 |
T40 |
11964 |
0 |
0 |
0 |
T139 |
238588 |
0 |
0 |
0 |
T169 |
41332 |
0 |
0 |
0 |
T209 |
67670 |
0 |
0 |
0 |
T261 |
8805 |
0 |
0 |
0 |
T283 |
0 |
221 |
0 |
0 |
T291 |
0 |
106 |
0 |
0 |
T292 |
0 |
160 |
0 |
0 |
T295 |
0 |
388 |
0 |
0 |
T324 |
0 |
205 |
0 |
0 |
T325 |
0 |
541 |
0 |
0 |
T327 |
0 |
29 |
0 |
0 |
T331 |
0 |
40 |
0 |
0 |
T332 |
0 |
24 |
0 |
0 |
T333 |
36188 |
0 |
0 |
0 |
T334 |
23639 |
0 |
0 |
0 |
T335 |
14905 |
0 |
0 |
0 |
rot_creator_auth_state_read_lock_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1325056266 |
4526 |
0 |
0 |
T17 |
358371 |
316 |
0 |
0 |
T30 |
11234 |
0 |
0 |
0 |
T40 |
11964 |
0 |
0 |
0 |
T139 |
238588 |
0 |
0 |
0 |
T169 |
41332 |
0 |
0 |
0 |
T209 |
67670 |
0 |
0 |
0 |
T261 |
8805 |
0 |
0 |
0 |
T283 |
0 |
209 |
0 |
0 |
T291 |
0 |
172 |
0 |
0 |
T292 |
0 |
166 |
0 |
0 |
T295 |
0 |
348 |
0 |
0 |
T324 |
0 |
186 |
0 |
0 |
T325 |
0 |
518 |
0 |
0 |
T327 |
0 |
87 |
0 |
0 |
T331 |
0 |
69 |
0 |
0 |
T332 |
0 |
31 |
0 |
0 |
T333 |
36188 |
0 |
0 |
0 |
T334 |
23639 |
0 |
0 |
0 |
T335 |
14905 |
0 |
0 |
0 |
vendor_test_read_lock_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1325056266 |
3952 |
0 |
0 |
T17 |
358371 |
321 |
0 |
0 |
T30 |
11234 |
0 |
0 |
0 |
T40 |
11964 |
0 |
0 |
0 |
T139 |
238588 |
0 |
0 |
0 |
T169 |
41332 |
0 |
0 |
0 |
T209 |
67670 |
0 |
0 |
0 |
T261 |
8805 |
0 |
0 |
0 |
T283 |
0 |
161 |
0 |
0 |
T291 |
0 |
135 |
0 |
0 |
T292 |
0 |
124 |
0 |
0 |
T295 |
0 |
367 |
0 |
0 |
T324 |
0 |
140 |
0 |
0 |
T325 |
0 |
396 |
0 |
0 |
T327 |
0 |
45 |
0 |
0 |
T331 |
0 |
40 |
0 |
0 |
T332 |
0 |
31 |
0 |
0 |
T333 |
36188 |
0 |
0 |
0 |
T334 |
23639 |
0 |
0 |
0 |
T335 |
14905 |
0 |
0 |
0 |