Assert Coverage for Module :
otp_ctrl_core_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1454434367 |
18078331 |
0 |
0 |
T7 |
419805 |
478388 |
0 |
0 |
T8 |
0 |
112784 |
0 |
0 |
T14 |
0 |
286576 |
0 |
0 |
T30 |
0 |
323080 |
0 |
0 |
T69 |
25587 |
0 |
0 |
0 |
T78 |
12968 |
0 |
0 |
0 |
T90 |
161660 |
0 |
0 |
0 |
T91 |
45812 |
0 |
0 |
0 |
T92 |
24007 |
0 |
0 |
0 |
T93 |
8896 |
0 |
0 |
0 |
T94 |
62728 |
0 |
0 |
0 |
T99 |
172992 |
0 |
0 |
0 |
T122 |
0 |
61538 |
0 |
0 |
T131 |
0 |
250906 |
0 |
0 |
T214 |
9340 |
0 |
0 |
0 |
T218 |
0 |
134364 |
0 |
0 |
T247 |
0 |
238131 |
0 |
0 |
T271 |
0 |
235622 |
0 |
0 |
T280 |
0 |
42638 |
0 |
0 |
check_regwen_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1454434367 |
4576 |
0 |
0 |
T14 |
147239 |
217 |
0 |
0 |
T16 |
15793 |
0 |
0 |
0 |
T30 |
208501 |
0 |
0 |
0 |
T165 |
88780 |
0 |
0 |
0 |
T178 |
179195 |
0 |
0 |
0 |
T216 |
0 |
150 |
0 |
0 |
T244 |
16356 |
0 |
0 |
0 |
T245 |
5807 |
0 |
0 |
0 |
T280 |
0 |
33 |
0 |
0 |
T281 |
11329 |
0 |
0 |
0 |
T282 |
102833 |
0 |
0 |
0 |
T283 |
35718 |
0 |
0 |
0 |
T296 |
0 |
322 |
0 |
0 |
T299 |
0 |
298 |
0 |
0 |
T331 |
0 |
277 |
0 |
0 |
T334 |
0 |
124 |
0 |
0 |
T338 |
0 |
138 |
0 |
0 |
T339 |
0 |
89 |
0 |
0 |
T340 |
0 |
234 |
0 |
0 |
check_timeout_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1454434367 |
4291 |
0 |
0 |
T14 |
147239 |
239 |
0 |
0 |
T16 |
15793 |
0 |
0 |
0 |
T30 |
208501 |
0 |
0 |
0 |
T165 |
88780 |
0 |
0 |
0 |
T178 |
179195 |
0 |
0 |
0 |
T216 |
0 |
161 |
0 |
0 |
T244 |
16356 |
0 |
0 |
0 |
T245 |
5807 |
0 |
0 |
0 |
T280 |
0 |
29 |
0 |
0 |
T281 |
11329 |
0 |
0 |
0 |
T282 |
102833 |
0 |
0 |
0 |
T283 |
35718 |
0 |
0 |
0 |
T296 |
0 |
401 |
0 |
0 |
T299 |
0 |
389 |
0 |
0 |
T331 |
0 |
365 |
0 |
0 |
T334 |
0 |
101 |
0 |
0 |
T338 |
0 |
122 |
0 |
0 |
T339 |
0 |
68 |
0 |
0 |
T340 |
0 |
285 |
0 |
0 |
check_trigger_regwen_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1454434367 |
4633 |
0 |
0 |
T14 |
147239 |
261 |
0 |
0 |
T16 |
15793 |
0 |
0 |
0 |
T30 |
208501 |
0 |
0 |
0 |
T165 |
88780 |
0 |
0 |
0 |
T178 |
179195 |
0 |
0 |
0 |
T216 |
0 |
127 |
0 |
0 |
T244 |
16356 |
0 |
0 |
0 |
T245 |
5807 |
0 |
0 |
0 |
T280 |
0 |
48 |
0 |
0 |
T281 |
11329 |
0 |
0 |
0 |
T282 |
102833 |
0 |
0 |
0 |
T283 |
35718 |
0 |
0 |
0 |
T296 |
0 |
304 |
0 |
0 |
T299 |
0 |
316 |
0 |
0 |
T331 |
0 |
307 |
0 |
0 |
T334 |
0 |
125 |
0 |
0 |
T338 |
0 |
111 |
0 |
0 |
T339 |
0 |
56 |
0 |
0 |
T340 |
0 |
169 |
0 |
0 |
consistency_check_period_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1454434367 |
5270 |
0 |
0 |
T14 |
147239 |
266 |
0 |
0 |
T16 |
15793 |
0 |
0 |
0 |
T30 |
208501 |
0 |
0 |
0 |
T165 |
88780 |
0 |
0 |
0 |
T178 |
179195 |
0 |
0 |
0 |
T216 |
0 |
143 |
0 |
0 |
T244 |
16356 |
0 |
0 |
0 |
T245 |
5807 |
0 |
0 |
0 |
T280 |
0 |
65 |
0 |
0 |
T281 |
11329 |
0 |
0 |
0 |
T282 |
102833 |
0 |
0 |
0 |
T283 |
35718 |
0 |
0 |
0 |
T296 |
0 |
372 |
0 |
0 |
T299 |
0 |
466 |
0 |
0 |
T331 |
0 |
367 |
0 |
0 |
T334 |
0 |
165 |
0 |
0 |
T338 |
0 |
139 |
0 |
0 |
T339 |
0 |
99 |
0 |
0 |
T340 |
0 |
267 |
0 |
0 |
creator_sw_cfg_read_lock_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1454434367 |
4276 |
0 |
0 |
T14 |
147239 |
286 |
0 |
0 |
T16 |
15793 |
0 |
0 |
0 |
T30 |
208501 |
0 |
0 |
0 |
T165 |
88780 |
0 |
0 |
0 |
T178 |
179195 |
0 |
0 |
0 |
T216 |
0 |
184 |
0 |
0 |
T244 |
16356 |
0 |
0 |
0 |
T245 |
5807 |
0 |
0 |
0 |
T280 |
0 |
28 |
0 |
0 |
T281 |
11329 |
0 |
0 |
0 |
T282 |
102833 |
0 |
0 |
0 |
T283 |
35718 |
0 |
0 |
0 |
T296 |
0 |
408 |
0 |
0 |
T299 |
0 |
416 |
0 |
0 |
T331 |
0 |
305 |
0 |
0 |
T334 |
0 |
139 |
0 |
0 |
T338 |
0 |
168 |
0 |
0 |
T339 |
0 |
46 |
0 |
0 |
T340 |
0 |
243 |
0 |
0 |
direct_access_address_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1454434367 |
3297 |
0 |
0 |
T14 |
147239 |
303 |
0 |
0 |
T16 |
15793 |
0 |
0 |
0 |
T30 |
208501 |
0 |
0 |
0 |
T165 |
88780 |
0 |
0 |
0 |
T178 |
179195 |
0 |
0 |
0 |
T216 |
0 |
176 |
0 |
0 |
T244 |
16356 |
0 |
0 |
0 |
T245 |
5807 |
0 |
0 |
0 |
T280 |
0 |
79 |
0 |
0 |
T281 |
11329 |
0 |
0 |
0 |
T282 |
102833 |
0 |
0 |
0 |
T283 |
35718 |
0 |
0 |
0 |
T296 |
0 |
333 |
0 |
0 |
T299 |
0 |
434 |
0 |
0 |
T331 |
0 |
436 |
0 |
0 |
T334 |
0 |
89 |
0 |
0 |
T338 |
0 |
114 |
0 |
0 |
T339 |
0 |
54 |
0 |
0 |
T340 |
0 |
251 |
0 |
0 |
direct_access_wdata_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1454434367 |
2657 |
0 |
0 |
T14 |
147239 |
267 |
0 |
0 |
T16 |
15793 |
0 |
0 |
0 |
T30 |
208501 |
0 |
0 |
0 |
T165 |
88780 |
0 |
0 |
0 |
T178 |
179195 |
0 |
0 |
0 |
T216 |
0 |
131 |
0 |
0 |
T244 |
16356 |
0 |
0 |
0 |
T245 |
5807 |
0 |
0 |
0 |
T280 |
0 |
40 |
0 |
0 |
T281 |
11329 |
0 |
0 |
0 |
T282 |
102833 |
0 |
0 |
0 |
T283 |
35718 |
0 |
0 |
0 |
T296 |
0 |
264 |
0 |
0 |
T299 |
0 |
297 |
0 |
0 |
T331 |
0 |
277 |
0 |
0 |
T334 |
0 |
95 |
0 |
0 |
T338 |
0 |
77 |
0 |
0 |
T339 |
0 |
48 |
0 |
0 |
T340 |
0 |
240 |
0 |
0 |
direct_access_wdata_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1454434367 |
2890 |
0 |
0 |
T14 |
147239 |
252 |
0 |
0 |
T16 |
15793 |
0 |
0 |
0 |
T30 |
208501 |
0 |
0 |
0 |
T165 |
88780 |
0 |
0 |
0 |
T178 |
179195 |
0 |
0 |
0 |
T216 |
0 |
154 |
0 |
0 |
T244 |
16356 |
0 |
0 |
0 |
T245 |
5807 |
0 |
0 |
0 |
T280 |
0 |
35 |
0 |
0 |
T281 |
11329 |
0 |
0 |
0 |
T282 |
102833 |
0 |
0 |
0 |
T283 |
35718 |
0 |
0 |
0 |
T296 |
0 |
325 |
0 |
0 |
T299 |
0 |
354 |
0 |
0 |
T331 |
0 |
337 |
0 |
0 |
T334 |
0 |
98 |
0 |
0 |
T338 |
0 |
139 |
0 |
0 |
T339 |
0 |
52 |
0 |
0 |
T340 |
0 |
209 |
0 |
0 |
integrity_check_period_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1454434367 |
4818 |
0 |
0 |
T14 |
147239 |
245 |
0 |
0 |
T16 |
15793 |
0 |
0 |
0 |
T30 |
208501 |
0 |
0 |
0 |
T165 |
88780 |
0 |
0 |
0 |
T178 |
179195 |
0 |
0 |
0 |
T216 |
0 |
118 |
0 |
0 |
T244 |
16356 |
0 |
0 |
0 |
T245 |
5807 |
0 |
0 |
0 |
T280 |
0 |
49 |
0 |
0 |
T281 |
11329 |
0 |
0 |
0 |
T282 |
102833 |
0 |
0 |
0 |
T283 |
35718 |
0 |
0 |
0 |
T296 |
0 |
259 |
0 |
0 |
T299 |
0 |
388 |
0 |
0 |
T331 |
0 |
439 |
0 |
0 |
T334 |
0 |
185 |
0 |
0 |
T338 |
0 |
167 |
0 |
0 |
T339 |
0 |
46 |
0 |
0 |
T340 |
0 |
141 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1454434367 |
5539 |
0 |
0 |
T14 |
0 |
352 |
0 |
0 |
T25 |
107115 |
0 |
0 |
0 |
T66 |
8918 |
0 |
0 |
0 |
T96 |
390486 |
16 |
0 |
0 |
T97 |
49856 |
0 |
0 |
0 |
T98 |
149827 |
0 |
0 |
0 |
T100 |
0 |
39 |
0 |
0 |
T119 |
33901 |
0 |
0 |
0 |
T146 |
127988 |
0 |
0 |
0 |
T164 |
10693 |
0 |
0 |
0 |
T176 |
60285 |
0 |
0 |
0 |
T181 |
0 |
58 |
0 |
0 |
T216 |
0 |
110 |
0 |
0 |
T227 |
0 |
16 |
0 |
0 |
T280 |
0 |
73 |
0 |
0 |
T296 |
0 |
325 |
0 |
0 |
T334 |
0 |
127 |
0 |
0 |
T338 |
0 |
144 |
0 |
0 |
T341 |
22992 |
0 |
0 |
0 |
owner_sw_cfg_read_lock_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1454434367 |
4103 |
0 |
0 |
T14 |
147239 |
270 |
0 |
0 |
T16 |
15793 |
0 |
0 |
0 |
T30 |
208501 |
0 |
0 |
0 |
T165 |
88780 |
0 |
0 |
0 |
T178 |
179195 |
0 |
0 |
0 |
T216 |
0 |
131 |
0 |
0 |
T244 |
16356 |
0 |
0 |
0 |
T245 |
5807 |
0 |
0 |
0 |
T280 |
0 |
67 |
0 |
0 |
T281 |
11329 |
0 |
0 |
0 |
T282 |
102833 |
0 |
0 |
0 |
T283 |
35718 |
0 |
0 |
0 |
T296 |
0 |
353 |
0 |
0 |
T299 |
0 |
358 |
0 |
0 |
T331 |
0 |
272 |
0 |
0 |
T334 |
0 |
115 |
0 |
0 |
T338 |
0 |
116 |
0 |
0 |
T339 |
0 |
63 |
0 |
0 |
T340 |
0 |
263 |
0 |
0 |
rot_creator_auth_codesign_read_lock_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1454434367 |
4185 |
0 |
0 |
T14 |
147239 |
249 |
0 |
0 |
T16 |
15793 |
0 |
0 |
0 |
T30 |
208501 |
0 |
0 |
0 |
T165 |
88780 |
0 |
0 |
0 |
T178 |
179195 |
0 |
0 |
0 |
T216 |
0 |
94 |
0 |
0 |
T244 |
16356 |
0 |
0 |
0 |
T245 |
5807 |
0 |
0 |
0 |
T280 |
0 |
59 |
0 |
0 |
T281 |
11329 |
0 |
0 |
0 |
T282 |
102833 |
0 |
0 |
0 |
T283 |
35718 |
0 |
0 |
0 |
T296 |
0 |
347 |
0 |
0 |
T299 |
0 |
454 |
0 |
0 |
T331 |
0 |
357 |
0 |
0 |
T334 |
0 |
96 |
0 |
0 |
T338 |
0 |
114 |
0 |
0 |
T339 |
0 |
87 |
0 |
0 |
T340 |
0 |
283 |
0 |
0 |
rot_creator_auth_state_read_lock_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1454434367 |
4122 |
0 |
0 |
T14 |
147239 |
250 |
0 |
0 |
T16 |
15793 |
0 |
0 |
0 |
T30 |
208501 |
0 |
0 |
0 |
T165 |
88780 |
0 |
0 |
0 |
T178 |
179195 |
0 |
0 |
0 |
T216 |
0 |
161 |
0 |
0 |
T244 |
16356 |
0 |
0 |
0 |
T245 |
5807 |
0 |
0 |
0 |
T280 |
0 |
64 |
0 |
0 |
T281 |
11329 |
0 |
0 |
0 |
T282 |
102833 |
0 |
0 |
0 |
T283 |
35718 |
0 |
0 |
0 |
T296 |
0 |
319 |
0 |
0 |
T299 |
0 |
339 |
0 |
0 |
T331 |
0 |
308 |
0 |
0 |
T334 |
0 |
93 |
0 |
0 |
T338 |
0 |
114 |
0 |
0 |
T339 |
0 |
46 |
0 |
0 |
T340 |
0 |
264 |
0 |
0 |
vendor_test_read_lock_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1454434367 |
3822 |
0 |
0 |
T14 |
147239 |
318 |
0 |
0 |
T16 |
15793 |
0 |
0 |
0 |
T30 |
208501 |
0 |
0 |
0 |
T165 |
88780 |
0 |
0 |
0 |
T178 |
179195 |
0 |
0 |
0 |
T216 |
0 |
149 |
0 |
0 |
T244 |
16356 |
0 |
0 |
0 |
T245 |
5807 |
0 |
0 |
0 |
T280 |
0 |
39 |
0 |
0 |
T281 |
11329 |
0 |
0 |
0 |
T282 |
102833 |
0 |
0 |
0 |
T283 |
35718 |
0 |
0 |
0 |
T296 |
0 |
295 |
0 |
0 |
T299 |
0 |
357 |
0 |
0 |
T331 |
0 |
305 |
0 |
0 |
T334 |
0 |
86 |
0 |
0 |
T338 |
0 |
129 |
0 |
0 |
T339 |
0 |
53 |
0 |
0 |
T340 |
0 |
205 |
0 |
0 |