Unified Coverage Report :: Module :: otp_ctrl

Module : otp_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.25	96.79	86.96	87.20		93.10	97.18

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	96.95	98.05	96.15	96.92		96.43	97.18

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.95	98.05	96.15	96.92		96.43	97.18

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.33	94.00	96.69	95.77	91.65	97.56	96.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
core_tlul_assert_device	100.00	100.00				100.00	100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
gen_alert_tx[2].u_prim_alert_sender	100.00			100.00
gen_alert_tx[3].u_prim_alert_sender	100.00			100.00
gen_alert_tx[4].u_prim_alert_sender	100.00			100.00
gen_bufs[0].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
gen_bufs[0].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[10].u_prim_mubi8_sender_read_lock	79.17	37.50				100.00	100.00
gen_bufs[10].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[1].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
gen_bufs[1].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[2].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
gen_bufs[2].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[3].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
gen_bufs[3].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[4].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
gen_bufs[4].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[5].u_prim_mubi8_sender_read_lock	79.17	37.50				100.00	100.00
gen_bufs[5].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[6].u_prim_mubi8_sender_read_lock	79.17	37.50				100.00	100.00
gen_bufs[6].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[7].u_prim_mubi8_sender_read_lock	79.17	37.50				100.00	100.00
gen_bufs[7].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[8].u_prim_mubi8_sender_read_lock	79.17	37.50				100.00	100.00
gen_bufs[8].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[9].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
gen_bufs[9].u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_partitions[0].gen_unbuffered.u_part_unbuf	97.56	100.00	100.00	100.00	90.00	98.15	97.22
gen_partitions[10].gen_lifecycle.u_part_buf	90.60	90.44	100.00	76.96	90.48	100.00	85.71
gen_partitions[1].gen_unbuffered.u_part_unbuf	98.32	100.00	100.00	100.00	91.67	98.25	100.00
gen_partitions[2].gen_unbuffered.u_part_unbuf	98.32	100.00	100.00	100.00	91.67	98.25	100.00
gen_partitions[3].gen_unbuffered.u_part_unbuf	98.32	100.00	100.00	100.00	91.67	98.25	100.00
gen_partitions[4].gen_unbuffered.u_part_unbuf	98.32	100.00	100.00	100.00	91.67	98.25	100.00
gen_partitions[5].gen_buffered.u_part_buf	95.22	98.28	97.62	100.00	92.00	97.06	86.36
gen_partitions[6].gen_buffered.u_part_buf	93.35	96.65	92.86	100.00	91.67	92.54	86.36
gen_partitions[7].gen_buffered.u_part_buf	95.98	98.54	93.75	100.00	91.67	96.25	95.65
gen_partitions[8].gen_buffered.u_part_buf	95.98	98.54	93.75	100.00	91.67	96.25	95.65
gen_partitions[9].gen_buffered.u_part_buf	95.98	98.54	93.75	100.00	91.67	96.25	95.65
otp_ctrl_core_csr_assert	100.00						100.00
prim_tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_arb	87.74	92.31	65.31			100.00	93.33
u_intr_error	100.00	100.00	100.00			100.00	100.00
u_intr_operation_done	100.00	100.00	100.00			100.00	100.00
u_keygmr_key_valid	100.00	100.00				100.00
u_otp	98.90	93.58	99.81	100.00	100.00	100.00	100.00
u_otp_arb	97.25	98.07	97.16			100.00	93.75
u_otp_ctrl_dai	90.27	85.64	91.96	100.00	87.72	89.04	87.23
u_otp_ctrl_kdi	96.45	99.63	99.64	100.00	86.36	95.70	97.37
u_otp_ctrl_lci	100.00	100.00	100.00	100.00	100.00	100.00	100.00
u_otp_ctrl_lfsr_timer	93.08	100.00	89.87	76.92	100.00	91.67	100.00
u_otp_ctrl_scrmbl	96.92	81.50	100.00	100.00	100.00	100.00	100.00
u_otp_init_sync	100.00	100.00				100.00
u_otp_rsp_fifo	100.00	100.00	100.00			100.00	100.00
u_part_sel_idx	74.55	65.65	89.83			88.89	53.85
u_prim_edn_req	92.19	100.00	93.75			100.00	75.00
u_prim_lc_sender_otp_broadcast_valid	100.00	100.00				100.00
u_prim_lc_sender_rma_token_valid	100.00	100.00				100.00
u_prim_lc_sender_secrets_valid	100.00	100.00				100.00
u_prim_lc_sender_test_tokens_valid	100.00	100.00				100.00
u_prim_lc_sync_check_byp_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_creator_seed_sw_rw_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_dft_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_escalate_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_owner_seed_sw_rw_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_seed_hw_rd_en	100.00	100.00				100.00	100.00
u_reg_core	99.15	99.65	96.09	100.00		100.00	100.00
u_scrmbl_mtx	79.48	75.00	99.17			100.00	43.75
u_tlul_adapter_sram	97.59	91.85	98.50			100.00	100.00
u_tlul_lc_gate	97.50	100.00	100.00		100.00	100.00	87.50

Line Coverage for Module : otp_ctrl

	Line No.	Total	Covered	Percent
TOTAL		156	151	96.79
CONT_ASSIGN	246	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
ALWAYS	279	14	13	92.86
ALWAYS	303	3	3	100.00
ALWAYS	319	11	10	90.91
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	381	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	389	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	399	1	1	100.00
ALWAYS	402	5	5	100.00
ALWAYS	429	19	19	100.00
CONT_ASSIGN	483	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
ALWAYS	494	9	9	100.00
ALWAYS	516	10	10	100.00
CONT_ASSIGN	580	1	1	100.00
CONT_ASSIGN	588	1	1	100.00
CONT_ASSIGN	635	1	1	100.00
CONT_ASSIGN	637	1	1	100.00
CONT_ASSIGN	760	1	1	100.00
CONT_ASSIGN	761	1	1	100.00
CONT_ASSIGN	762	1	1	100.00
CONT_ASSIGN	792	1	1	100.00
CONT_ASSIGN	794	1	1	100.00
ALWAYS	871	2	2	100.00
ALWAYS	929	2	2	100.00
ALWAYS	956	4	4	100.00
CONT_ASSIGN	983	1	1	100.00
ALWAYS	986	3	3	100.00
CONT_ASSIGN	1038	1	1	100.00
CONT_ASSIGN	1040	1	1	100.00
CONT_ASSIGN	1074	1	0	0.00
CONT_ASSIGN	1125	1	0	0.00
CONT_ASSIGN	1180	1	1	100.00
CONT_ASSIGN	1180	1	1	100.00
CONT_ASSIGN	1180	1	1	100.00
CONT_ASSIGN	1180	1	1	100.00
CONT_ASSIGN	1180	1	1	100.00
CONT_ASSIGN	1235	1	1	100.00
CONT_ASSIGN	1235	1	1	100.00
CONT_ASSIGN	1235	1	1	100.00
CONT_ASSIGN	1235	1	1	100.00
CONT_ASSIGN	1235	1	1	100.00
CONT_ASSIGN	1295	1	1	100.00
CONT_ASSIGN	1307	1	0	0.00
CONT_ASSIGN	1331	1	1	100.00
ALWAYS	1343	2	2	100.00
CONT_ASSIGN	1357	1	1	100.00
ALWAYS	1385	9	9	100.00
CONT_ASSIGN	1416	1	1	100.00
CONT_ASSIGN	1417	1	1	100.00
CONT_ASSIGN	1419	1	1	100.00
CONT_ASSIGN	1421	1	1	100.00
CONT_ASSIGN	1425	1	1	100.00
CONT_ASSIGN	1427	1	1	100.00
CONT_ASSIGN	1429	1	1	100.00
CONT_ASSIGN	1434	1	1	100.00
CONT_ASSIGN	1436	1	1	100.00
CONT_ASSIGN	1438	1	1	100.00
CONT_ASSIGN	1470	1	1	100.00
CONT_ASSIGN	1472	1	1	100.00
CONT_ASSIGN	1476	1	1	100.00
CONT_ASSIGN	1480	1	1	100.00
CONT_ASSIGN	1484	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
246	1	1
248	10	10
279	1	1
280	1	1
281	1	1
282	1	1
283	1	1
284	1	1
287	0	1
			MISSING_ELSE
292	1	1
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
303	1	1
304	1	1
306	1	1
319	1	1
324	1	1
325	1	1
329	1	1
330	1	1
331	1	1
332	1	1
			MISSING_ELSE
			MISSING_ELSE
336	1	1
337	1	1
338	1	1
339	0	1
			MISSING_ELSE
			MISSING_ELSE
377	1	1
381	1	1
385	1	1
389	1	1
390	1	1
398	1	1
399	1	1
402	1	1
403	1	1
405	1	1
407	1	1
408	1	1
429	1	1
430	1	1
431	1	1
433	1	1
435	1	1
438	1	1
440	1	1
443	1	1
444	1	1
			MISSING_ELSE
448	1	1
450	1	1
454	1	1
457	1	1
459	1	1
464	1	1
465	1	1
			MISSING_ELSE
467	1	1
468	1	1
			MISSING_ELSE
473	1	1
483	1	1
491	1	1
494	1	1
495	1	1
496	1	1
497	1	1
498	1	1
500	1	1
501	1	1
502	1	1
503	1	1
516	1	1
518	1	1
520	1	1
522	1	1
524	1	1
533	1	1
535	1	1
536	1	1
537	1	1
538	1	1
580	1	1
588	1	1
635	1	1
637	1	1
760	1	1
761	1	1
762	1	1
792	1	1
794	1	1
871	1	1
872	1	1
929	1	1
930	1	1
956	1	1
957	1	1
958	1	1
959	1	1
983	1	1
986	1	1
987	1	1
989	1	1
1038	1	1
1040	1	1
1074	0	1
1125	0	1
1180	5	5
1235	5	5
1295	1	1
1307	0	1
1331	1	1
1343	1	1
1344	1	1
1357	1	1
1385	1	1
1386	1	1
1387	1	1
1388	1	1
1390	1	1
1391	1	1
1392	1	1
1393	1	1
1394	1	1
1416	1	1
1417	1	1
1419	1	1
1421	1	1
1425	1	1
1427	1	1
1429	1	1
1434	1	1
1436	1	1
1438	1	1
1470	1	1
1472	1	1
1476	1	1
1480	1	1
1484	1	1

---

Cond Coverage for Module : otp_ctrl

	Total	Covered	Percent
Conditions	115	100	86.96
Logical	115	100	86.96
Non-Logical	0	0
Event	0	0

 LINE       248
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b00001000000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[1].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T9,T10

 LINE       248
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b00111101000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[2].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       248
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b10001111000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[3].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       248
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11001010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[4].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T14
1	1	Covered	T1,T3,T4

 LINE       248
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11001111000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[5].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T14
1	1	Covered	T7,T8,T14

 LINE       248
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011000000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[6].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T14
1	1	Covered	T7,T8,T14

 LINE       248
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[7].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T14
1	1	Covered	T7,T8,T14

 LINE       248
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011111000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[8].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T14
1	1	Covered	T7,T8,T14

 LINE       248
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11101010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[9].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T14
1	1	Covered	T7,T8,T14

 LINE       248
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11110101000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[10].PartEnd))
             -------------------1------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T8,T14

 LINE       283
 EXPRESSION (tlul_part_sel_oh != '0)
            ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       292
 EXPRESSION (((|part_tlul_gnt)) | tlul_oob_err_q)
             ---------1--------   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       293
 EXPRESSION (((|part_tlul_rvalid)) | tlul_oob_err_q)
             ----------1----------   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       377
 EXPRESSION ((reg2hw.direct_access_regwen.qe && ((!reg2hw.direct_access_regwen.q))) ? 1'b0 : direct_access_regwen_q)
             -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       377
 SUB-EXPRESSION (reg2hw.direct_access_regwen.qe && ((!reg2hw.direct_access_regwen.q)))
                 ---------------1--------------    -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       381
 EXPRESSION (reg2hw.direct_access_cmd.digest.qe | reg2hw.direct_access_cmd.wr.qe | reg2hw.direct_access_cmd.rd.qe)
             -----------------1----------------   ---------------2--------------   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       398
 EXPRESSION (lci_prog_idle & dai_prog_idle)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       431
 EXPRESSION (fatal_bus_integ_error_q | ((|intg_error)))
             -----------1-----------   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T24,T25,T26
1	0	Not Covered

 LINE       440
 EXPRESSION (part_error[k] == MacroError)
            --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       444
 EXPRESSION (part_error[k] == MacroEccUncorrError)
            -------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T10,T104

 LINE       464
 EXPRESSION (fatal_macro_error_q || fatal_check_error_q)
             ---------1---------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T9
1	0	Covered	T1,T10,T104

 LINE       473
 EXPRESSION (chk_timeout | lfsr_fsm_err | scrmbl_fsm_err | ((|part_fsm_err)))
             -----1-----   ------2-----   -------3------   --------4--------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T1,T9,T10
0	0	1	0	Covered	T24,T25,T26
0	1	0	0	Covered	T24,T25,T26
1	0	0	0	Covered	T5,T52,T55

 LINE       522
 EXPRESSION (direct_access_regwen_q & dai_idle)
             -----------1----------   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       588
 SUB-EXPRESSION (reg2hw.alert_test.recov_prim_otp_alert.q & reg2hw.alert_test.recov_prim_otp_alert.qe)
                 --------------------1-------------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T244,T245,T246
1	0	Covered	T1,T2,T3
1	1	Covered	T244,T245,T246

 LINE       588
 SUB-EXPRESSION (reg2hw.alert_test.fatal_prim_otp_alert.q & reg2hw.alert_test.fatal_prim_otp_alert.qe)
                 --------------------1-------------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T244,T245,T246
1	0	Covered	T1,T2,T3
1	1	Covered	T244,T245,T246

 LINE       588
 SUB-EXPRESSION (reg2hw.alert_test.fatal_bus_integ_error.q & reg2hw.alert_test.fatal_bus_integ_error.qe)
                 --------------------1--------------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T244,T245,T246
1	0	Covered	T1,T2,T3
1	1	Covered	T244,T245,T246

 LINE       588
 SUB-EXPRESSION (reg2hw.alert_test.fatal_check_error.q & reg2hw.alert_test.fatal_check_error.qe)
                 ------------------1------------------   -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T244,T245,T246
1	0	Covered	T1,T2,T3
1	1	Covered	T244,T245,T246

 LINE       588
 SUB-EXPRESSION (reg2hw.alert_test.fatal_macro_error.q & reg2hw.alert_test.fatal_macro_error.qe)
                 ------------------1------------------   -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T244,T245,T246
1	0	Covered	T1,T2,T3
1	1	Covered	T244,T245,T246

 LINE       635
 EXPRESSION (reg2hw.check_trigger.integrity.q & reg2hw.check_trigger.integrity.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       637
 EXPRESSION (reg2hw.check_trigger.consistency.q & reg2hw.check_trigger.consistency.qe)
             -----------------1----------------   -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       760
 EXPRESSION (otp_prim_ready & otp_rsp_fifo_ready)
             -------1------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       761
 EXPRESSION (otp_arb_valid & otp_rsp_fifo_ready)
             ------1------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       762
 EXPRESSION (otp_prim_ready & otp_prim_valid)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       872
 EXPRESSION (otp_rvalid & otp_fifo_valid)
             -----1----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       1416
 EXPRESSION (part_digest[Secret1Idx] != '0)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T12

 LINE       1434
 EXPRESSION ((part_digest[Secret0Idx] != '0) ? On : Off)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T11,T12

 LINE       1434
 SUB-EXPRESSION (part_digest[Secret0Idx] != '0)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T11,T12

 LINE       1436
 EXPRESSION ((part_digest[Secret2Idx] != '0) ? On : Off)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T5,T13

 LINE       1436
 SUB-EXPRESSION (part_digest[Secret2Idx] != '0)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T5,T13

 LINE       1438
 EXPRESSION ((part_digest[Secret2Idx] != '0) ? On : Off)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T5,T13

 LINE       1438
 SUB-EXPRESSION (part_digest[Secret2Idx] != '0)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T5,T13

---

Toggle Coverage for Module : otp_ctrl

	Total	Covered	Percent
Totals	155	141	90.97
Total Bits	11096	9676	87.20
Total Bits 0->1	5548	4838	87.20
Total Bits 1->0	5548	4838	87.20

Ports	155	141	90.97
Port Bits	11096	9676	87.20
Port Bits 0->1	5548	4838	87.20
Port Bits 1->0	5548	4838	87.20

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_o.edn_req	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
edn_i.edn_fips	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
edn_i.edn_ack	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
core_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_user.instr_type[3:0]	Yes	Yes	T3,T13,T104	Yes	T3,T13,T104	INPUT
core_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
core_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
core_tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_source[7:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
core_tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
prim_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
prim_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
prim_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
prim_tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T10,T11	Yes	T1,T10,T11	INPUT
prim_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
prim_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
prim_tl_i.a_mask[3:0]	Yes	Yes	T1,T11,T103	Yes	T1,T10,T11	INPUT
prim_tl_i.a_address[31:0]	Yes	Yes	T1,T10,T11	Yes	T1,T10,T11	INPUT
prim_tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
prim_tl_i.a_size[1:0]	Yes	Yes	T1,T10,T11	Yes	T1,T11,T103	INPUT
prim_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
prim_tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
prim_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
prim_tl_o.a_ready	Yes	Yes	T13,T103,T63	Yes	T13,T103,T63	OUTPUT
prim_tl_o.d_error	Yes	Yes	T13,T24,T31	Yes	T13,T24,T31	OUTPUT
prim_tl_o.d_user.data_intg[6:0]	Yes	Yes	T13,T31,T62	Yes	T13,T31,T62	OUTPUT
prim_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
prim_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_data[31:0]	Yes	Yes	T13,T24,T31	Yes	T13,T24,T31	OUTPUT
prim_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
prim_tl_o.d_size[1:0]	Yes	Yes	T7,T8,T14	Yes	T7,T8,T14	OUTPUT
prim_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
prim_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
intr_otp_operation_done_o	Yes	Yes	T1,T4,T9	Yes	T1,T4,T9	OUTPUT
intr_otp_error_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T10,T104	Yes	T1,T10,T104	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T24,T25,T244	Yes	T24,T25,T244	INPUT
alert_rx_i[2].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[3].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T24,T25,T244	Yes	T24,T25,T244	INPUT
alert_rx_i[3].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[3].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[4].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[4].ack_p	Yes	Yes	T244,T245,T246	Yes	T244,T245,T246	INPUT
alert_rx_i[4].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[4].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T10,T104	Yes	T1,T10,T104	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T24,T25,T244	Yes	T24,T25,T244	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T24,T25,T244	Yes	T24,T25,T244	OUTPUT
alert_tx_o[4].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[4].alert_p	Yes	Yes	T244,T245,T246	Yes	T244,T245,T246	OUTPUT
obs_ctrl_i.obmen[3:0]	No	No		No		INPUT
obs_ctrl_i.obmsl[3:0]	No	No		No		INPUT
obs_ctrl_i.obgsl[3:0]	No	No		No		INPUT
otp_obs_o[7:0]	Unreachable	Unreachable		Unreachable		OUTPUT
otp_ast_pwr_seq_o.pwr_seq[1:0]	No	No		No		OUTPUT
otp_ast_pwr_seq_h_i.pwr_seq_h[1:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T10	INPUT
pwr_otp_i.otp_init	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwr_otp_o.otp_idle	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwr_otp_o.otp_done	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
lc_otp_vendor_test_i.ctrl[31:0]	No	No		No		INPUT
lc_otp_vendor_test_o.status[31:0]	No	No		No		OUTPUT
lc_otp_program_i.count[383:0]	Yes	Yes	T96,T7,T247	Yes	T96,T248,T219	INPUT
lc_otp_program_i.state[319:0]	Yes	Yes	T96,T7,T177	Yes	T96,T7,T177	INPUT
lc_otp_program_i.req	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
lc_otp_program_o.ack	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
lc_otp_program_o.err	Yes	Yes	T6,T96,T249	Yes	T6,T96,T249	OUTPUT
lc_creator_seed_sw_rw_en_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T4	INPUT
lc_owner_seed_sw_rw_en_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T4	INPUT
lc_seed_hw_rd_en_i[3:0]	Yes	Yes	T1,T4,T9	Yes	T1,T2,T4	INPUT
lc_dft_en_i[3:0]	Yes	Yes	T2,T9,T5	Yes	T2,T3,T11	INPUT
lc_escalate_en_i[3:0]	Yes	Yes	T3,T12,T103	Yes	T3,T12,T103	INPUT
lc_check_byp_en_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
otp_lc_data_o.rma_token[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.rma_token_valid[3:0]	Yes	Yes	T12,T5,T13	Yes	T12,T5,T13	OUTPUT
otp_lc_data_o.test_exit_token[127:0]	Yes	Yes	T11,T102,T107	Yes	T102,T114,T55	OUTPUT
otp_lc_data_o.test_unlock_token[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.test_tokens_valid[3:0]	Yes	Yes	T4,T12,T5	Yes	T4,T11,T12	OUTPUT
otp_lc_data_o.secrets_valid[3:0]	Yes	Yes	T12,T5,T13	Yes	T12,T5,T13	OUTPUT
otp_lc_data_o.count[0]	No	No		No		OUTPUT
otp_lc_data_o.count[8:1]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[9]	No	No		No		OUTPUT
otp_lc_data_o.count[10]	Yes	Yes	*T1,*T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[11]	No	No		No		OUTPUT
otp_lc_data_o.count[14:12]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[16:15]	No	No		No		OUTPUT
otp_lc_data_o.count[28:17]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[30:29]	No	No		No		OUTPUT
otp_lc_data_o.count[31]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[32]	No	No		No		OUTPUT
otp_lc_data_o.count[41:33]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[42]	No	No		No		OUTPUT
otp_lc_data_o.count[51:43]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[52]	No	No		No		OUTPUT
otp_lc_data_o.count[63:53]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[65:64]	No	No		No		OUTPUT
otp_lc_data_o.count[76:66]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[77]	No	No		No		OUTPUT
otp_lc_data_o.count[85:78]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[86]	No	No		No		OUTPUT
otp_lc_data_o.count[100:87]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[101]	No	No		No		OUTPUT
otp_lc_data_o.count[121:102]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[122]	No	No		No		OUTPUT
otp_lc_data_o.count[124:123]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[125]	No	No		No		OUTPUT
otp_lc_data_o.count[137:126]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[138]	No	No		No		OUTPUT
otp_lc_data_o.count[150:139]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[151]	No	No		No		OUTPUT
otp_lc_data_o.count[155:152]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[156]	No	No		No		OUTPUT
otp_lc_data_o.count[158:157]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[160:159]	No	No		No		OUTPUT
otp_lc_data_o.count[165:161]	Yes	Yes	T1,T4,*T102	Yes	T1,T4,T102	OUTPUT
otp_lc_data_o.count[166]	No	No		No		OUTPUT
otp_lc_data_o.count[174:167]	Yes	Yes	T1,T4,*T102	Yes	T1,T4,T102	OUTPUT
otp_lc_data_o.count[175]	No	No		No		OUTPUT
otp_lc_data_o.count[185:176]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[186]	No	No		No		OUTPUT
otp_lc_data_o.count[191:187]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[192]	No	No		No		OUTPUT
otp_lc_data_o.count[193]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[194]	No	No		No		OUTPUT
otp_lc_data_o.count[198:195]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[199]	No	No		No		OUTPUT
otp_lc_data_o.count[217:200]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[218]	No	No		No		OUTPUT
otp_lc_data_o.count[225:219]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[227:226]	No	No		No		OUTPUT
otp_lc_data_o.count[228]	Yes	Yes	*T1,*T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[229]	No	No		No		OUTPUT
otp_lc_data_o.count[232:230]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[233]	No	No		No		OUTPUT
otp_lc_data_o.count[237:234]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[238]	No	No		No		OUTPUT
otp_lc_data_o.count[240:239]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[241]	No	No		No		OUTPUT
otp_lc_data_o.count[251:242]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[252]	No	No		No		OUTPUT
otp_lc_data_o.count[265:253]	Yes	Yes	T1,*T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[266]	No	No		No		OUTPUT
otp_lc_data_o.count[269:267]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[270]	No	No		No		OUTPUT
otp_lc_data_o.count[274:271]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[275]	No	No		No		OUTPUT
otp_lc_data_o.count[301:276]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[304:302]	No	No		No		OUTPUT
otp_lc_data_o.count[309:305]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[310]	No	No		No		OUTPUT
otp_lc_data_o.count[316:311]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[317]	No	No		No		OUTPUT
otp_lc_data_o.count[330:318]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[331]	No	No		No		OUTPUT
otp_lc_data_o.count[333:332]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[334]	No	No		No		OUTPUT
otp_lc_data_o.count[335]	Yes	Yes	*T1,*T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[337:336]	No	No		No		OUTPUT
otp_lc_data_o.count[343:338]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[344]	No	No		No		OUTPUT
otp_lc_data_o.count[365:345]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[367:366]	No	No		No		OUTPUT
otp_lc_data_o.count[371:368]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[372]	No	No		No		OUTPUT
otp_lc_data_o.count[383:373]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[12:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[13]	No	No		No		OUTPUT
otp_lc_data_o.state[15:14]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[16]	No	No		No		OUTPUT
otp_lc_data_o.state[17]	Yes	Yes	*T1,*T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[20:18]	No	No		No		OUTPUT
otp_lc_data_o.state[34:21]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[35]	No	No		No		OUTPUT
otp_lc_data_o.state[36]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[37]	No	No		No		OUTPUT
otp_lc_data_o.state[47:38]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[48]	No	No		No		OUTPUT
otp_lc_data_o.state[50:49]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[52:51]	No	No		No		OUTPUT
otp_lc_data_o.state[65:53]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[66]	No	No		No		OUTPUT
otp_lc_data_o.state[73:67]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[74]	No	No		No		OUTPUT
otp_lc_data_o.state[77:75]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[78]	No	No		No		OUTPUT
otp_lc_data_o.state[83:79]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[85:84]	No	No		No		OUTPUT
otp_lc_data_o.state[87:86]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[88]	No	No		No		OUTPUT
otp_lc_data_o.state[95:89]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[96]	No	No		No		OUTPUT
otp_lc_data_o.state[98:97]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[99]	No	No		No		OUTPUT
otp_lc_data_o.state[101:100]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[102]	No	No		No		OUTPUT
otp_lc_data_o.state[103]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[104]	No	No		No		OUTPUT
otp_lc_data_o.state[113:105]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[115:114]	No	No		No		OUTPUT
otp_lc_data_o.state[121:116]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[122]	No	No		No		OUTPUT
otp_lc_data_o.state[123]	Yes	Yes	*T1,*T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[124]	No	No		No		OUTPUT
otp_lc_data_o.state[126:125]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[127]	No	No		No		OUTPUT
otp_lc_data_o.state[134:128]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[135]	No	No		No		OUTPUT
otp_lc_data_o.state[136]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[137]	No	No		No		OUTPUT
otp_lc_data_o.state[141:138]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[142]	No	No		No		OUTPUT
otp_lc_data_o.state[146:143]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[147]	No	No		No		OUTPUT
otp_lc_data_o.state[149:148]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[150]	No	No		No		OUTPUT
otp_lc_data_o.state[152:151]	Yes	Yes	T1,T5,T13	Yes	T1,T5,T13	OUTPUT
otp_lc_data_o.state[154:153]	No	No		No		OUTPUT
otp_lc_data_o.state[156:155]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[157]	No	No		No		OUTPUT
otp_lc_data_o.state[160:158]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[161]	No	No		No		OUTPUT
otp_lc_data_o.state[163:162]	Yes	Yes	T1,*T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[164]	No	No		No		OUTPUT
otp_lc_data_o.state[177:165]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[178]	No	No		No		OUTPUT
otp_lc_data_o.state[181:179]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[184:182]	No	No		No		OUTPUT
otp_lc_data_o.state[186:185]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[187]	No	No		No		OUTPUT
otp_lc_data_o.state[198:188]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[199]	No	No		No		OUTPUT
otp_lc_data_o.state[210:200]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[211]	No	No		No		OUTPUT
otp_lc_data_o.state[215:212]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[216]	No	No		No		OUTPUT
otp_lc_data_o.state[226:217]	Yes	Yes	T1,*T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[227]	No	No		No		OUTPUT
otp_lc_data_o.state[230:228]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[231]	No	No		No		OUTPUT
otp_lc_data_o.state[234:232]	Yes	Yes	T1,T5,T13	Yes	T1,T5,T13	OUTPUT
otp_lc_data_o.state[235]	No	No		No		OUTPUT
otp_lc_data_o.state[236]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[237]	No	No		No		OUTPUT
otp_lc_data_o.state[239:238]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[240]	No	No		No		OUTPUT
otp_lc_data_o.state[260:241]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[261]	No	No		No		OUTPUT
otp_lc_data_o.state[263:262]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[264]	No	No		No		OUTPUT
otp_lc_data_o.state[268:265]	Yes	Yes	T1,*T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[269]	No	No		No		OUTPUT
otp_lc_data_o.state[273:270]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[274]	No	No		No		OUTPUT
otp_lc_data_o.state[278:275]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[280:279]	No	No		No		OUTPUT
otp_lc_data_o.state[285:281]	Yes	Yes	T1,T5,T13	Yes	T1,T5,T13	OUTPUT
otp_lc_data_o.state[286]	No	No		No		OUTPUT
otp_lc_data_o.state[301:287]	Yes	Yes	T1,*T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[302]	No	No		No		OUTPUT
otp_lc_data_o.state[306:303]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[307]	No	No		No		OUTPUT
otp_lc_data_o.state[319:308]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_keymgr_key_o.owner_seed_valid	No	No		No		OUTPUT
otp_keymgr_key_o.owner_seed[255:0]	No	No		No		OUTPUT
otp_keymgr_key_o.creator_seed_valid	No	No		No		OUTPUT
otp_keymgr_key_o.creator_seed[255:0]	No	No		No		OUTPUT
otp_keymgr_key_o.creator_root_key_share1_valid	Yes	Yes	T12,T5,T13	Yes	T12,T5,T13	OUTPUT
otp_keymgr_key_o.creator_root_key_share1[255:0]	Yes	Yes	T1,T2,T4	Yes	T1,T9,T12	OUTPUT
otp_keymgr_key_o.creator_root_key_share0_valid	Yes	Yes	T12,T5,T13	Yes	T12,T5,T13	OUTPUT
otp_keymgr_key_o.creator_root_key_share0[255:0]	Yes	Yes	T5,T31,T97	Yes	T5,T31,T97	OUTPUT
flash_otp_key_i.addr_req	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
flash_otp_key_i.data_req	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
flash_otp_key_o.seed_valid	Yes	Yes	T4,T5,T13	Yes	T4,T5,T13	OUTPUT
flash_otp_key_o.rand_key[127:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
flash_otp_key_o.key[127:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
flash_otp_key_o.addr_ack	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
flash_otp_key_o.data_ack	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
sram_otp_key_i[0].req	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
sram_otp_key_i[1].req	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
sram_otp_key_i[2].req	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
sram_otp_key_i[3].req	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
sram_otp_key_o[0].seed_valid	Yes	Yes	T4,T5,T13	Yes	T4,T5,T13	OUTPUT
sram_otp_key_o[0].nonce[127:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
sram_otp_key_o[0].key[127:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
sram_otp_key_o[0].ack	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
sram_otp_key_o[1].seed_valid	Yes	Yes	T4,T5,T13	Yes	T4,T5,T13	OUTPUT
sram_otp_key_o[1].nonce[127:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
sram_otp_key_o[1].key[127:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
sram_otp_key_o[1].ack	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
sram_otp_key_o[2].seed_valid	Yes	Yes	T4,T5,T13	Yes	T4,T5,T13	OUTPUT
sram_otp_key_o[2].nonce[127:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
sram_otp_key_o[2].key[127:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
sram_otp_key_o[2].ack	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
sram_otp_key_o[3].seed_valid	Yes	Yes	T4,T5,T13	Yes	T4,T5,T13	OUTPUT
sram_otp_key_o[3].nonce[127:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
sram_otp_key_o[3].key[127:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
sram_otp_key_o[3].ack	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otbn_otp_key_i.req	Yes	Yes	T1,T4,T11	Yes	T1,T4,T11	INPUT
otbn_otp_key_o.seed_valid	Yes	Yes	T4,T5,T13	Yes	T4,T5,T13	OUTPUT
otbn_otp_key_o.nonce[63:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otbn_otp_key_o.key[127:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otbn_otp_key_o.ack	Yes	Yes	T1,T5,T13	Yes	T1,T5,T13	OUTPUT
otp_broadcast_o.hw_cfg0_data.device_id[255:0]	Yes	Yes	T114,T96,T90	Yes	T114,T96,T90	OUTPUT
otp_broadcast_o.hw_cfg0_data.manuf_state[255:0]	Yes	Yes	T96,T90,T99	Yes	T96,T90,T99	OUTPUT
otp_broadcast_o.hw_cfg0_data.hw_cfg0_digest[63:0]	Yes	Yes	T102,T55,T62	Yes	T102,T105,T55	OUTPUT
otp_broadcast_o.hw_cfg1_data.en_sram_ifetch[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_broadcast_o.hw_cfg1_data.en_csrng_sw_app_read[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_broadcast_o.hw_cfg1_data.unallocated[47:0]	Yes	Yes	T114,T31,T55	Yes	T3,T107,T114	OUTPUT
otp_broadcast_o.hw_cfg1_data.hw_cfg1_digest[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_broadcast_o.valid[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_ext_voltage_h_io	No	No		No		INOUT
scan_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T4,T9	INPUT
scan_rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T4,T10	INPUT
scanmode_i[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T9	INPUT
cio_test_o[7:0]	No	No		No		OUTPUT
cio_test_en_o[7:0]	Yes	Yes	T13,T24,T31	Yes	T13,T24,T31	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : otp_ctrl

	Line No.	Total	Covered	Percent
Branches		29	27	93.10
TERNARY	377	2	1	50.00
TERNARY	1434	2	2	100.00
TERNARY	1436	2	2	100.00
TERNARY	1438	2	2	100.00
IF	282	3	2	66.67
IF	303	2	2	100.00
IF	329	2	2	100.00
IF	336	2	2	100.00
IF	402	2	2	100.00
IF	443	2	2	100.00
IF	464	2	2	100.00
IF	467	2	2	100.00
IF	494	2	2	100.00
IF	986	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	377	((reg2hw.direct_access_regwen.qe && (!reg2hw.direct_access_regwen.q))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1434	((part_digest[Secret0Idx] != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1436	((part_digest[Secret2Idx] != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T5,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1438	((part_digest[Secret2Idx] != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T5,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	282	if (tlul_req)
-2-:	283	if ((tlul_part_sel_oh != '0))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Not Covered
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	303	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	329	if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_creator_seed_sw_rw_en))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	336	if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_owner_seed_sw_rw_en))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	402	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	443	if (otp_ctrl_part_pkg::PartInfo[k].integrity)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((fatal_macro_error_q || fatal_check_error_q))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	467	if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_escalate_en[k]))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	494	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	986	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : otp_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	71	71	100.00	69	97.18
Cover properties	0	0		0
Cover sequences	0	0		0
Total	71	71	100.00	69	97.18

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnown_A	1451411390	1450559481	0	0
CoreTlOutKnown_A	1451411390	1450559481	0	0
CreatorRootKeyShare0Size_A	1123	1123	0	0
CreatorRootKeyShare1Size_A	1123	1123	0	0
ErrorCodeWidth_A	1123	1123	0	0
FlashAddrKeySeedSize_A	1123	1123	0	0
FlashDataKeySeedSize_A	1123	1123	0	0
FlashOtpKeyRspKnown_A	1451411390	1450559481	0	0
FpvSecCmCntCnstyCheck_A	1451411390	50	0	0
FpvSecCmCntDaiCheck_A	1451411390	50	0	0
FpvSecCmCntIntegCheck_A	1451411390	50	0	0
FpvSecCmCntKdiEntropyCheck_A	1451411390	50	0	0
FpvSecCmCntKdiSeedCheck_A	1451411390	50	0	0
FpvSecCmCntLciCheck_A	1451411390	50	0	0
FpvSecCmCntScrmblCheck_A	1451411390	50	0	0
FpvSecCmCtrlDaiFsmCheck_A	1451411390	50	0	0
FpvSecCmCtrlKdiFsmCheck_A	1451411390	50	0	0
FpvSecCmCtrlLciFsmCheck_A	1451411390	50	0	0
FpvSecCmCtrlLfsrTimerFsmCheck_A	1451411390	50	0	0
FpvSecCmCtrlScrambleFsmCheck_A	1451411390	50	0	0
FpvSecCmDoubleLfsrCheck_A	1451411390	50	0	0
FpvSecCmRegWeOnehotCheck_A	1451411390	50	0	0
FpvSecCmTlLcGateFsm_A	1451411390	50	0	0
IntrOtpErrorKnown_A	1451411390	1450559481	0	0
IntrOtpOperationDoneKnown_A	1451411390	1450559481	0	0
LcOtpProgramRspKnown_A	1451411390	1450559481	0	0
LcSeedHwRdEnStable0_A	1451411390	2200	0	0
LcSeedHwRdEnStable1_A	1451411390	2200	0	0
LcSeedHwRdEnStable2_A	1451411390	0	0	0
LcSeedHwRdEnStable3_A	1451411390	0	0	0
LcStateSize_A	1123	1123	0	0
LcTransitionCntSize_A	1123	1123	0	0
OtpAstPwrSeqKnown_A	1451411390	1450559481	0	0
OtpBroadcastKnown_A	1451411390	1450559481	0	0
OtpErrorCode0_A	1123	1123	0	0
OtpErrorCode1_A	1123	1123	0	0
OtpErrorCode2_A	1123	1123	0	0
OtpErrorCode3_A	1123	1123	0	0
OtpErrorCode4_A	1123	1123	0	0
OtpIfWidth_A	1123	1123	0	0
OtpKeymgrKeyKnown_A	1451411390	1450559481	0	0
OtpLcDataKnown_A	1451411390	1450559481	0	0
OtpOtgnKeyKnown_A	1451411390	1450559481	0	0
OtpRespFifoUnderflow_A	1451411390	1245821	0	0
OtpSramKeyKnown_A	1451411390	1450559481	0	0
PartSelMustBeOnehot_A	1451411390	1450559481	0	0
PrimTlOutKnown_A	1451411390	1450559481	0	0
PwrOtpInitRspKnown_A	1451411390	1450559481	0	0
RmaTokenSize_A	1123	1123	0	0
SramDataKeySeedSize_A	1123	1123	0	0
TestExitTokenSize_A	1123	1123	0	0
TestUnlockTokenSize_A	1123	1123	0	0
gen_partitions[0].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	1451411390	50	0	0
gen_partitions[10].gen_lifecycle.FpvSecCmCntPartLcCheck_A	1451411390	50	0	0
gen_partitions[10].gen_lifecycle.FpvSecCmCtrlPartLcFsmCheck_A	1451411390	50	0	0
gen_partitions[1].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	1451411390	50	0	0
gen_partitions[2].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	1451411390	50	0	0
gen_partitions[3].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	1451411390	50	0	0
gen_partitions[4].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	1451411390	50	0	0
gen_partitions[5].gen_buffered.FpvSecCmCntPartBufCheck_A	1451411390	50	0	0
gen_partitions[5].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	1451411390	50	0	0
gen_partitions[6].gen_buffered.FpvSecCmCntPartBufCheck_A	1451411390	50	0	0
gen_partitions[6].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	1451411390	50	0	0
gen_partitions[7].gen_buffered.FpvSecCmCntPartBufCheck_A	1451411390	50	0	0
gen_partitions[7].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	1451411390	50	0	0
gen_partitions[8].gen_buffered.FpvSecCmCntPartBufCheck_A	1451411390	50	0	0
gen_partitions[8].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	1451411390	50	0	0
gen_partitions[9].gen_buffered.FpvSecCmCntPartBufCheck_A	1451411390	50	0	0
gen_partitions[9].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	1451411390	50	0	0
gen_reg_we_assert_generic.FpvSecCmPrimFsmCheck_A	1451411390	50	0	0
gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A	1451411390	50	0	0

AlertTxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

CoreTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

CreatorRootKeyShare0Size_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123	1123	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

CreatorRootKeyShare1Size_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123	1123	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

ErrorCodeWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123	1123	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

FlashAddrKeySeedSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123	1123	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

FlashDataKeySeedSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123	1123	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

FlashOtpKeyRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

FpvSecCmCntCnstyCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

FpvSecCmCntDaiCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

FpvSecCmCntIntegCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

FpvSecCmCntKdiEntropyCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

FpvSecCmCntKdiSeedCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

FpvSecCmCntLciCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

FpvSecCmCntScrmblCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

FpvSecCmCtrlDaiFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

FpvSecCmCtrlKdiFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

FpvSecCmCtrlLciFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

FpvSecCmCtrlLfsrTimerFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

FpvSecCmCtrlScrambleFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

FpvSecCmDoubleLfsrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

FpvSecCmTlLcGateFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

IntrOtpErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

IntrOtpOperationDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

LcOtpProgramRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

LcSeedHwRdEnStable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	2200	0	0
T5	67882	9	0	0
T12	17367	2	0	0
T13	51488	7	0	0
T31	0	8	0	0
T52	0	6	0	0
T63	36605	2	0	0
T102	19569	0	0	0
T103	11685	0	0	0
T104	16521	0	0	0
T105	13652	0	0	0
T106	24703	2	0	0
T107	18845	0	0	0
T113	0	1	0	0
T114	0	2	0	0
T115	0	1	0	0

LcSeedHwRdEnStable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	2200	0	0
T5	67882	9	0	0
T12	17367	2	0	0
T13	51488	7	0	0
T31	0	8	0	0
T52	0	6	0	0
T63	36605	2	0	0
T102	19569	0	0	0
T103	11685	0	0	0
T104	16521	0	0	0
T105	13652	0	0	0
T106	24703	2	0	0
T107	18845	0	0	0
T113	0	1	0	0
T114	0	2	0	0
T115	0	1	0	0

LcSeedHwRdEnStable2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	0	0	0

LcSeedHwRdEnStable3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	0	0	0

LcStateSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123	1123	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

LcTransitionCntSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123	1123	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAstPwrSeqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

OtpBroadcastKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

OtpErrorCode0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123	1123	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpErrorCode1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123	1123	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpErrorCode2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123	1123	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpErrorCode3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123	1123	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpErrorCode4_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123	1123	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpIfWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123	1123	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpKeymgrKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

OtpLcDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

OtpOtgnKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

OtpRespFifoUnderflow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1245821	0	0
T1	80703	1566	0	0
T2	21112	169	0	0
T3	14351	113	0	0
T4	39226	633	0	0
T5	67882	1018	0	0
T9	16233	245	0	0
T10	10549	116	0	0
T11	12064	154	0	0
T12	17367	285	0	0
T13	51488	925	0	0

OtpSramKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

PartSelMustBeOnehot_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

PrimTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

PwrOtpInitRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

RmaTokenSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123	1123	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

SramDataKeySeedSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123	1123	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TestExitTokenSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123	1123	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TestUnlockTokenSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123	1123	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

gen_partitions[0].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

gen_partitions[10].gen_lifecycle.FpvSecCmCntPartLcCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

gen_partitions[10].gen_lifecycle.FpvSecCmCtrlPartLcFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

gen_partitions[1].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

gen_partitions[2].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

gen_partitions[3].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

gen_partitions[4].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

gen_partitions[5].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

gen_partitions[5].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

gen_partitions[6].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

gen_partitions[6].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

gen_partitions[7].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

gen_partitions[7].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

gen_partitions[8].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

gen_partitions[8].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

gen_partitions[9].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

gen_partitions[9].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

gen_reg_we_assert_generic.FpvSecCmPrimFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		154	151	98.05
CONT_ASSIGN	246	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
ALWAYS	279	13	13	100.00
ALWAYS	303	3	3	100.00
ALWAYS	319	10	10	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	381	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	389	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	399	1	1	100.00
ALWAYS	402	5	5	100.00
ALWAYS	429	19	19	100.00
CONT_ASSIGN	483	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
ALWAYS	494	9	9	100.00
ALWAYS	516	10	10	100.00
CONT_ASSIGN	580	1	1	100.00
CONT_ASSIGN	588	1	1	100.00
CONT_ASSIGN	635	1	1	100.00
CONT_ASSIGN	637	1	1	100.00
CONT_ASSIGN	760	1	1	100.00
CONT_ASSIGN	761	1	1	100.00
CONT_ASSIGN	762	1	1	100.00
CONT_ASSIGN	792	1	1	100.00
CONT_ASSIGN	794	1	1	100.00
ALWAYS	871	2	2	100.00
ALWAYS	929	2	2	100.00
ALWAYS	956	4	4	100.00
CONT_ASSIGN	983	1	1	100.00
ALWAYS	986	3	3	100.00
CONT_ASSIGN	1038	1	1	100.00
CONT_ASSIGN	1040	1	1	100.00
CONT_ASSIGN	1074	1	0	0.00
CONT_ASSIGN	1125	1	0	0.00
CONT_ASSIGN	1180	1	1	100.00
CONT_ASSIGN	1180	1	1	100.00
CONT_ASSIGN	1180	1	1	100.00
CONT_ASSIGN	1180	1	1	100.00
CONT_ASSIGN	1180	1	1	100.00
CONT_ASSIGN	1235	1	1	100.00
CONT_ASSIGN	1235	1	1	100.00
CONT_ASSIGN	1235	1	1	100.00
CONT_ASSIGN	1235	1	1	100.00
CONT_ASSIGN	1235	1	1	100.00
CONT_ASSIGN	1295	1	1	100.00
CONT_ASSIGN	1307	1	0	0.00
CONT_ASSIGN	1331	1	1	100.00
ALWAYS	1343	2	2	100.00
CONT_ASSIGN	1357	1	1	100.00
ALWAYS	1385	9	9	100.00
CONT_ASSIGN	1416	1	1	100.00
CONT_ASSIGN	1417	1	1	100.00
CONT_ASSIGN	1419	1	1	100.00
CONT_ASSIGN	1421	1	1	100.00
CONT_ASSIGN	1425	1	1	100.00
CONT_ASSIGN	1427	1	1	100.00
CONT_ASSIGN	1429	1	1	100.00
CONT_ASSIGN	1434	1	1	100.00
CONT_ASSIGN	1436	1	1	100.00
CONT_ASSIGN	1438	1	1	100.00
CONT_ASSIGN	1470	1	1	100.00
CONT_ASSIGN	1472	1	1	100.00
CONT_ASSIGN	1476	1	1	100.00
CONT_ASSIGN	1480	1	1	100.00
CONT_ASSIGN	1484	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
246	1	1
248	10	10
279	1	1
280	1	1
281	1	1
282	1	1
283	1	1
284	1	1
287		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
292	1	1
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
303	1	1
304	1	1
306	1	1
319	1	1
324	1	1
325	1	1
329	1	1
330	1	1
331	1	1
332	1	1
			MISSING_ELSE
			MISSING_ELSE
336	1	1
337	1	1
338	1	1
339		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
			MISSING_ELSE
377	1	1
381	1	1
385	1	1
389	1	1
390	1	1
398	1	1
399	1	1
402	1	1
403	1	1
405	1	1
407	1	1
408	1	1
429	1	1
430	1	1
431	1	1
433	1	1
435	1	1
438	1	1
440	1	1
443	1	1
444	1	1
			MISSING_ELSE
448	1	1
450	1	1
454	1	1
457	1	1
459	1	1
464	1	1
465	1	1
			MISSING_ELSE
467	1	1
468	1	1
			MISSING_ELSE
473	1	1
483	1	1
491	1	1
494	1	1
495	1	1
496	1	1
497	1	1
498	1	1
500	1	1
501	1	1
502	1	1
503	1	1
516	1	1
518	1	1
520	1	1
522	1	1
524	1	1
533	1	1
535	1	1
536	1	1
537	1	1
538	1	1
580	1	1
588	1	1
635	1	1
637	1	1
760	1	1
761	1	1
762	1	1
792	1	1
794	1	1
871	1	1
872	1	1
929	1	1
930	1	1
956	1	1
957	1	1
958	1	1
959	1	1
983	1	1
986	1	1
987	1	1
989	1	1
1038	1	1
1040	1	1
1074	0	1
1125	0	1
1180	5	5
1235	5	5
1295	1	1
1307	0	1
1331	1	1
1343	1	1
1344	1	1
1357	1	1
1385	1	1
1386	1	1
1387	1	1
1388	1	1
1390	1	1
1391	1	1
1392	1	1
1393	1	1
1394	1	1
1416	1	1
1417	1	1
1419	1	1
1421	1	1
1425	1	1
1427	1	1
1429	1	1
1434	1	1
1436	1	1
1438	1	1
1470	1	1
1472	1	1
1476	1	1
1480	1	1
1484	1	1

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	104	100	96.15
Logical	104	100	96.15
Non-Logical	0	0
Event	0	0

 LINE       248
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b00001000000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[1].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T9,T10

 LINE       248
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b00111101000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[2].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       248
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b10001111000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[3].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       248
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11001010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[4].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T14
1	1	Covered	T1,T3,T4

 LINE       248
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11001111000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[5].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T14
1	1	Covered	T7,T8,T14

 LINE       248
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011000000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[6].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T14
1	1	Covered	T7,T8,T14

 LINE       248
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[7].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T14
1	1	Covered	T7,T8,T14

 LINE       248
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011111000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[8].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T14
1	1	Covered	T7,T8,T14

 LINE       248
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11101010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[9].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T14
1	1	Covered	T7,T8,T14

 LINE       248
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11110101000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[10].PartEnd))
             -------------------1------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		vcs_gen_start:k=10:vcs_gen_end:VC_COV_UNR
1	1	Covered	T7,T8,T14

 LINE       283
 EXPRESSION (tlul_part_sel_oh != '0)
            ------------1-----------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Covered	T1,T2,T3

 LINE       292
 EXPRESSION (((|part_tlul_gnt)) | tlul_oob_err_q)
             ---------1--------   -------2------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Covered	T1,T2,T3
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T2,T3

 LINE       293
 EXPRESSION (((|part_tlul_rvalid)) | tlul_oob_err_q)
             ----------1----------   -------2------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Covered	T1,T2,T3
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T2,T3

 LINE       377
 EXPRESSION ((reg2hw.direct_access_regwen.qe && ((!reg2hw.direct_access_regwen.q))) ? 1'b0 : direct_access_regwen_q)
             -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       377
 SUB-EXPRESSION (reg2hw.direct_access_regwen.qe && ((!reg2hw.direct_access_regwen.q)))
                 ---------------1--------------    -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       381
 EXPRESSION (reg2hw.direct_access_cmd.digest.qe | reg2hw.direct_access_cmd.wr.qe | reg2hw.direct_access_cmd.rd.qe)
             -----------------1----------------   ---------------2--------------   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	0	0	Covered	T1,T2,T3
0	0	1	Excluded		VC_COV_UNR
0	1	0	Excluded		VC_COV_UNR
1	0	0	Excluded		VC_COV_UNR

 LINE       398
 EXPRESSION (lci_prog_idle & dai_prog_idle)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       431
 EXPRESSION (fatal_bus_integ_error_q | ((|intg_error)))
             -----------1-----------   -------2-------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Covered	T1,T2,T3
0	1	Covered	T24,T25,T26
1	0	Excluded		VC_COV_UNR

 LINE       440
 EXPRESSION (part_error[k] == MacroError)
            --------------1--------------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       444
 EXPRESSION (part_error[k] == MacroEccUncorrError)
            -------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T10,T104

 LINE       464
 EXPRESSION (fatal_macro_error_q || fatal_check_error_q)
             ---------1---------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T9
1	0	Covered	T1,T10,T104

 LINE       473
 EXPRESSION (chk_timeout | lfsr_fsm_err | scrmbl_fsm_err | ((|part_fsm_err)))
             -----1-----   ------2-----   -------3------   --------4--------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T1,T9,T10
0	0	1	0	Covered	T24,T25,T26
0	1	0	0	Covered	T24,T25,T26
1	0	0	0	Covered	T5,T52,T55

 LINE       522
 EXPRESSION (direct_access_regwen_q & dai_idle)
             -----------1----------   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       588
 SUB-EXPRESSION (reg2hw.alert_test.recov_prim_otp_alert.q & reg2hw.alert_test.recov_prim_otp_alert.qe)
                 --------------------1-------------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T244,T245,T246
1	0	Covered	T1,T2,T3
1	1	Covered	T244,T245,T246

 LINE       588
 SUB-EXPRESSION (reg2hw.alert_test.fatal_prim_otp_alert.q & reg2hw.alert_test.fatal_prim_otp_alert.qe)
                 --------------------1-------------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T244,T245,T246
1	0	Covered	T1,T2,T3
1	1	Covered	T244,T245,T246

 LINE       588
 SUB-EXPRESSION (reg2hw.alert_test.fatal_bus_integ_error.q & reg2hw.alert_test.fatal_bus_integ_error.qe)
                 --------------------1--------------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T244,T245,T246
1	0	Covered	T1,T2,T3
1	1	Covered	T244,T245,T246

 LINE       588
 SUB-EXPRESSION (reg2hw.alert_test.fatal_check_error.q & reg2hw.alert_test.fatal_check_error.qe)
                 ------------------1------------------   -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T244,T245,T246
1	0	Covered	T1,T2,T3
1	1	Covered	T244,T245,T246

 LINE       588
 SUB-EXPRESSION (reg2hw.alert_test.fatal_macro_error.q & reg2hw.alert_test.fatal_macro_error.qe)
                 ------------------1------------------   -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T244,T245,T246
1	0	Covered	T1,T2,T3
1	1	Covered	T244,T245,T246

 LINE       635
 EXPRESSION (reg2hw.check_trigger.integrity.q & reg2hw.check_trigger.integrity.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       637
 EXPRESSION (reg2hw.check_trigger.consistency.q & reg2hw.check_trigger.consistency.qe)
             -----------------1----------------   -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       760
 EXPRESSION (otp_prim_ready & otp_rsp_fifo_ready)
             -------1------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       761
 EXPRESSION (otp_arb_valid & otp_rsp_fifo_ready)
             ------1------   ---------2--------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       762
 EXPRESSION (otp_prim_ready & otp_prim_valid)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       872
 EXPRESSION (otp_rvalid & otp_fifo_valid)
             -----1----   -------2------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       1416
 EXPRESSION (part_digest[Secret1Idx] != '0)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T12

 LINE       1434
 EXPRESSION ((part_digest[Secret0Idx] != '0) ? On : Off)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T11,T12

 LINE       1434
 SUB-EXPRESSION (part_digest[Secret0Idx] != '0)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T11,T12

 LINE       1436
 EXPRESSION ((part_digest[Secret2Idx] != '0) ? On : Off)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T5,T13

 LINE       1436
 SUB-EXPRESSION (part_digest[Secret2Idx] != '0)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T5,T13

 LINE       1438
 EXPRESSION ((part_digest[Secret2Idx] != '0) ? On : Off)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T5,T13

 LINE       1438
 SUB-EXPRESSION (part_digest[Secret2Idx] != '0)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T5,T13

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	148	141	95.27
Total Bits	9984	9676	96.92
Total Bits 0->1	4992	4838	96.92
Total Bits 1->0	4992	4838	96.92

Ports	148	141	95.27
Port Bits	9984	9676	96.92
Port Bits 0->1	4992	4838	96.92
Port Bits 1->0	4992	4838	96.92

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_o.edn_req	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
edn_i.edn_fips	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
edn_i.edn_ack	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
core_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_user.instr_type[3:0]	Yes	Yes	T3,T13,T104	Yes	T3,T13,T104	INPUT
core_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
core_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
core_tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_source[7:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
core_tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
prim_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
prim_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
prim_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
prim_tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T10,T11	Yes	T1,T10,T11	INPUT
prim_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
prim_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
prim_tl_i.a_mask[3:0]	Yes	Yes	T1,T11,T103	Yes	T1,T10,T11	INPUT
prim_tl_i.a_address[31:0]	Yes	Yes	T1,T10,T11	Yes	T1,T10,T11	INPUT
prim_tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
prim_tl_i.a_size[1:0]	Yes	Yes	T1,T10,T11	Yes	T1,T11,T103	INPUT
prim_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
prim_tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
prim_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
prim_tl_o.a_ready	Yes	Yes	T13,T103,T63	Yes	T13,T103,T63	OUTPUT
prim_tl_o.d_error	Yes	Yes	T13,T24,T31	Yes	T13,T24,T31	OUTPUT
prim_tl_o.d_user.data_intg[6:0]	Yes	Yes	T13,T31,T62	Yes	T13,T31,T62	OUTPUT
prim_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
prim_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_data[31:0]	Yes	Yes	T13,T24,T31	Yes	T13,T24,T31	OUTPUT
prim_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
prim_tl_o.d_size[1:0]	Yes	Yes	T7,T8,T14	Yes	T7,T8,T14	OUTPUT
prim_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
prim_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
intr_otp_operation_done_o	Yes	Yes	T1,T4,T9	Yes	T1,T4,T9	OUTPUT
intr_otp_error_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T10,T104	Yes	T1,T10,T104	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T24,T25,T244	Yes	T24,T25,T244	INPUT
alert_rx_i[2].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[3].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T24,T25,T244	Yes	T24,T25,T244	INPUT
alert_rx_i[3].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[3].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[4].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[4].ack_p	Yes	Yes	T244,T245,T246	Yes	T244,T245,T246	INPUT
alert_rx_i[4].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[4].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T10,T104	Yes	T1,T10,T104	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T24,T25,T244	Yes	T24,T25,T244	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T24,T25,T244	Yes	T24,T25,T244	OUTPUT
alert_tx_o[4].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[4].alert_p	Yes	Yes	T244,T245,T246	Yes	T244,T245,T246	OUTPUT
obs_ctrl_i.obmen[3:0]	No	No		No		INPUT
obs_ctrl_i.obmsl[3:0]	No	No		No		INPUT
obs_ctrl_i.obgsl[3:0]	No	No		No		INPUT
otp_obs_o[7:0]	Unreachable	Unreachable		Unreachable		OUTPUT
otp_ast_pwr_seq_o.pwr_seq[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
otp_ast_pwr_seq_h_i.pwr_seq_h[1:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T10	INPUT
pwr_otp_i.otp_init	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwr_otp_o.otp_idle	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwr_otp_o.otp_done	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
lc_otp_vendor_test_i.ctrl[31:0]	No	No		No		INPUT
lc_otp_vendor_test_o.status[31:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
lc_otp_program_i.count[383:0]	Yes	Yes	T96,T7,T247	Yes	T96,T248,T219	INPUT
lc_otp_program_i.state[319:0]	Yes	Yes	T96,T7,T177	Yes	T96,T7,T177	INPUT
lc_otp_program_i.req	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
lc_otp_program_o.ack	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
lc_otp_program_o.err	Yes	Yes	T6,T96,T249	Yes	T6,T96,T249	OUTPUT
lc_creator_seed_sw_rw_en_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T4	INPUT
lc_owner_seed_sw_rw_en_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T4	INPUT
lc_seed_hw_rd_en_i[3:0]	Yes	Yes	T1,T4,T9	Yes	T1,T2,T4	INPUT
lc_dft_en_i[3:0]	Yes	Yes	T2,T9,T5	Yes	T2,T3,T11	INPUT
lc_escalate_en_i[3:0]	Yes	Yes	T3,T12,T103	Yes	T3,T12,T103	INPUT
lc_check_byp_en_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
otp_lc_data_o.rma_token[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.rma_token_valid[3:0]	Yes	Yes	T12,T5,T13	Yes	T12,T5,T13	OUTPUT
otp_lc_data_o.test_exit_token[127:0]	Yes	Yes	T11,T102,T107	Yes	T102,T114,T55	OUTPUT
otp_lc_data_o.test_unlock_token[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.test_tokens_valid[3:0]	Yes	Yes	T4,T12,T5	Yes	T4,T11,T12	OUTPUT
otp_lc_data_o.secrets_valid[3:0]	Yes	Yes	T12,T5,T13	Yes	T12,T5,T13	OUTPUT
otp_lc_data_o.count[0]	No	No		No		OUTPUT
otp_lc_data_o.count[8:1]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[9]	No	No		No		OUTPUT
otp_lc_data_o.count[10]	Yes	Yes	*T1,*T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[11]	No	No		No		OUTPUT
otp_lc_data_o.count[14:12]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[16:15]	No	No		No		OUTPUT
otp_lc_data_o.count[28:17]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[30:29]	No	No		No		OUTPUT
otp_lc_data_o.count[31]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[32]	No	No		No		OUTPUT
otp_lc_data_o.count[41:33]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[42]	No	No		No		OUTPUT
otp_lc_data_o.count[51:43]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[52]	No	No		No		OUTPUT
otp_lc_data_o.count[63:53]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[65:64]	No	No		No		OUTPUT
otp_lc_data_o.count[76:66]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[77]	No	No		No		OUTPUT
otp_lc_data_o.count[85:78]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[86]	No	No		No		OUTPUT
otp_lc_data_o.count[100:87]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[101]	No	No		No		OUTPUT
otp_lc_data_o.count[121:102]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[122]	No	No		No		OUTPUT
otp_lc_data_o.count[124:123]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[125]	No	No		No		OUTPUT
otp_lc_data_o.count[137:126]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[138]	No	No		No		OUTPUT
otp_lc_data_o.count[150:139]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[151]	No	No		No		OUTPUT
otp_lc_data_o.count[155:152]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[156]	No	No		No		OUTPUT
otp_lc_data_o.count[158:157]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[160:159]	No	No		No		OUTPUT
otp_lc_data_o.count[165:161]	Yes	Yes	T1,T4,*T102	Yes	T1,T4,T102	OUTPUT
otp_lc_data_o.count[166]	No	No		No		OUTPUT
otp_lc_data_o.count[174:167]	Yes	Yes	T1,T4,*T102	Yes	T1,T4,T102	OUTPUT
otp_lc_data_o.count[175]	No	No		No		OUTPUT
otp_lc_data_o.count[185:176]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[186]	No	No		No		OUTPUT
otp_lc_data_o.count[191:187]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[192]	No	No		No		OUTPUT
otp_lc_data_o.count[193]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[194]	No	No		No		OUTPUT
otp_lc_data_o.count[198:195]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[199]	No	No		No		OUTPUT
otp_lc_data_o.count[217:200]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[218]	No	No		No		OUTPUT
otp_lc_data_o.count[225:219]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[227:226]	No	No		No		OUTPUT
otp_lc_data_o.count[228]	Yes	Yes	*T1,*T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[229]	No	No		No		OUTPUT
otp_lc_data_o.count[232:230]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[233]	No	No		No		OUTPUT
otp_lc_data_o.count[237:234]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[238]	No	No		No		OUTPUT
otp_lc_data_o.count[240:239]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[241]	No	No		No		OUTPUT
otp_lc_data_o.count[251:242]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[252]	No	No		No		OUTPUT
otp_lc_data_o.count[265:253]	Yes	Yes	T1,*T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[266]	No	No		No		OUTPUT
otp_lc_data_o.count[269:267]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[270]	No	No		No		OUTPUT
otp_lc_data_o.count[274:271]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[275]	No	No		No		OUTPUT
otp_lc_data_o.count[301:276]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[304:302]	No	No		No		OUTPUT
otp_lc_data_o.count[309:305]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[310]	No	No		No		OUTPUT
otp_lc_data_o.count[316:311]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[317]	No	No		No		OUTPUT
otp_lc_data_o.count[330:318]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[331]	No	No		No		OUTPUT
otp_lc_data_o.count[333:332]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[334]	No	No		No		OUTPUT
otp_lc_data_o.count[335]	Yes	Yes	*T1,*T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[337:336]	No	No		No		OUTPUT
otp_lc_data_o.count[343:338]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[344]	No	No		No		OUTPUT
otp_lc_data_o.count[365:345]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.count[367:366]	No	No		No		OUTPUT
otp_lc_data_o.count[371:368]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[372]	No	No		No		OUTPUT
otp_lc_data_o.count[383:373]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[12:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[13]	No	No		No		OUTPUT
otp_lc_data_o.state[15:14]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[16]	No	No		No		OUTPUT
otp_lc_data_o.state[17]	Yes	Yes	*T1,*T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[20:18]	No	No		No		OUTPUT
otp_lc_data_o.state[34:21]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[35]	No	No		No		OUTPUT
otp_lc_data_o.state[36]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[37]	No	No		No		OUTPUT
otp_lc_data_o.state[47:38]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[48]	No	No		No		OUTPUT
otp_lc_data_o.state[50:49]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[52:51]	No	No		No		OUTPUT
otp_lc_data_o.state[65:53]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[66]	No	No		No		OUTPUT
otp_lc_data_o.state[73:67]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[74]	No	No		No		OUTPUT
otp_lc_data_o.state[77:75]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[78]	No	No		No		OUTPUT
otp_lc_data_o.state[83:79]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[85:84]	No	No		No		OUTPUT
otp_lc_data_o.state[87:86]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[88]	No	No		No		OUTPUT
otp_lc_data_o.state[95:89]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[96]	No	No		No		OUTPUT
otp_lc_data_o.state[98:97]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[99]	No	No		No		OUTPUT
otp_lc_data_o.state[101:100]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[102]	No	No		No		OUTPUT
otp_lc_data_o.state[103]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[104]	No	No		No		OUTPUT
otp_lc_data_o.state[113:105]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[115:114]	No	No		No		OUTPUT
otp_lc_data_o.state[121:116]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[122]	No	No		No		OUTPUT
otp_lc_data_o.state[123]	Yes	Yes	*T1,*T4,*T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[124]	No	No		No		OUTPUT
otp_lc_data_o.state[126:125]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[127]	No	No		No		OUTPUT
otp_lc_data_o.state[134:128]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[135]	No	No		No		OUTPUT
otp_lc_data_o.state[136]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[137]	No	No		No		OUTPUT
otp_lc_data_o.state[141:138]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[142]	No	No		No		OUTPUT
otp_lc_data_o.state[146:143]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[147]	No	No		No		OUTPUT
otp_lc_data_o.state[149:148]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[150]	No	No		No		OUTPUT
otp_lc_data_o.state[152:151]	Yes	Yes	T1,T5,T13	Yes	T1,T5,T13	OUTPUT
otp_lc_data_o.state[154:153]	No	No		No		OUTPUT
otp_lc_data_o.state[156:155]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[157]	No	No		No		OUTPUT
otp_lc_data_o.state[160:158]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[161]	No	No		No		OUTPUT
otp_lc_data_o.state[163:162]	Yes	Yes	T1,*T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[164]	No	No		No		OUTPUT
otp_lc_data_o.state[177:165]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[178]	No	No		No		OUTPUT
otp_lc_data_o.state[181:179]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[184:182]	No	No		No		OUTPUT
otp_lc_data_o.state[186:185]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[187]	No	No		No		OUTPUT
otp_lc_data_o.state[198:188]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[199]	No	No		No		OUTPUT
otp_lc_data_o.state[210:200]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[211]	No	No		No		OUTPUT
otp_lc_data_o.state[215:212]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[216]	No	No		No		OUTPUT
otp_lc_data_o.state[226:217]	Yes	Yes	T1,*T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[227]	No	No		No		OUTPUT
otp_lc_data_o.state[230:228]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[231]	No	No		No		OUTPUT
otp_lc_data_o.state[234:232]	Yes	Yes	T1,T5,T13	Yes	T1,T5,T13	OUTPUT
otp_lc_data_o.state[235]	No	No		No		OUTPUT
otp_lc_data_o.state[236]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[237]	No	No		No		OUTPUT
otp_lc_data_o.state[239:238]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[240]	No	No		No		OUTPUT
otp_lc_data_o.state[260:241]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[261]	No	No		No		OUTPUT
otp_lc_data_o.state[263:262]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[264]	No	No		No		OUTPUT
otp_lc_data_o.state[268:265]	Yes	Yes	T1,*T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[269]	No	No		No		OUTPUT
otp_lc_data_o.state[273:270]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[274]	No	No		No		OUTPUT
otp_lc_data_o.state[278:275]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[280:279]	No	No		No		OUTPUT
otp_lc_data_o.state[285:281]	Yes	Yes	T1,T5,T13	Yes	T1,T5,T13	OUTPUT
otp_lc_data_o.state[286]	No	No		No		OUTPUT
otp_lc_data_o.state[301:287]	Yes	Yes	T1,*T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[302]	No	No		No		OUTPUT
otp_lc_data_o.state[306:303]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otp_lc_data_o.state[307]	No	No		No		OUTPUT
otp_lc_data_o.state[319:308]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_keymgr_key_o.owner_seed_valid	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
otp_keymgr_key_o.owner_seed[255:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
otp_keymgr_key_o.creator_seed_valid	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
otp_keymgr_key_o.creator_seed[255:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
otp_keymgr_key_o.creator_root_key_share1_valid	Yes	Yes	T12,T5,T13	Yes	T12,T5,T13	OUTPUT
otp_keymgr_key_o.creator_root_key_share1[255:0]	Yes	Yes	T1,T2,T4	Yes	T1,T9,T12	OUTPUT
otp_keymgr_key_o.creator_root_key_share0_valid	Yes	Yes	T12,T5,T13	Yes	T12,T5,T13	OUTPUT
otp_keymgr_key_o.creator_root_key_share0[255:0]	Yes	Yes	T5,T31,T97	Yes	T5,T31,T97	OUTPUT
flash_otp_key_i.addr_req	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
flash_otp_key_i.data_req	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
flash_otp_key_o.seed_valid	Yes	Yes	T4,T5,T13	Yes	T4,T5,T13	OUTPUT
flash_otp_key_o.rand_key[127:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
flash_otp_key_o.key[127:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
flash_otp_key_o.addr_ack	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
flash_otp_key_o.data_ack	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
sram_otp_key_i[0].req	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
sram_otp_key_i[1].req	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
sram_otp_key_i[2].req	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
sram_otp_key_i[3].req	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
sram_otp_key_o[0].seed_valid	Yes	Yes	T4,T5,T13	Yes	T4,T5,T13	OUTPUT
sram_otp_key_o[0].nonce[127:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
sram_otp_key_o[0].key[127:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
sram_otp_key_o[0].ack	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
sram_otp_key_o[1].seed_valid	Yes	Yes	T4,T5,T13	Yes	T4,T5,T13	OUTPUT
sram_otp_key_o[1].nonce[127:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
sram_otp_key_o[1].key[127:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
sram_otp_key_o[1].ack	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
sram_otp_key_o[2].seed_valid	Yes	Yes	T4,T5,T13	Yes	T4,T5,T13	OUTPUT
sram_otp_key_o[2].nonce[127:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
sram_otp_key_o[2].key[127:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
sram_otp_key_o[2].ack	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
sram_otp_key_o[3].seed_valid	Yes	Yes	T4,T5,T13	Yes	T4,T5,T13	OUTPUT
sram_otp_key_o[3].nonce[127:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
sram_otp_key_o[3].key[127:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
sram_otp_key_o[3].ack	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otbn_otp_key_i.req	Yes	Yes	T1,T4,T11	Yes	T1,T4,T11	INPUT
otbn_otp_key_o.seed_valid	Yes	Yes	T4,T5,T13	Yes	T4,T5,T13	OUTPUT
otbn_otp_key_o.nonce[63:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otbn_otp_key_o.key[127:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
otbn_otp_key_o.ack	Yes	Yes	T1,T5,T13	Yes	T1,T5,T13	OUTPUT
otp_broadcast_o.hw_cfg0_data.device_id[255:0]	Yes	Yes	T114,T96,T90	Yes	T114,T96,T90	OUTPUT
otp_broadcast_o.hw_cfg0_data.manuf_state[255:0]	Yes	Yes	T96,T90,T99	Yes	T96,T90,T99	OUTPUT
otp_broadcast_o.hw_cfg0_data.hw_cfg0_digest[63:0]	Yes	Yes	T102,T55,T62	Yes	T102,T105,T55	OUTPUT
otp_broadcast_o.hw_cfg1_data.en_sram_ifetch[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_broadcast_o.hw_cfg1_data.en_csrng_sw_app_read[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_broadcast_o.hw_cfg1_data.unallocated[47:0]	Yes	Yes	T114,T31,T55	Yes	T3,T107,T114	OUTPUT
otp_broadcast_o.hw_cfg1_data.hw_cfg1_digest[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_broadcast_o.valid[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_ext_voltage_h_io	No	No		No		INOUT
scan_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T4,T9	INPUT
scan_rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T4,T10	INPUT
scanmode_i[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T9	INPUT
cio_test_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
cio_test_en_o[7:0]	Yes	Yes	T13,T24,T31	Yes	T13,T24,T31	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
Branches		28	27	96.43
TERNARY	377	2	1	50.00
TERNARY	1434	2	2	100.00
TERNARY	1436	2	2	100.00
TERNARY	1438	2	2	100.00
IF	282	2	2	100.00
IF	303	2	2	100.00
IF	329	2	2	100.00
IF	336	2	2	100.00
IF	402	2	2	100.00
IF	443	2	2	100.00
IF	464	2	2	100.00
IF	467	2	2	100.00
IF	494	2	2	100.00
IF	986	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	377	((reg2hw.direct_access_regwen.qe && (!reg2hw.direct_access_regwen.q))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1434	((part_digest[Secret0Idx] != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1436	((part_digest[Secret2Idx] != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T5,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1438	((part_digest[Secret2Idx] != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T5,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	282	if (tlul_req)
-2-:	283	if ((tlul_part_sel_oh != '0))

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	303	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	329	if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_creator_seed_sw_rw_en))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	336	if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_owner_seed_sw_rw_en))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	402	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	443	if (otp_ctrl_part_pkg::PartInfo[k].integrity)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((fatal_macro_error_q || fatal_check_error_q))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	467	if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_escalate_en[k]))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	494	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	986	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	71	71	100.00	69	97.18
Cover properties	0	0		0
Cover sequences	0	0		0
Total	71	71	100.00	69	97.18

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnown_A	1451411390	1450559481	0	0
CoreTlOutKnown_A	1451411390	1450559481	0	0
CreatorRootKeyShare0Size_A	1123	1123	0	0
CreatorRootKeyShare1Size_A	1123	1123	0	0
ErrorCodeWidth_A	1123	1123	0	0
FlashAddrKeySeedSize_A	1123	1123	0	0
FlashDataKeySeedSize_A	1123	1123	0	0
FlashOtpKeyRspKnown_A	1451411390	1450559481	0	0
FpvSecCmCntCnstyCheck_A	1451411390	50	0	0
FpvSecCmCntDaiCheck_A	1451411390	50	0	0
FpvSecCmCntIntegCheck_A	1451411390	50	0	0
FpvSecCmCntKdiEntropyCheck_A	1451411390	50	0	0
FpvSecCmCntKdiSeedCheck_A	1451411390	50	0	0
FpvSecCmCntLciCheck_A	1451411390	50	0	0
FpvSecCmCntScrmblCheck_A	1451411390	50	0	0
FpvSecCmCtrlDaiFsmCheck_A	1451411390	50	0	0
FpvSecCmCtrlKdiFsmCheck_A	1451411390	50	0	0
FpvSecCmCtrlLciFsmCheck_A	1451411390	50	0	0
FpvSecCmCtrlLfsrTimerFsmCheck_A	1451411390	50	0	0
FpvSecCmCtrlScrambleFsmCheck_A	1451411390	50	0	0
FpvSecCmDoubleLfsrCheck_A	1451411390	50	0	0
FpvSecCmRegWeOnehotCheck_A	1451411390	50	0	0
FpvSecCmTlLcGateFsm_A	1451411390	50	0	0
IntrOtpErrorKnown_A	1451411390	1450559481	0	0
IntrOtpOperationDoneKnown_A	1451411390	1450559481	0	0
LcOtpProgramRspKnown_A	1451411390	1450559481	0	0
LcSeedHwRdEnStable0_A	1451411390	2200	0	0
LcSeedHwRdEnStable1_A	1451411390	2200	0	0
LcSeedHwRdEnStable2_A	1451411390	0	0	0
LcSeedHwRdEnStable3_A	1451411390	0	0	0
LcStateSize_A	1123	1123	0	0
LcTransitionCntSize_A	1123	1123	0	0
OtpAstPwrSeqKnown_A	1451411390	1450559481	0	0
OtpBroadcastKnown_A	1451411390	1450559481	0	0
OtpErrorCode0_A	1123	1123	0	0
OtpErrorCode1_A	1123	1123	0	0
OtpErrorCode2_A	1123	1123	0	0
OtpErrorCode3_A	1123	1123	0	0
OtpErrorCode4_A	1123	1123	0	0
OtpIfWidth_A	1123	1123	0	0
OtpKeymgrKeyKnown_A	1451411390	1450559481	0	0
OtpLcDataKnown_A	1451411390	1450559481	0	0
OtpOtgnKeyKnown_A	1451411390	1450559481	0	0
OtpRespFifoUnderflow_A	1451411390	1245821	0	0
OtpSramKeyKnown_A	1451411390	1450559481	0	0
PartSelMustBeOnehot_A	1451411390	1450559481	0	0
PrimTlOutKnown_A	1451411390	1450559481	0	0
PwrOtpInitRspKnown_A	1451411390	1450559481	0	0
RmaTokenSize_A	1123	1123	0	0
SramDataKeySeedSize_A	1123	1123	0	0
TestExitTokenSize_A	1123	1123	0	0
TestUnlockTokenSize_A	1123	1123	0	0
gen_partitions[0].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	1451411390	50	0	0
gen_partitions[10].gen_lifecycle.FpvSecCmCntPartLcCheck_A	1451411390	50	0	0
gen_partitions[10].gen_lifecycle.FpvSecCmCtrlPartLcFsmCheck_A	1451411390	50	0	0
gen_partitions[1].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	1451411390	50	0	0
gen_partitions[2].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	1451411390	50	0	0
gen_partitions[3].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	1451411390	50	0	0
gen_partitions[4].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	1451411390	50	0	0
gen_partitions[5].gen_buffered.FpvSecCmCntPartBufCheck_A	1451411390	50	0	0
gen_partitions[5].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	1451411390	50	0	0
gen_partitions[6].gen_buffered.FpvSecCmCntPartBufCheck_A	1451411390	50	0	0
gen_partitions[6].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	1451411390	50	0	0
gen_partitions[7].gen_buffered.FpvSecCmCntPartBufCheck_A	1451411390	50	0	0
gen_partitions[7].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	1451411390	50	0	0
gen_partitions[8].gen_buffered.FpvSecCmCntPartBufCheck_A	1451411390	50	0	0
gen_partitions[8].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	1451411390	50	0	0
gen_partitions[9].gen_buffered.FpvSecCmCntPartBufCheck_A	1451411390	50	0	0
gen_partitions[9].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	1451411390	50	0	0
gen_reg_we_assert_generic.FpvSecCmPrimFsmCheck_A	1451411390	50	0	0
gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A	1451411390	50	0	0

AlertTxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

CoreTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

CreatorRootKeyShare0Size_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123	1123	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

CreatorRootKeyShare1Size_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123	1123	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

ErrorCodeWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123	1123	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

FlashAddrKeySeedSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123	1123	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

FlashDataKeySeedSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123	1123	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

FlashOtpKeyRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

FpvSecCmCntCnstyCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

FpvSecCmCntDaiCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

FpvSecCmCntIntegCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

FpvSecCmCntKdiEntropyCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

FpvSecCmCntKdiSeedCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

FpvSecCmCntLciCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

FpvSecCmCntScrmblCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

FpvSecCmCtrlDaiFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

FpvSecCmCtrlKdiFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

FpvSecCmCtrlLciFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

FpvSecCmCtrlLfsrTimerFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

FpvSecCmCtrlScrambleFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

FpvSecCmDoubleLfsrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

FpvSecCmTlLcGateFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

IntrOtpErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

IntrOtpOperationDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

LcOtpProgramRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

LcSeedHwRdEnStable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	2200	0	0
T5	67882	9	0	0
T12	17367	2	0	0
T13	51488	7	0	0
T31	0	8	0	0
T52	0	6	0	0
T63	36605	2	0	0
T102	19569	0	0	0
T103	11685	0	0	0
T104	16521	0	0	0
T105	13652	0	0	0
T106	24703	2	0	0
T107	18845	0	0	0
T113	0	1	0	0
T114	0	2	0	0
T115	0	1	0	0

LcSeedHwRdEnStable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	2200	0	0
T5	67882	9	0	0
T12	17367	2	0	0
T13	51488	7	0	0
T31	0	8	0	0
T52	0	6	0	0
T63	36605	2	0	0
T102	19569	0	0	0
T103	11685	0	0	0
T104	16521	0	0	0
T105	13652	0	0	0
T106	24703	2	0	0
T107	18845	0	0	0
T113	0	1	0	0
T114	0	2	0	0
T115	0	1	0	0

LcSeedHwRdEnStable2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	0	0	0

LcSeedHwRdEnStable3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	0	0	0

LcStateSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123	1123	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

LcTransitionCntSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123	1123	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAstPwrSeqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

OtpBroadcastKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

OtpErrorCode0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123	1123	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpErrorCode1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123	1123	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpErrorCode2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123	1123	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpErrorCode3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123	1123	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpErrorCode4_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123	1123	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpIfWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123	1123	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpKeymgrKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

OtpLcDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

OtpOtgnKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

OtpRespFifoUnderflow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1245821	0	0
T1	80703	1566	0	0
T2	21112	169	0	0
T3	14351	113	0	0
T4	39226	633	0	0
T5	67882	1018	0	0
T9	16233	245	0	0
T10	10549	116	0	0
T11	12064	154	0	0
T12	17367	285	0	0
T13	51488	925	0	0

OtpSramKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

PartSelMustBeOnehot_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

PrimTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

PwrOtpInitRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

RmaTokenSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123	1123	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

SramDataKeySeedSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123	1123	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TestExitTokenSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123	1123	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TestUnlockTokenSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123	1123	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

gen_partitions[0].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

gen_partitions[10].gen_lifecycle.FpvSecCmCntPartLcCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

gen_partitions[10].gen_lifecycle.FpvSecCmCtrlPartLcFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

gen_partitions[1].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

gen_partitions[2].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

gen_partitions[3].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

gen_partitions[4].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

gen_partitions[5].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

gen_partitions[5].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

gen_partitions[6].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

gen_partitions[6].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

gen_partitions[7].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

gen_partitions[7].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

gen_partitions[8].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

gen_partitions[8].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

gen_partitions[9].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

gen_partitions[9].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

gen_reg_we_assert_generic.FpvSecCmPrimFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0

gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	50	0	0
T6	19084	0	0	0
T24	104056	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T61	19740	0	0	0
T113	21681	0	0	0
T114	28886	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	0	0	0
T250	0	10	0	0
T251	0	10	0	0