Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.95	98.05	96.15	96.92		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.95	98.05	96.15	96.92		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T66,T37,T43

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T4,T9,T12
1	Covered	T1,T52,T55

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T24,T25,T26

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T136,T137,T138
1	Covered	T136,T137,T138

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T9

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T4,T9

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b10001111000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T3,T4

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T4,T9
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T4,T9
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T11,T12

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T11,T12

---

FSM Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T3
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T4,T9
ReadWaitSt	252	Covered	T1,T4,T9
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T3,T9
IdleSt->ReadSt	236	Covered	T1,T4,T9
InitSt->ErrorSt	315	Covered	T2,T10,T11
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T141,T161,T162
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T4,T11,T12
ReadSt->ReadWaitSt	252	Covered	T1,T4,T9
ReadWaitSt->ErrorSt	276	Covered	T184,T185,T186
ReadWaitSt->IdleSt	270	Covered	T1,T4,T9
ResetSt->ErrorSt	315	Covered	T71,T72,T73
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T4,T11,T12
CheckFailError	317	Covered	T136,T137,T138
FsmStateError	289	Covered	T1,T2,T3
MacroEccCorrError	221	Covered	T1,T52,T55
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T107,T6,T7
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T4,T11,T12
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T136,T137,T138
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T2,T3
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T1,T66,T37
MacroEccCorrError->NoError	235	Covered	T52,T55,T95
NoError->AccessError	256	Covered	T4,T11,T12
NoError->CheckFailError	317	Covered	T136,T137,T138
NoError->FsmStateError	289	Covered	T1,T2,T3
NoError->MacroEccCorrError	221	Covered	T1,T52,T55

---

Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T9

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T9

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T66,T37,T43
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T161,T163,T187
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T4,T9
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T4,T9
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T97,T100,T128
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T4,T11,T12
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T1,T52,T55
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T4,T9,T12
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T184,T185,T186
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T4,T9
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T24,T25,T26
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T3,T11
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T3,T11
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T24,T25,T26

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T136,T137,T138
1	0	Covered	T136,T137,T138
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	1451411390	1450559481	0	0
DigestKnown_A	1451411390	1450559481	0	0
DigestOffsetMustBeRepresentable_A	1123	1123	0	0
EccErrorState_A	1451411390	8659	0	0
ErrorKnown_A	1451411390	1450559481	0	0
FsmStateKnown_A	1451411390	1450559481	0	0
InitDoneKnown_A	1451411390	1450559481	0	0
InitReadLocksPartition_A	1451411390	285847729	0	0
InitWriteLocksPartition_A	1451411390	285847729	0	0
OffsetMustBeBlockAligned_A	1123	1123	0	0
OtpAddrKnown_A	1451411390	1450559481	0	0
OtpCmdKnown_A	1451411390	1450559481	0	0
OtpErrorState_A	1451411390	43	0	0
OtpReqKnown_A	1451411390	1450559481	0	0
OtpSizeKnown_A	1451411390	1450559481	0	0
OtpWdataKnown_A	1451411390	1450559481	0	0
ReadLockPropagation_A	1451411390	643112612	0	0
SizeMustBeBlockAligned_A	1123	1123	0	0
TlulGntKnown_A	1451411390	1450559481	0	0
TlulRdataKnown_A	1451411390	1450559481	0	0
TlulReadOnReadLock_A	1451411390	7244	0	0
TlulRerrorKnown_A	1451411390	1450559481	0	0
TlulRvalidKnown_A	1451411390	1450559481	0	0
WriteLockPropagation_A	1451411390	2364558	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	1451411390	25071784	0	0
u_state_regs_A	1451411390	1450559481	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123	1123	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	8659	0	0
T79	34679	0	0	0
T136	11604	2368	0	0
T137	13197	3938	0	0
T138	0	2353	0	0
T154	14369	0	0	0
T155	13170	0	0	0
T156	6745	0	0	0
T157	21140	0	0	0
T158	46927	0	0	0
T159	48278	0	0	0
T160	82780	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	285847729	0	0
T1	80703	12750	0	0
T2	21112	13946	0	0
T3	14351	8202	0	0
T4	39226	6274	0	0
T5	67882	1601	0	0
T9	16233	5856	0	0
T10	10549	3256	0	0
T11	12064	4044	0	0
T12	17367	3940	0	0
T13	51488	1412	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	285847729	0	0
T1	80703	12750	0	0
T2	21112	13946	0	0
T3	14351	8202	0	0
T4	39226	6274	0	0
T5	67882	1601	0	0
T9	16233	5856	0	0
T10	10549	3256	0	0
T11	12064	4044	0	0
T12	17367	3940	0	0
T13	51488	1412	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123	1123	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	43	0	0
T6	19084	0	0	0
T31	118578	0	0	0
T52	131958	0	0	0
T55	41992	0	0	0
T61	19740	0	0	0
T65	15241	0	0	0
T115	35590	0	0	0
T145	156347	0	0	0
T161	8950	1	0	0
T163	0	1	0	0
T175	9634	0	0	0
T187	0	1	0	0
T188	0	1	0	0
T189	0	1	0	0
T190	0	1	0	0
T191	0	1	0	0
T192	0	1	0	0
T193	0	1	0	0
T194	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	643112612	0	0
T1	80703	1177	0	0
T2	21112	0	0	0
T3	14351	0	0	0
T4	39226	889	0	0
T5	67882	15369	0	0
T9	16233	0	0	0
T10	10549	0	0	0
T11	12064	1753	0	0
T12	17367	1890	0	0
T13	51488	3545	0	0
T31	0	53391	0	0
T52	0	21497	0	0
T105	0	2116	0	0
T107	0	10907	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123	1123	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	7244	0	0
T1	80703	8	0	0
T2	21112	0	0	0
T3	14351	3	0	0
T4	39226	1	0	0
T5	67882	9	0	0
T9	16233	0	0	0
T10	10549	0	0	0
T11	12064	2	0	0
T12	17367	5	0	0
T13	51488	0	0	0
T63	0	5	0	0
T105	0	4	0	0
T107	0	3	0	0
T109	0	4	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	2364558	0	0
T13	51488	442	0	0
T31	0	9399	0	0
T62	0	6071	0	0
T63	36605	0	0	0
T90	0	11941	0	0
T96	0	8610	0	0
T98	0	22061	0	0
T100	0	21439	0	0
T101	0	12209	0	0
T102	19569	0	0	0
T103	11685	0	0	0
T104	16521	0	0	0
T105	13652	0	0	0
T106	24703	0	0	0
T107	18845	0	0	0
T108	9840	0	0	0
T109	21991	0	0	0
T143	0	8641	0	0
T176	0	8622	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	25071784	0	0
T4	39226	7690	0	0
T5	67882	56805	0	0
T9	16233	0	0	0
T10	10549	0	0	0
T11	12064	2834	0	0
T12	17367	11553	0	0
T13	51488	10509	0	0
T52	0	91792	0	0
T63	0	25933	0	0
T102	19569	0	0	0
T103	11685	0	0	0
T104	16521	0	0	0
T105	0	2518	0	0
T143	0	15920	0	0
T161	0	2501	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T65,T78,T44

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T4,T9,T10
1	Covered	T1,T143,T52

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T24,T25,T26

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T142,T138
1	Covered	T142,T138

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T9

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T4,T9

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b11001010000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T3,T4

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T4,T9
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T4,T9
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T13,T105

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T13,T105

---

FSM Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T3
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T4,T9
ReadWaitSt	252	Covered	T1,T4,T9
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T3,T9
IdleSt->ReadSt	236	Covered	T1,T4,T9
InitSt->ErrorSt	315	Covered	T2,T10,T11
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T161,T163,T66
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T4,T11,T5
ReadSt->ReadWaitSt	252	Covered	T1,T4,T9
ReadWaitSt->ErrorSt	276	Covered	T171,T184,T195
ReadWaitSt->IdleSt	270	Covered	T1,T4,T9
ResetSt->ErrorSt	315	Covered	T71,T72,T73
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T4,T11,T5
CheckFailError	317	Covered	T142,T138
FsmStateError	289	Covered	T1,T2,T3
MacroEccCorrError	221	Covered	T1,T143,T52
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T107,T146,T7
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T4,T11,T5
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T142,T138
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T2,T3
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T1,T143,T65
MacroEccCorrError->NoError	235	Covered	T52,T55,T121
NoError->AccessError	256	Covered	T4,T11,T5
NoError->CheckFailError	317	Covered	T142,T138
NoError->FsmStateError	289	Covered	T1,T2,T3
NoError->MacroEccCorrError	221	Covered	T1,T143,T52

---

Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T9

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T9

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T13,T105
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T65,T78,T44
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T66,T196,T197
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T4,T9
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T4,T9
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T96,T97,T100
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T4,T11,T5
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T1,T143,T52
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T4,T9,T10
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T171,T184,T195
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T4,T9
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T24,T25,T26
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T3,T11
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T3,T11
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T24,T25,T26

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T142,T138
1	0	Covered	T142,T138
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	1451411390	1450559481	0	0
DigestKnown_A	1451411390	1450559481	0	0
DigestOffsetMustBeRepresentable_A	1123	1123	0	0
EccErrorState_A	1451411390	4998	0	0
ErrorKnown_A	1451411390	1450559481	0	0
FsmStateKnown_A	1451411390	1450559481	0	0
InitDoneKnown_A	1451411390	1450559481	0	0
InitReadLocksPartition_A	1451411390	286022163	0	0
InitWriteLocksPartition_A	1451411390	286022163	0	0
OffsetMustBeBlockAligned_A	1123	1123	0	0
OtpAddrKnown_A	1451411390	1450559481	0	0
OtpCmdKnown_A	1451411390	1450559481	0	0
OtpErrorState_A	1451411390	36	0	0
OtpReqKnown_A	1451411390	1450559481	0	0
OtpSizeKnown_A	1451411390	1450559481	0	0
OtpWdataKnown_A	1451411390	1450559481	0	0
ReadLockPropagation_A	1451411390	626899542	0	0
SizeMustBeBlockAligned_A	1123	1123	0	0
TlulGntKnown_A	1451411390	1450559481	0	0
TlulRdataKnown_A	1451411390	1450559481	0	0
TlulReadOnReadLock_A	1451411390	6950	0	0
TlulRerrorKnown_A	1451411390	1450559481	0	0
TlulRvalidKnown_A	1451411390	1450559481	0	0
WriteLockPropagation_A	1451411390	893890	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	1451411390	10175201	0	0
u_state_regs_A	1451411390	1450559481	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123	1123	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	4998	0	0
T138	0	2353	0	0
T142	12729	2645	0	0
T198	25995	0	0	0
T199	67015	0	0	0
T200	15181	0	0	0
T201	12844	0	0	0
T202	12855	0	0	0
T203	15587	0	0	0
T204	48024	0	0	0
T205	18167	0	0	0
T206	5009	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	286022163	0	0
T1	80703	13107	0	0
T2	21112	13997	0	0
T3	14351	8236	0	0
T4	39226	6427	0	0
T5	67882	1805	0	0
T9	16233	5907	0	0
T10	10549	3273	0	0
T11	12064	4078	0	0
T12	17367	4008	0	0
T13	51488	1633	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	286022163	0	0
T1	80703	13107	0	0
T2	21112	13997	0	0
T3	14351	8236	0	0
T4	39226	6427	0	0
T5	67882	1805	0	0
T9	16233	5907	0	0
T10	10549	3273	0	0
T11	12064	4078	0	0
T12	17367	4008	0	0
T13	51488	1633	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123	1123	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	36	0	0
T7	419805	0	0	0
T37	15774	0	0	0
T64	9353	0	0	0
T66	8918	1	0	0
T89	14973	0	0	0
T90	161660	0	0	0
T91	45812	0	0	0
T92	24007	0	0	0
T93	8896	0	0	0
T146	127988	0	0	0
T171	0	1	0	0
T184	0	1	0	0
T196	0	1	0	0
T197	0	1	0	0
T207	0	1	0	0
T208	0	1	0	0
T209	0	1	0	0
T210	0	1	0	0
T211	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	626899542	0	0
T1	80703	1175	0	0
T2	21112	0	0	0
T3	14351	0	0	0
T4	39226	453	0	0
T5	67882	12273	0	0
T9	16233	0	0	0
T10	10549	0	0	0
T11	12064	1751	0	0
T12	17367	1888	0	0
T13	51488	0	0	0
T31	0	47538	0	0
T52	0	28949	0	0
T105	0	2114	0	0
T107	0	10895	0	0
T145	0	22400	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123	1123	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	6950	0	0
T1	80703	8	0	0
T2	21112	0	0	0
T3	14351	2	0	0
T4	39226	1	0	0
T5	67882	6	0	0
T9	16233	0	0	0
T10	10549	0	0	0
T11	12064	4	0	0
T12	17367	1	0	0
T13	51488	0	0	0
T63	0	5	0	0
T105	0	6	0	0
T107	0	3	0	0
T109	0	2	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	893890	0	0
T13	51488	326	0	0
T62	0	2025	0	0
T63	36605	0	0	0
T90	0	11941	0	0
T96	0	18696	0	0
T102	19569	0	0	0
T103	11685	0	0	0
T104	16521	0	0	0
T105	13652	0	0	0
T106	24703	0	0	0
T107	18845	0	0	0
T108	9840	0	0	0
T109	21991	0	0	0
T111	0	11094	0	0
T121	0	2439	0	0
T128	0	952	0	0
T177	0	3951	0	0
T212	0	6387	0	0
T213	0	433	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	10175201	0	0
T1	80703	2733	0	0
T2	21112	0	0	0
T3	14351	0	0	0
T4	39226	0	0	0
T5	67882	0	0	0
T9	16233	0	0	0
T10	10549	0	0	0
T11	12064	0	0	0
T12	17367	0	0	0
T13	51488	24809	0	0
T62	0	56551	0	0
T63	0	25865	0	0
T89	0	4950	0	0
T90	0	138756	0	0
T96	0	82659	0	0
T105	0	2501	0	0
T214	0	2506	0	0
T215	0	3379	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451411390	1450559481	0	0
T1	80703	79122	0	0
T2	21112	20778	0	0
T3	14351	14171	0	0
T4	39226	38460	0	0
T5	67882	66650	0	0
T9	16233	15958	0	0
T10	10549	10258	0	0
T11	12064	11857	0	0
T12	17367	16957	0	0
T13	51488	50419	0	0