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ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE
tb.dut.u_otp_ctrl_dai.ScrmblMtxReqKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_otp_ctrl_dai.ScrmblSelKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_otp_ctrl_dai.ScrmblValidKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_otp_ctrl_dai.gen_part_sel[0].PartEndMax_A	0	0	1149	1149	0	0
tb.dut.u_otp_ctrl_dai.gen_part_sel[10].PartEndMax_A	0	0	1149	1149	0	0
tb.dut.u_otp_ctrl_dai.gen_part_sel[1].PartEndMax_A	0	0	1149	1149	0	0
tb.dut.u_otp_ctrl_dai.gen_part_sel[2].PartEndMax_A	0	0	1149	1149	0	0
tb.dut.u_otp_ctrl_dai.gen_part_sel[3].PartEndMax_A	0	0	1149	1149	0	0
tb.dut.u_otp_ctrl_dai.gen_part_sel[4].PartEndMax_A	0	0	1149	1149	0	0
tb.dut.u_otp_ctrl_dai.gen_part_sel[5].PartEndMax_A	0	0	1149	1149	0	0
tb.dut.u_otp_ctrl_dai.gen_part_sel[6].PartEndMax_A	0	0	1149	1149	0	0
tb.dut.u_otp_ctrl_dai.gen_part_sel[7].PartEndMax_A	0	0	1149	1149	0	0
tb.dut.u_otp_ctrl_dai.gen_part_sel[8].PartEndMax_A	0	0	1149	1149	0	0
tb.dut.u_otp_ctrl_dai.gen_part_sel[9].PartEndMax_A	0	0	1149	1149	0	0
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.CheckHotOne_A	0	0	516265254	515410973	0	0
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.CheckNGreaterZero_A	0	0	1149	1149	0	0
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.GrantKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.IdxKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.Priority_A	0	0	516265254	515410973	0	0
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.ReqImpliesValid_A	0	0	516265254	515410973	0	0
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.ValidKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_otp_ctrl_dai.u_state_regs.AssertConnected_A	0	0	1149	1149	0	0
tb.dut.u_otp_ctrl_dai.u_state_regs_A	0	0	516265254	515410973	0	0
tb.dut.u_otp_ctrl_kdi.EdnReqKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_otp_ctrl_kdi.EntropyWidthDividesDigestBlockWidth_A	0	0	1149	1149	0	0
tb.dut.u_otp_ctrl_kdi.FlashOtpKeyRspKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_otp_ctrl_kdi.FsmErrKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_otp_ctrl_kdi.KeyNonceSize0_A	0	0	1149	1149	0	0
tb.dut.u_otp_ctrl_kdi.KeyNonceSize1_A	0	0	1149	1149	0	0
tb.dut.u_otp_ctrl_kdi.KeyNonceSize2_A	0	0	1149	1149	0	0
tb.dut.u_otp_ctrl_kdi.KeyNonceSize3_A	0	0	1149	1149	0	0
tb.dut.u_otp_ctrl_kdi.KeyNonceSize4_A	0	0	1149	1149	0	0
tb.dut.u_otp_ctrl_kdi.KeyNonceSize5_A	0	0	1149	1149	0	0
tb.dut.u_otp_ctrl_kdi.KeyNonceSize6_A	0	0	1149	1149	0	0
tb.dut.u_otp_ctrl_kdi.NonceWidth_A	0	0	1149	1149	0	0
tb.dut.u_otp_ctrl_kdi.OtbnOtpKeyRspKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_otp_ctrl_kdi.ScrmblCmdKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_otp_ctrl_kdi.ScrmblDataKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_otp_ctrl_kdi.ScrmblModeKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_otp_ctrl_kdi.ScrmblMtxReqKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_otp_ctrl_kdi.ScrmblSelKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_otp_ctrl_kdi.ScrmblValidKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_otp_ctrl_kdi.SramOtpKeyRspKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_otp_ctrl_kdi.u_req_arb.CheckHotOne_A	0	0	516265254	515410973	0	0
tb.dut.u_otp_ctrl_kdi.u_req_arb.CheckNGreaterZero_A	0	0	1149	1149	0	0
tb.dut.u_otp_ctrl_kdi.u_req_arb.GntImpliesReady_A	0	0	516265254	42251	0	0
tb.dut.u_otp_ctrl_kdi.u_req_arb.GntImpliesValid_A	0	0	516265254	42251	0	0
tb.dut.u_otp_ctrl_kdi.u_req_arb.GrantKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_otp_ctrl_kdi.u_req_arb.IdxKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_otp_ctrl_kdi.u_req_arb.IndexIsCorrect_A	0	0	516265254	42251	0	0
tb.dut.u_otp_ctrl_kdi.u_req_arb.LockArbDecision_A	0	0	516265254	75903886	0	0
tb.dut.u_otp_ctrl_kdi.u_req_arb.NoReadyValidNoGrant_A	0	0	516265254	439462550	0	0
tb.dut.u_otp_ctrl_kdi.u_req_arb.ReadyAndValidImplyGrant_A	0	0	516265254	42251	0	0
tb.dut.u_otp_ctrl_kdi.u_req_arb.ReqAndReadyImplyGrant_A	0	0	516265254	42251	0	0
tb.dut.u_otp_ctrl_kdi.u_req_arb.ReqImpliesValid_A	0	0	516265254	75948423	0	0
tb.dut.u_otp_ctrl_kdi.u_req_arb.ReqStaysHighUntilGranted0_M	0	0	516265254	75903886	0	0
tb.dut.u_otp_ctrl_kdi.u_req_arb.ValidKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_otp_ctrl_kdi.u_req_arb.gen_data_port_assertion.DataFlow_A	0	0	516265254	42251	0	0
tb.dut.u_otp_ctrl_kdi.u_state_regs.AssertConnected_A	0	0	1149	1149	0	0
tb.dut.u_otp_ctrl_kdi.u_state_regs_A	0	0	516265254	515410973	0	0
tb.dut.u_otp_ctrl_lci.ErrorKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_otp_ctrl_lci.LcAckKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_otp_ctrl_lci.LcErrKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_otp_ctrl_lci.LcValueMustBeWiderThanNativeOtpWidth_A	0	0	1149	1149	0	0
tb.dut.u_otp_ctrl_lci.LciIdleKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_otp_ctrl_lci.OtpAddrKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_otp_ctrl_lci.OtpCmdKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_otp_ctrl_lci.OtpReqKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_otp_ctrl_lci.OtpSizeKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_otp_ctrl_lci.OtpWdataKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_otp_ctrl_lci.u_state_regs.AssertConnected_A	0	0	1149	1149	0	0
tb.dut.u_otp_ctrl_lci.u_state_regs_A	0	0	516265254	515410973	0	0
tb.dut.u_otp_ctrl_lfsr_timer.ChkPendingKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_otp_ctrl_lfsr_timer.ChkTimeoutKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_otp_ctrl_lfsr_timer.CnstyChkReqKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_otp_ctrl_lfsr_timer.EdnIsWideEnough_A	0	0	1149	1149	0	0
tb.dut.u_otp_ctrl_lfsr_timer.EdnReqKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_otp_ctrl_lfsr_timer.IntegChkReqKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.AssertConnected_A	0	0	1149	1149	0	0
tb.dut.u_otp_ctrl_lfsr_timer.u_state_regs.AssertConnected_A	0	0	1149	1149	0	0
tb.dut.u_otp_ctrl_lfsr_timer.u_state_regs_A	0	0	516265254	515410973	0	0
tb.dut.u_otp_ctrl_scrmbl.CheckNumDecKeys_A	0	0	516265254	249839	0	0
tb.dut.u_otp_ctrl_scrmbl.CheckNumDigest1_A	0	0	516265254	148124	0	0
tb.dut.u_otp_ctrl_scrmbl.CheckNumEncKeys_A	0	0	516265254	268279	0	0
tb.dut.u_otp_ctrl_scrmbl.DecKeyLutKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_otp_ctrl_scrmbl.DigestConstLutKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_otp_ctrl_scrmbl.DigestIvLutKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_otp_ctrl_scrmbl.EncKeyLutKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_otp_ctrl_scrmbl.NumMaxPresentRounds_A	0	0	1149	1149	0	0
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_dec.SupportedNumPhysRounds0_A	0	0	1149	1149	0	0
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_dec.SupportedNumPhysRounds1_A	0	0	1149	1149	0	0
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_dec.SupportedNumRounds_A	0	0	1149	1149	0	0
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_dec.SupportedWidths_A	0	0	1149	1149	0	0
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_enc.SupportedNumPhysRounds0_A	0	0	1149	1149	0	0
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_enc.SupportedNumPhysRounds1_A	0	0	1149	1149	0	0
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_enc.SupportedNumRounds_A	0	0	1149	1149	0	0
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_enc.SupportedWidths_A	0	0	1149	1149	0	0
tb.dut.u_otp_ctrl_scrmbl.u_state_regs.AssertConnected_A	0	0	1149	1149	0	0
tb.dut.u_otp_ctrl_scrmbl.u_state_regs_A	0	0	516265254	515410973	0	0
tb.dut.u_otp_rsp_fifo.DataKnown_A	0	0	516265254	17721563	0	0
tb.dut.u_otp_rsp_fifo.DepthKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_otp_rsp_fifo.RvalidKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_otp_rsp_fifo.WreadyKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_otp_rsp_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	516265254	17721563	0	0
tb.dut.u_part_sel_idx.CheckHotOne_A	0	0	516265254	515410973	0	0
tb.dut.u_part_sel_idx.CheckNGreaterZero_A	0	0	1149	1149	0	0
tb.dut.u_part_sel_idx.GrantKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_part_sel_idx.IdxKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_part_sel_idx.Priority_A	0	0	516265254	515410973	0	0
tb.dut.u_part_sel_idx.ReqImpliesValid_A	0	0	516265254	515410973	0	0
tb.dut.u_part_sel_idx.ValidKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_prim_edn_req.DataOutputDiffFromPrev_A	0	0	516265254	276392439	0	0
tb.dut.u_prim_edn_req.DataOutputValid_A	0	0	516265254	266396	0	0
tb.dut.u_prim_edn_req.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	0	0	516265254	533177	0	0
tb.dut.u_prim_edn_req.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	0	0	516265254	533130	0	0
tb.dut.u_prim_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckAckNeedsReq	0	0	1437368023	533339	0	0
tb.dut.u_prim_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckHoldReq	0	0	516265254	266190	0	0
tb.dut.u_prim_lc_sync_check_byp_en.NumCopiesMustBeGreaterZero_A	0	0	1149	1149	0	0
tb.dut.u_prim_lc_sync_check_byp_en.OutputsKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_prim_lc_sync_check_byp_en.gen_flops.OutputDelay_A	0	0	516265254	515370658	0	3447
tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en.NumCopiesMustBeGreaterZero_A	0	0	1149	1149	0	0
tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en.OutputsKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en.gen_flops.OutputDelay_A	0	0	516265254	515370658	0	3447
tb.dut.u_prim_lc_sync_dft_en.NumCopiesMustBeGreaterZero_A	0	0	1149	1149	0	0
tb.dut.u_prim_lc_sync_dft_en.OutputsKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_prim_lc_sync_dft_en.gen_flops.OutputDelay_A	0	0	516265254	515370658	0	3447
tb.dut.u_prim_lc_sync_escalate_en.NumCopiesMustBeGreaterZero_A	0	0	1149	1149	0	0
tb.dut.u_prim_lc_sync_escalate_en.OutputsKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_prim_lc_sync_escalate_en.gen_flops.OutputDelay_A	0	0	516265254	515370658	0	3447
tb.dut.u_prim_lc_sync_owner_seed_sw_rw_en.NumCopiesMustBeGreaterZero_A	0	0	1149	1149	0	0
tb.dut.u_prim_lc_sync_owner_seed_sw_rw_en.OutputsKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_prim_lc_sync_owner_seed_sw_rw_en.gen_flops.OutputDelay_A	0	0	516265254	515370658	0	3447
tb.dut.u_prim_lc_sync_seed_hw_rd_en.NumCopiesMustBeGreaterZero_A	0	0	1149	1149	0	0
tb.dut.u_prim_lc_sync_seed_hw_rd_en.OutputsKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_prim_lc_sync_seed_hw_rd_en.gen_flops.OutputDelay_A	0	0	516265254	515370658	0	3447
tb.dut.u_reg_core.en2addrHit	0	0	519505586	9666094	0	0
tb.dut.u_reg_core.reAfterRv	0	0	519505586	9666094	0	0
tb.dut.u_reg_core.rePulse	0	0	519505586	7634531	0	0
tb.dut.u_reg_core.u_chk.PayLoadWidthCheck	0	0	1324	1324	0	0
tb.dut.u_reg_core.u_reg_if.AllowedLatency_A	0	0	1324	1324	0	0
tb.dut.u_reg_core.u_reg_if.MatchedWidthAssert	0	0	1324	1324	0	0
tb.dut.u_reg_core.u_reg_if.u_err.dataWidthOnly32_A	0	0	1324	1324	0	0
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	1324	1324	0	0
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1324	1324	0	0
tb.dut.u_reg_core.u_rsp_intg_gen.DataWidthCheck_A	0	0	1324	1324	0	0
tb.dut.u_reg_core.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1324	1324	0	0
tb.dut.u_reg_core.u_socket.NotOverflowed_A	0	0	519505586	518593810	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.DataKnown_A	0	0	519505586	65019050	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.DepthKnown_A	0	0	519505586	518593810	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.RvalidKnown_A	0	0	519505586	518593810	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.WreadyKnown_A	0	0	519505586	518593810	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1324	1324	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DataKnown_A	0	0	519505586	72293544	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DepthKnown_A	0	0	519505586	518593810	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.RvalidKnown_A	0	0	519505586	518593810	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.WreadyKnown_A	0	0	519505586	518593810	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1324	1324	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DataKnown_A	0	0	519505586	21294611	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DepthKnown_A	0	0	519505586	518593810	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.RvalidKnown_A	0	0	519505586	518593810	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.WreadyKnown_A	0	0	519505586	518593810	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1324	1324	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DataKnown_A	0	0	519505586	28739037	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DepthKnown_A	0	0	519505586	518593810	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A	0	0	519505586	518593810	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.WreadyKnown_A	0	0	519505586	518593810	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1324	1324	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DataKnown_A	0	0	519505586	30543950	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DepthKnown_A	0	0	519505586	518593810	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.RvalidKnown_A	0	0	519505586	518593810	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.WreadyKnown_A	0	0	519505586	518593810	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1324	1324	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DataKnown_A	0	0	519505586	43554507	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DepthKnown_A	0	0	519505586	518593810	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A	0	0	519505586	518593810	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.WreadyKnown_A	0	0	519505586	518593810	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1324	1324	0	0
tb.dut.u_reg_core.u_socket.maxN	0	0	1324	1324	0	0
tb.dut.u_reg_core.wePulse	0	0	519505586	2031563	0	0
tb.dut.u_scrmbl_mtx.CheckHotOne_A	0	0	516265254	515410973	0	0
tb.dut.u_scrmbl_mtx.CheckNGreaterZero_A	0	0	1149	1149	0	0
tb.dut.u_scrmbl_mtx.GrantKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_scrmbl_mtx.IdxKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_scrmbl_mtx.NoReadyValidNoGrant_A	0	0	516265254	469060853	0	0
tb.dut.u_scrmbl_mtx.ReqImpliesValid_A	0	0	516265254	46350120	0	0
tb.dut.u_scrmbl_mtx.ValidKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_tlul_adapter_sram.AddrOutKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_tlul_adapter_sram.DataIntgOptions_A	0	0	1149	1149	0	0
tb.dut.u_tlul_adapter_sram.ReqOutKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_tlul_adapter_sram.SramDwHasByteGranularity_A	0	0	1149	1149	0	0
tb.dut.u_tlul_adapter_sram.SramDwIsMultipleOfTlulWidth_A	0	0	1149	1149	0	0
tb.dut.u_tlul_adapter_sram.TlOutKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_tlul_adapter_sram.TlOutPayloadKnown_A	0	0	516265254	28709620	0	0
tb.dut.u_tlul_adapter_sram.TlOutPayloadKnown_AKnownEnable	0	0	516265254	515410973	0	0
tb.dut.u_tlul_adapter_sram.WdataOutKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_tlul_adapter_sram.WeOutKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_tlul_adapter_sram.WmaskOutKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_tlul_adapter_sram.adapterNoReadOrWrite	0	0	1149	1149	0	0
tb.dut.u_tlul_adapter_sram.rvalidHighReqFifoEmpty	0	0	516265254	103712	0	0
tb.dut.u_tlul_adapter_sram.rvalidHighWhenRspFifoFull	0	0	516265254	103712	0	0
tb.dut.u_tlul_adapter_sram.u_err.dataWidthOnly32_A	0	0	1149	1149	0	0
tb.dut.u_tlul_adapter_sram.u_reqfifo.DataKnown_A	0	0	516265254	29268277	0	0
tb.dut.u_tlul_adapter_sram.u_reqfifo.DepthKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_tlul_adapter_sram.u_reqfifo.RvalidKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_tlul_adapter_sram.u_reqfifo.WreadyKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_tlul_adapter_sram.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	516265254	29268277	0	0
tb.dut.u_tlul_adapter_sram.u_rsp_gen.DataWidthCheck_A	0	0	1149	1149	0	0
tb.dut.u_tlul_adapter_sram.u_rsp_gen.PayLoadWidthCheck	0	0	1149	1149	0	0
tb.dut.u_tlul_adapter_sram.u_rspfifo.DataKnown_A	0	0	516265254	243109	0	0
tb.dut.u_tlul_adapter_sram.u_rspfifo.DepthKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_tlul_adapter_sram.u_rspfifo.RvalidKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_tlul_adapter_sram.u_rspfifo.WreadyKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_tlul_adapter_sram.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	516265254	243109	0	0
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.DataKnown_A	0	0	516265254	662369	0	0
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.DepthKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.RvalidKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.WreadyKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	516265254	662369	0	0
tb.dut.u_tlul_lc_gate.u_err_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1149	1149	0	0
tb.dut.u_tlul_lc_gate.u_err_en_sync.OutputsKnown_A	0	0	516265254	515410973	0	0
tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_no_flops.OutputDelay_A	0	0	516265254	515410973	0	0
tb.dut.u_tlul_lc_gate.u_state_regs.AssertConnected_A	0	0	1149	1149	0	0
tb.dut.u_tlul_lc_gate.u_state_regs_A	0	0	516265254	515410973	0	0
tb.dut.u_tlul_lc_gate.u_tlul_err_resp.u_intg_gen.DataWidthCheck_A	0	0	1149	1149	0	0
tb.dut.u_tlul_lc_gate.u_tlul_err_resp.u_intg_gen.PayLoadWidthCheck	0	0	1149	1149	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_arb.RoundRobin_A	0	0	516265254	0	0	1149
tb.dut.u_otp_arb.RoundRobin_A	0	0	516265254	0	0	1149
tb.dut.u_otp_ctrl_kdi.u_req_arb.RoundRobin_A	0	0	516265254	0	0	1149
tb.dut.u_prim_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	516265254	0	0	1149
tb.dut.u_prim_lc_sync_check_byp_en.gen_flops.OutputDelay_A	0	0	516265254	515370658	0	3447
tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en.gen_flops.OutputDelay_A	0	0	516265254	515370658	0	3447
tb.dut.u_prim_lc_sync_dft_en.gen_flops.OutputDelay_A	0	0	516265254	515370658	0	3447
tb.dut.u_prim_lc_sync_escalate_en.gen_flops.OutputDelay_A	0	0	516265254	515370658	0	3447
tb.dut.u_prim_lc_sync_owner_seed_sw_rw_en.gen_flops.OutputDelay_A	0	0	516265254	515370658	0	3447
tb.dut.u_prim_lc_sync_seed_hw_rd_en.gen_flops.OutputDelay_A	0	0	516265254	515370658	0	3447
tb.dut.u_scrmbl_mtx.RoundRobin_A	0	0	516265254	0	0	1149

Assertions Without Attempts:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.OtpErrorState_A	0	0	0	0	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.OtpErrorState_A	0	0	0	0	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.OtpErrorState_A	0	0	0	0	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.OtpErrorState_A	0	0	0	0	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.OtpErrorState_A	0	0	0	0	0	0

---

Detail Report for Cover Sequences

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.core_tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	519506548	1189	1189	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	519506548	278	278	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	519506548	281	281	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	519506548	183	183	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	519506548	44	44	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	519506548	148	148	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	519506548	133	133	0
tb.dut.core_tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	519506548	3406	3406	0
tb.dut.core_tlul_assert_device.gen_device_cov.b2bReq_C	0	0	519506548	7193	7193	0
tb.dut.core_tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	519506548	3320032	3320032	1223
tb.dut.prim_tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	519506548	300	300	0
tb.dut.prim_tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	519506548	90	90	1
tb.dut.prim_tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	519506548	94	94	1
tb.dut.prim_tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	519506548	66	66	1
tb.dut.prim_tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	519506548	8	8	1
tb.dut.prim_tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	519506548	60	60	1
tb.dut.prim_tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	519506548	28	28	1
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	519506548	1028	1028	0
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bReq_C	0	0	519506548	2623	2623	0
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	519506548	60538	60538	59

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.core_tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	519506548	1189	1189	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	519506548	278	278	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	519506548	281	281	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	519506548	183	183	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	519506548	44	44	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	519506548	148	148	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	519506548	133	133	0
tb.dut.core_tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	519506548	3406	3406	0
tb.dut.core_tlul_assert_device.gen_device_cov.b2bReq_C	0	0	519506548	7193	7193	0
tb.dut.core_tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	519506548	3320032	3320032	1223
tb.dut.prim_tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	519506548	300	300	0
tb.dut.prim_tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	519506548	90	90	1
tb.dut.prim_tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	519506548	94	94	1
tb.dut.prim_tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	519506548	66	66	1
tb.dut.prim_tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	519506548	8	8	1
tb.dut.prim_tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	519506548	60	60	1
tb.dut.prim_tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	519506548	28	28	1
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	519506548	1028	1028	0
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bReq_C	0	0	519506548	2623	2623	0
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	519506548	60538	60538	59