Unified Coverage Report :: Module :: otp_ctrl_part_unbuf

Module : otp_ctrl_part_unbuf

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.82	98.49	96.36		64.71	94.57	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf	97.23	100.00	100.00		90.00	100.00	96.15
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf	98.33	100.00	100.00		91.67	100.00	100.00
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf	98.33	100.00	100.00		91.67	100.00	100.00
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf	98.33	100.00	100.00		91.67	100.00	100.00
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf	98.33	100.00	100.00		91.67	100.00	100.00

Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=65616,DigestOffset=56,StateWidth=10 )
Line Coverage for Module self-instances :

SCORE	LINE
97.23	100.00

tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		93	86	92.47
CONT_ASSIGN	138	1	1	100.00
ALWAYS	153	3	3	100.00
ALWAYS	164	68	61	89.71
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
153	1	1
154	1	1
156	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			==> MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	0	1
			MISSING_ELSE
224	0	1
225	0	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	0	1
			MISSING_ELSE
276	0	1
277	0	1
279	0	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
339	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=134651988,DigestOffset=480,StateWidth=10 )
Line Coverage for Module self-instances :

SCORE	LINE
98.33	100.00

tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=1024082004,DigestOffset=1136,StateWidth=10 )
Line Coverage for Module self-instances :

SCORE	LINE
98.33	100.00

tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=-1,DigestOffset=1608,StateWidth=10 )
Line Coverage for Module self-instances :

SCORE	LINE
98.33	100.00

tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=-1,DigestOffset=1648,StateWidth=10 )
Line Coverage for Module self-instances :

SCORE	LINE
98.33	100.00

tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=-1,DigestOffset=1608,StateWidth=10 )
Cond Coverage for Module self-instances :

SCORE	COND
98.33	100.00

tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	34	33	97.06
Logical	34	33	97.06
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T60,T127,T128

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T5,T4
1	Covered	T22,T129,T130

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T16,T17,T18

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T67,T131,T132
1	Covered	T67,T131,T132

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T5

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b10001111000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T5,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T5,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T10

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T10

---

Cond Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=65616,DigestOffset=56,StateWidth=10 )
Cond Coverage for Module self-instances :

SCORE	COND
97.23	100.00

tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	31	29	93.55
Logical	31	29	93.55
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T5,T4
1	Not Covered

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T16,T17,T18

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T67,T69
1	Covered	T67,T69

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T5

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T3,T5,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T3,T5,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T3,T5,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

---

Cond Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=134651988,DigestOffset=480,StateWidth=10 )
Cond Coverage for Module self-instances :

SCORE	COND
98.33	100.00

tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	34	33	97.06
Logical	34	33	97.06
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T61,T88,T128

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T5,T4
1	Covered	T22,T129,T130

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T16,T17,T18

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T69,T132,T133
1	Covered	T69,T132,T133

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T5

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T3,T5,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T3,T5,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T3,T5,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

---

Cond Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=1024082004,DigestOffset=1136,StateWidth=10 )
Cond Coverage for Module self-instances :

SCORE	COND
98.33	100.00

tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	34	33	97.06
Logical	34	33	97.06
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T134,T73,T135

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T5,T4,T6
1	Covered	T22,T129,T130

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T16,T17,T18

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T69,T136
1	Covered	T69,T136

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T5

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T4,T6

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T5,T4,T6

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00111101000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T5

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T5,T4,T6
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T5,T4,T6
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=-1,DigestOffset=1648,StateWidth=10 )
Cond Coverage for Module self-instances :

SCORE	COND
98.33	100.00

tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	34	33	97.06
Logical	34	33	97.06
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T70,T37,T44

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T5,T4,T6
1	Covered	T22,T129,T130

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T16,T17,T18

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T67,T131,T136
1	Covered	T67,T131,T136

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T5

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T4,T6

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T8,T4
1	1	Covered	T5,T4,T6

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b11001010000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T5,T8

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T5,T4,T6
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T5,T4,T6
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T61,T96

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T61,T96

---

FSM Coverage for Module : otp_ctrl_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T5
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T2,T3,T5
ReadWaitSt	252	Covered	T2,T3,T5
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
IdleSt->ErrorSt	315	Covered	T1,T2,T5
IdleSt->ReadSt	236	Covered	T2,T3,T5
InitSt->ErrorSt	315	Covered	T137,T138,T85
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T103,T137,T138
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T2,T3,T4
ReadSt->ReadWaitSt	252	Covered	T2,T3,T5
ReadWaitSt->ErrorSt	276	Covered	T129,T130,T139
ReadWaitSt->IdleSt	270	Covered	T2,T3,T5
ResetSt->ErrorSt	315	Covered	T67,T68,T69
ResetSt->IdleSt	196	Not Covered
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	20	10	50.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T2,T3,T4
CheckFailError	317	Covered	T67,T69,T131
FsmStateError	289	Covered	T1,T2,T5
MacroEccCorrError	221	Covered	T61,T22,T134
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AccessError->CheckFailError	317	Not Covered
AccessError->FsmStateError	325	Covered	T2,T4,T6
AccessError->MacroEccCorrError	221	Not Covered
AccessError->NoError	235	Covered	T2,T3,T4
CheckFailError->AccessError	256	Not Covered
CheckFailError->FsmStateError	325	Not Covered
CheckFailError->MacroEccCorrError	221	Not Covered
CheckFailError->NoError	235	Covered	T67,T69,T131
FsmStateError->AccessError	256	Not Covered
FsmStateError->CheckFailError	317	Not Covered
FsmStateError->MacroEccCorrError	221	Not Covered
FsmStateError->NoError	235	Covered	T1,T2,T5
MacroEccCorrError->AccessError	256	Not Covered
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T61,T134,T129
MacroEccCorrError->NoError	235	Covered	T22,T130,T39
NoError->AccessError	256	Covered	T2,T3,T4
NoError->CheckFailError	317	Covered	T67,T69,T131
NoError->FsmStateError	289	Covered	T1,T2,T5
NoError->MacroEccCorrError	221	Covered	T61,T22,T134

---

Branch Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=65616,DigestOffset=56,StateWidth=10 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
97.23	100.00

tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		46	41	89.13
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	18	78.26
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00
IF	153	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T5
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T3,T5,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T3,T4,T12
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T4,T6
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T3,T5,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T3,T5,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T16,T17,T18
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T2,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T2,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T5
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T67,T69
1	0	Covered	T67,T69
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	if ((otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T1,T2,T3

---

Branch Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=134651988,DigestOffset=480,StateWidth=10 + Info=1024082004,DigestOffset=1136,StateWidth=10 + Info=-1,DigestOffset=1608,StateWidth=10 + Info=-1,DigestOffset=1648,StateWidth=10 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.33	100.00

tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

SCORE	BRANCH
98.33	100.00

tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

SCORE	BRANCH
98.33	100.00

tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

SCORE	BRANCH
98.33	100.00

tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T61,T134,T73
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T103,T104,T140
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T5
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T5
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T3,T4,T6
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T3,T4,T6
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T22,T129,T130
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T5
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T129,T130,T139
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T16,T17,T18
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T2,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T2,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T5
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T67,T69,T131
1	0	Covered	T67,T69,T131
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : otp_ctrl_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	1999827655	1995365540	0	0
DigestKnown_A	1999827655	1995365540	0	0
DigestOffsetMustBeRepresentable_A	5710	5710	0	0
EccErrorState_A	1999827655	51414	0	0
ErrorKnown_A	1999827655	1995365540	0	0
FsmStateKnown_A	1999827655	1995365540	0	0
InitDoneKnown_A	1999827655	1995365540	0	0
InitReadLocksPartition_A	1999827655	460874530	0	0
InitWriteLocksPartition_A	1999827655	460874530	0	0
OffsetMustBeBlockAligned_A	5710	5710	0	0
OtpAddrKnown_A	1999827655	1995365540	0	0
OtpCmdKnown_A	1999827655	1995365540	0	0
OtpErrorState_A	1999827655	217	0	0
OtpReqKnown_A	1999827655	1995365540	0	0
OtpSizeKnown_A	1999827655	1995365540	0	0
OtpWdataKnown_A	1999827655	1995365540	0	0
ReadLockPropagation_A	1999827655	867721418	0	0
SizeMustBeBlockAligned_A	5710	5710	0	0
TlulGntKnown_A	1999827655	1995365540	0	0
TlulRdataKnown_A	1999827655	1995365540	0	0
TlulReadOnReadLock_A	1999827655	39534	0	0
TlulRerrorKnown_A	1999827655	1995365540	0	0
TlulRvalidKnown_A	1999827655	1995365540	0	0
WriteLockPropagation_A	1999827655	12002789	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	1999827655	144586443	0	0
u_state_regs_A	1999827655	1995365540	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1999827655	1995365540	0	0
T1	50275	48845	0	0
T2	49680	48635	0	0
T3	209255	204890	0	0
T4	4607230	4569350	0	0
T5	74340	73065	0	0
T6	3696300	3696080	0	0
T7	137790	136385	0	0
T8	48945	48065	0	0
T9	126650	124640	0	0
T10	87160	85220	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1999827655	1995365540	0	0
T1	50275	48845	0	0
T2	49680	48635	0	0
T3	209255	204890	0	0
T4	4607230	4569350	0	0
T5	74340	73065	0	0
T6	3696300	3696080	0	0
T7	137790	136385	0	0
T8	48945	48065	0	0
T9	126650	124640	0	0
T10	87160	85220	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5710	5710	0	0
T1	5	5	0	0
T2	5	5	0	0
T3	5	5	0	0
T4	5	5	0	0
T5	5	5	0	0
T6	5	5	0	0
T7	5	5	0	0
T8	5	5	0	0
T9	5	5	0	0
T10	5	5	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1999827655	51414	0	0
T43	45630	0	0	0
T65	65326	0	0	0
T67	39858	11589	0	0
T68	46482	0	0	0
T69	17798	6582	0	0
T110	2478339	0	0	0
T114	90411	0	0	0
T131	0	4236	0	0
T132	0	7896	0	0
T133	0	5170	0	0
T136	0	9927	0	0
T141	0	6014	0	0
T142	86760	0	0	0
T143	33051	0	0	0
T144	542754	0	0	0
T145	728691	0	0	0
T146	2522895	0	0	0
T147	56630	0	0	0
T148	1555642	0	0	0
T149	57880	0	0	0
T150	30430	0	0	0
T151	299456	0	0	0
T152	62536	0	0	0
T153	21418	0	0	0
T154	160898	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1999827655	1995365540	0	0
T1	50275	48845	0	0
T2	49680	48635	0	0
T3	209255	204890	0	0
T4	4607230	4569350	0	0
T5	74340	73065	0	0
T6	3696300	3696080	0	0
T7	137790	136385	0	0
T8	48945	48065	0	0
T9	126650	124640	0	0
T10	87160	85220	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1999827655	1995365540	0	0
T1	50275	48845	0	0
T2	49680	48635	0	0
T3	209255	204890	0	0
T4	4607230	4569350	0	0
T5	74340	73065	0	0
T6	3696300	3696080	0	0
T7	137790	136385	0	0
T8	48945	48065	0	0
T9	126650	124640	0	0
T10	87160	85220	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1999827655	1995365540	0	0
T1	50275	48845	0	0
T2	49680	48635	0	0
T3	209255	204890	0	0
T4	4607230	4569350	0	0
T5	74340	73065	0	0
T6	3696300	3696080	0	0
T7	137790	136385	0	0
T8	48945	48065	0	0
T9	126650	124640	0	0
T10	87160	85220	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1999827655	460874530	0	0
T1	50275	12580	0	0
T2	49680	17675	0	0
T3	209255	5980	0	0
T4	4607230	1475735	0	0
T5	74340	25370	0	0
T6	3696300	319520	0	0
T7	137790	72080	0	0
T8	48945	22260	0	0
T9	126650	48185	0	0
T10	87160	31210	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1999827655	460874530	0	0
T1	50275	12580	0	0
T2	49680	17675	0	0
T3	209255	5980	0	0
T4	4607230	1475735	0	0
T5	74340	25370	0	0
T6	3696300	319520	0	0
T7	137790	72080	0	0
T8	48945	22260	0	0
T9	126650	48185	0	0
T10	87160	31210	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5710	5710	0	0
T1	5	5	0	0
T2	5	5	0	0
T3	5	5	0	0
T4	5	5	0	0
T5	5	5	0	0
T6	5	5	0	0
T7	5	5	0	0
T8	5	5	0	0
T9	5	5	0	0
T10	5	5	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1999827655	1995365540	0	0
T1	50275	48845	0	0
T2	49680	48635	0	0
T3	209255	204890	0	0
T4	4607230	4569350	0	0
T5	74340	73065	0	0
T6	3696300	3696080	0	0
T7	137790	136385	0	0
T8	48945	48065	0	0
T9	126650	124640	0	0
T10	87160	85220	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1999827655	1995365540	0	0
T1	50275	48845	0	0
T2	49680	48635	0	0
T3	209255	204890	0	0
T4	4607230	4569350	0	0
T5	74340	73065	0	0
T6	3696300	3696080	0	0
T7	137790	136385	0	0
T8	48945	48065	0	0
T9	126650	124640	0	0
T10	87160	85220	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1999827655	217	0	0
T11	211326	0	0	0
T23	67494	0	0	0
T31	627287	0	0	0
T32	512446	0	0	0
T86	0	1	0	0
T89	30144	0	0	0
T90	111874	0	0	0
T91	99676	0	0	0
T92	272581	0	0	0
T98	26650	0	0	0
T99	25294	0	0	0
T103	11410	1	0	0
T104	32064	1	0	0
T129	69165	2	0	0
T130	0	1	0	0
T134	17706	0	0	0
T137	14125	1	0	0
T138	0	1	0	0
T139	0	2	0	0
T140	12236	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0
T164	0	1	0	0
T165	0	1	0	0
T166	0	2	0	0
T167	179222	0	0	0
T168	41398	0	0	0
T169	34985	0	0	0
T170	518255	0	0	0
T171	5388	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1999827655	1995365540	0	0
T1	50275	48845	0	0
T2	49680	48635	0	0
T3	209255	204890	0	0
T4	4607230	4569350	0	0
T5	74340	73065	0	0
T6	3696300	3696080	0	0
T7	137790	136385	0	0
T8	48945	48065	0	0
T9	126650	124640	0	0
T10	87160	85220	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1999827655	1995365540	0	0
T1	50275	48845	0	0
T2	49680	48635	0	0
T3	209255	204890	0	0
T4	4607230	4569350	0	0
T5	74340	73065	0	0
T6	3696300	3696080	0	0
T7	137790	136385	0	0
T8	48945	48065	0	0
T9	126650	124640	0	0
T10	87160	85220	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1999827655	1995365540	0	0
T1	50275	48845	0	0
T2	49680	48635	0	0
T3	209255	204890	0	0
T4	4607230	4569350	0	0
T5	74340	73065	0	0
T6	3696300	3696080	0	0
T7	137790	136385	0	0
T8	48945	48065	0	0
T9	126650	124640	0	0
T10	87160	85220	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1999827655	867721418	0	0
T2	29808	13572	0	0
T3	209255	4128	0	0
T4	4607230	1175537	0	0
T5	74340	0	0	0
T6	3696300	801798	0	0
T7	137790	81796	0	0
T8	48945	0	0	0
T9	126650	13131	0	0
T10	87160	16529	0	0
T22	0	14928	0	0
T61	38935	0	0	0
T95	25670	0	0	0
T96	0	16541	0	0
T97	0	206509	0	0
T167	0	143138	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5710	5710	0	0
T1	5	5	0	0
T2	5	5	0	0
T3	5	5	0	0
T4	5	5	0	0
T5	5	5	0	0
T6	5	5	0	0
T7	5	5	0	0
T8	5	5	0	0
T9	5	5	0	0
T10	5	5	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1999827655	1995365540	0	0
T1	50275	48845	0	0
T2	49680	48635	0	0
T3	209255	204890	0	0
T4	4607230	4569350	0	0
T5	74340	73065	0	0
T6	3696300	3696080	0	0
T7	137790	136385	0	0
T8	48945	48065	0	0
T9	126650	124640	0	0
T10	87160	85220	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1999827655	1995365540	0	0
T1	50275	48845	0	0
T2	49680	48635	0	0
T3	209255	204890	0	0
T4	4607230	4569350	0	0
T5	74340	73065	0	0
T6	3696300	3696080	0	0
T7	137790	136385	0	0
T8	48945	48065	0	0
T9	126650	124640	0	0
T10	87160	85220	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1999827655	39534	0	0
T1	50275	19	0	0
T2	49680	19	0	0
T3	209255	1	0	0
T4	4607230	390	0	0
T5	74340	0	0	0
T6	3696300	292	0	0
T7	137790	52	0	0
T8	48945	4	0	0
T9	126650	46	0	0
T10	87160	135	0	0
T22	0	55	0	0
T96	0	12	0	0
T97	0	38	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1999827655	1995365540	0	0
T1	50275	48845	0	0
T2	49680	48635	0	0
T3	209255	204890	0	0
T4	4607230	4569350	0	0
T5	74340	73065	0	0
T6	3696300	3696080	0	0
T7	137790	136385	0	0
T8	48945	48065	0	0
T9	126650	124640	0	0
T10	87160	85220	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1999827655	1995365540	0	0
T1	50275	48845	0	0
T2	49680	48635	0	0
T3	209255	204890	0	0
T4	4607230	4569350	0	0
T5	74340	73065	0	0
T6	3696300	3696080	0	0
T7	137790	136385	0	0
T8	48945	48065	0	0
T9	126650	124640	0	0
T10	87160	85220	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1999827655	12002789	0	0
T3	83702	998	0	0
T4	4607230	97360	0	0
T5	29736	0	0	0
T6	3696300	0	0	0
T7	137790	0	0	0
T8	19578	0	0	0
T9	126650	0	0	0
T10	87160	0	0	0
T22	164175	0	0	0
T32	0	25848	0	0
T61	38935	0	0	0
T81	0	58559	0	0
T82	0	9051	0	0
T84	0	5692	0	0
T90	0	30309	0	0
T91	0	43714	0	0
T92	0	84753	0	0
T93	0	114201	0	0
T94	0	17745	0	0
T95	64175	0	0	0
T96	41013	0	0	0
T97	149553	0	0	0
T110	0	64079	0	0
T114	0	381	0	0
T172	0	12214	0	0
T173	0	2582	0	0
T174	0	1595	0	0
T175	0	2080	0	0
T176	0	33736	0	0
T177	0	11023	0	0
T178	0	8321	0	0
T179	0	5281	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1999827655	144586443	0	0
T1	20110	5139	0	0
T2	29808	7386	0	0
T3	167404	48717	0	0
T4	4607230	1068864	0	0
T5	59472	0	0	0
T6	3696300	0	0	0
T7	137790	0	0	0
T8	39156	0	0	0
T9	126650	47148	0	0
T10	87160	36236	0	0
T22	54725	0	0	0
T23	0	23483	0	0
T32	0	365810	0	0
T61	23361	2565	0	0
T91	0	87869	0	0
T92	0	135899	0	0
T93	0	193958	0	0
T95	25670	0	0	0
T96	13671	23492	0	0
T97	49851	9854	0	0
T100	0	35234	0	0
T103	0	2886	0	0
T104	0	7781	0	0
T130	0	4535	0	0
T134	0	5069	0	0
T137	0	2311	0	0
T140	0	3112	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1999827655	1995365540	0	0
T1	50275	48845	0	0
T2	49680	48635	0	0
T3	209255	204890	0	0
T4	4607230	4569350	0	0
T5	74340	73065	0	0
T6	3696300	3696080	0	0
T7	137790	136385	0	0
T8	48945	48065	0	0
T9	126650	124640	0	0
T10	87160	85220	0	0