Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.82	97.40	96.15	96.96		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.82	97.40	96.15	96.96		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T60,T127,T128

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T5,T4
1	Covered	T22,T129,T130

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T16,T17,T18

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T67,T131,T132
1	Covered	T67,T131,T132

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T5

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b10001111000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T5,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T5,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T10

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T10

---

FSM Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T5
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T2,T3,T5
ReadWaitSt	252	Covered	T2,T5,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T2,T5
IdleSt->ReadSt	236	Covered	T2,T3,T5
InitSt->ErrorSt	315	Covered	T137,T138,T85
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T103,T104,T134
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T3,T4,T6
ReadSt->ReadWaitSt	252	Covered	T2,T5,T4
ReadWaitSt->ErrorSt	276	Covered	T129,T139,T182
ReadWaitSt->IdleSt	270	Covered	T2,T5,T4
ResetSt->ErrorSt	315	Covered	T67,T68,T69
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T3,T4,T6
CheckFailError	317	Covered	T67,T131,T132
FsmStateError	289	Covered	T1,T2,T5
MacroEccCorrError	221	Covered	T22,T129,T130
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T4,T6,T7
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T3,T4,T6
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T67,T131,T132
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T2,T5
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T129,T130,T60
MacroEccCorrError->NoError	235	Covered	T22,T130,T24
NoError->AccessError	256	Covered	T3,T4,T6
NoError->CheckFailError	317	Covered	T67,T131,T132
NoError->FsmStateError	289	Covered	T1,T2,T5
NoError->MacroEccCorrError	221	Covered	T22,T129,T130

---

Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T60,T127,T128
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T104,T134,T185
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T5
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T5,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T4,T12,T92
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T3,T4,T6
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T22,T129,T130
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T5,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T129,T139,T182
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T5,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T16,T17,T18
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T2,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T2,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T5
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T67,T131,T132
1	0	Covered	T67,T131,T132
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	399965531	399073108	0	0
DigestKnown_A	399965531	399073108	0	0
DigestOffsetMustBeRepresentable_A	1142	1142	0	0
EccErrorState_A	399965531	16245	0	0
ErrorKnown_A	399965531	399073108	0	0
FsmStateKnown_A	399965531	399073108	0	0
InitDoneKnown_A	399965531	399073108	0	0
InitReadLocksPartition_A	399965531	92361372	0	0
InitWriteLocksPartition_A	399965531	92361372	0	0
OffsetMustBeBlockAligned_A	1142	1142	0	0
OtpAddrKnown_A	399965531	399073108	0	0
OtpCmdKnown_A	399965531	399073108	0	0
OtpErrorState_A	399965531	44	0	0
OtpReqKnown_A	399965531	399073108	0	0
OtpSizeKnown_A	399965531	399073108	0	0
OtpWdataKnown_A	399965531	399073108	0	0
ReadLockPropagation_A	399965531	171740558	0	0
SizeMustBeBlockAligned_A	1142	1142	0	0
TlulGntKnown_A	399965531	399073108	0	0
TlulRdataKnown_A	399965531	399073108	0	0
TlulReadOnReadLock_A	399965531	8003	0	0
TlulRerrorKnown_A	399965531	399073108	0	0
TlulRvalidKnown_A	399965531	399073108	0	0
WriteLockPropagation_A	399965531	3113831	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	399965531	36291546	0	0
u_state_regs_A	399965531	399073108	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399965531	399073108	0	0
T1	10055	9769	0	0
T2	9936	9727	0	0
T3	41851	40978	0	0
T4	921446	913870	0	0
T5	14868	14613	0	0
T6	739260	739216	0	0
T7	27558	27277	0	0
T8	9789	9613	0	0
T9	25330	24928	0	0
T10	17432	17044	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399965531	399073108	0	0
T1	10055	9769	0	0
T2	9936	9727	0	0
T3	41851	40978	0	0
T4	921446	913870	0	0
T5	14868	14613	0	0
T6	739260	739216	0	0
T7	27558	27277	0	0
T8	9789	9613	0	0
T9	25330	24928	0	0
T10	17432	17044	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1142	1142	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399965531	16245	0	0
T43	15210	0	0	0
T67	13286	3863	0	0
T68	15494	0	0	0
T110	826113	0	0	0
T114	30137	0	0	0
T131	0	2118	0	0
T132	0	3948	0	0
T136	0	3309	0	0
T141	0	3007	0	0
T142	28920	0	0	0
T143	11017	0	0	0
T144	180918	0	0	0
T145	242897	0	0	0
T146	840965	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399965531	399073108	0	0
T1	10055	9769	0	0
T2	9936	9727	0	0
T3	41851	40978	0	0
T4	921446	913870	0	0
T5	14868	14613	0	0
T6	739260	739216	0	0
T7	27558	27277	0	0
T8	9789	9613	0	0
T9	25330	24928	0	0
T10	17432	17044	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399965531	399073108	0	0
T1	10055	9769	0	0
T2	9936	9727	0	0
T3	41851	40978	0	0
T4	921446	913870	0	0
T5	14868	14613	0	0
T6	739260	739216	0	0
T7	27558	27277	0	0
T8	9789	9613	0	0
T9	25330	24928	0	0
T10	17432	17044	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399965531	399073108	0	0
T1	10055	9769	0	0
T2	9936	9727	0	0
T3	41851	40978	0	0
T4	921446	913870	0	0
T5	14868	14613	0	0
T6	739260	739216	0	0
T7	27558	27277	0	0
T8	9789	9613	0	0
T9	25330	24928	0	0
T10	17432	17044	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399965531	92361372	0	0
T1	10055	2553	0	0
T2	9936	3569	0	0
T3	41851	1366	0	0
T4	921446	296714	0	0
T5	14868	5125	0	0
T6	739260	64142	0	0
T7	27558	14467	0	0
T8	9789	4503	0	0
T9	25330	9739	0	0
T10	17432	6293	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399965531	92361372	0	0
T1	10055	2553	0	0
T2	9936	3569	0	0
T3	41851	1366	0	0
T4	921446	296714	0	0
T5	14868	5125	0	0
T6	739260	64142	0	0
T7	27558	14467	0	0
T8	9789	4503	0	0
T9	25330	9739	0	0
T10	17432	6293	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1142	1142	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399965531	399073108	0	0
T1	10055	9769	0	0
T2	9936	9727	0	0
T3	41851	40978	0	0
T4	921446	913870	0	0
T5	14868	14613	0	0
T6	739260	739216	0	0
T7	27558	27277	0	0
T8	9789	9613	0	0
T9	25330	24928	0	0
T10	17432	17044	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399965531	399073108	0	0
T1	10055	9769	0	0
T2	9936	9727	0	0
T3	41851	40978	0	0
T4	921446	913870	0	0
T5	14868	14613	0	0
T6	739260	739216	0	0
T7	27558	27277	0	0
T8	9789	9613	0	0
T9	25330	24928	0	0
T10	17432	17044	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399965531	44	0	0
T11	105663	0	0	0
T23	33747	0	0	0
T32	256223	0	0	0
T88	0	1	0	0
T98	13325	0	0	0
T99	12647	0	0	0
T104	16032	1	0	0
T129	0	1	0	0
T134	8853	1	0	0
T135	0	1	0	0
T139	0	1	0	0
T140	12236	0	0	0
T167	89611	0	0	0
T168	20699	0	0	0
T182	0	1	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399965531	399073108	0	0
T1	10055	9769	0	0
T2	9936	9727	0	0
T3	41851	40978	0	0
T4	921446	913870	0	0
T5	14868	14613	0	0
T6	739260	739216	0	0
T7	27558	27277	0	0
T8	9789	9613	0	0
T9	25330	24928	0	0
T10	17432	17044	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399965531	399073108	0	0
T1	10055	9769	0	0
T2	9936	9727	0	0
T3	41851	40978	0	0
T4	921446	913870	0	0
T5	14868	14613	0	0
T6	739260	739216	0	0
T7	27558	27277	0	0
T8	9789	9613	0	0
T9	25330	24928	0	0
T10	17432	17044	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399965531	399073108	0	0
T1	10055	9769	0	0
T2	9936	9727	0	0
T3	41851	40978	0	0
T4	921446	913870	0	0
T5	14868	14613	0	0
T6	739260	739216	0	0
T7	27558	27277	0	0
T8	9789	9613	0	0
T9	25330	24928	0	0
T10	17432	17044	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399965531	171740558	0	0
T3	41851	248	0	0
T4	921446	264849	0	0
T5	14868	0	0	0
T6	739260	193469	0	0
T7	27558	16936	0	0
T8	9789	0	0	0
T9	25330	1302	0	0
T10	17432	3283	0	0
T22	0	3433	0	0
T61	7787	0	0	0
T95	12835	0	0	0
T96	0	3364	0	0
T97	0	42673	0	0
T167	0	71575	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1142	1142	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399965531	399073108	0	0
T1	10055	9769	0	0
T2	9936	9727	0	0
T3	41851	40978	0	0
T4	921446	913870	0	0
T5	14868	14613	0	0
T6	739260	739216	0	0
T7	27558	27277	0	0
T8	9789	9613	0	0
T9	25330	24928	0	0
T10	17432	17044	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399965531	399073108	0	0
T1	10055	9769	0	0
T2	9936	9727	0	0
T3	41851	40978	0	0
T4	921446	913870	0	0
T5	14868	14613	0	0
T6	739260	739216	0	0
T7	27558	27277	0	0
T8	9789	9613	0	0
T9	25330	24928	0	0
T10	17432	17044	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399965531	8003	0	0
T1	10055	4	0	0
T2	9936	3	0	0
T3	41851	1	0	0
T4	921446	86	0	0
T5	14868	0	0	0
T6	739260	60	0	0
T7	27558	8	0	0
T8	9789	0	0	0
T9	25330	7	0	0
T10	17432	21	0	0
T22	0	11	0	0
T96	0	2	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399965531	399073108	0	0
T1	10055	9769	0	0
T2	9936	9727	0	0
T3	41851	40978	0	0
T4	921446	913870	0	0
T5	14868	14613	0	0
T6	739260	739216	0	0
T7	27558	27277	0	0
T8	9789	9613	0	0
T9	25330	24928	0	0
T10	17432	17044	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399965531	399073108	0	0
T1	10055	9769	0	0
T2	9936	9727	0	0
T3	41851	40978	0	0
T4	921446	913870	0	0
T5	14868	14613	0	0
T6	739260	739216	0	0
T7	27558	27277	0	0
T8	9789	9613	0	0
T9	25330	24928	0	0
T10	17432	17044	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399965531	3113831	0	0
T4	921446	9360	0	0
T6	739260	0	0	0
T7	27558	0	0	0
T9	25330	0	0	0
T10	17432	0	0	0
T22	54725	0	0	0
T32	0	4743	0	0
T61	7787	0	0	0
T81	0	12391	0	0
T82	0	2145	0	0
T84	0	790	0	0
T91	0	16399	0	0
T92	0	13768	0	0
T93	0	23060	0	0
T94	0	7500	0	0
T95	12835	0	0	0
T96	13671	0	0	0
T97	49851	0	0	0
T172	0	6107	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399965531	36291546	0	0
T3	41851	16154	0	0
T4	921446	242913	0	0
T5	14868	0	0	0
T6	739260	0	0	0
T7	27558	0	0	0
T8	9789	0	0	0
T9	25330	0	0	0
T10	17432	9008	0	0
T23	0	3742	0	0
T32	0	66461	0	0
T61	7787	0	0	0
T95	12835	0	0	0
T96	0	5839	0	0
T97	0	2438	0	0
T100	0	17566	0	0
T104	0	3871	0	0
T134	0	2515	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399965531	399073108	0	0
T1	10055	9769	0	0
T2	9936	9727	0	0
T3	41851	40978	0	0
T4	921446	913870	0	0
T5	14868	14613	0	0
T6	739260	739216	0	0
T7	27558	27277	0	0
T8	9789	9613	0	0
T9	25330	24928	0	0
T10	17432	17044	0	0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T70,T37,T44

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T5,T4,T6
1	Covered	T22,T129,T130

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T16,T17,T18

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T67,T131,T136
1	Covered	T67,T131,T136

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T5

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T4,T6

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T8,T4
1	1	Covered	T5,T4,T6

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b11001010000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T5,T8

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T5,T4,T6
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T5,T4,T6
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T61,T96

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T61,T96

---

FSM Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T5
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T5,T4,T6
ReadWaitSt	252	Covered	T5,T4,T6
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T2,T5
IdleSt->ReadSt	236	Covered	T5,T4,T6
InitSt->ErrorSt	315	Covered	T103,T140,T137
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T61,T104,T134
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T4,T6,T9
ReadSt->ReadWaitSt	252	Covered	T5,T4,T6
ReadWaitSt->ErrorSt	276	Covered	T129,T130,T188
ReadWaitSt->IdleSt	270	Covered	T5,T4,T6
ResetSt->ErrorSt	315	Covered	T67,T68,T69
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T4,T6,T9
CheckFailError	317	Covered	T67,T131,T136
FsmStateError	289	Covered	T1,T2,T5
MacroEccCorrError	221	Covered	T22,T129,T130
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T4,T6,T7
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T4,T6,T9
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T67,T131,T136
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T2,T5
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T129,T130,T139
MacroEccCorrError->NoError	235	Covered	T22,T39,T24
NoError->AccessError	256	Covered	T4,T6,T9
NoError->CheckFailError	317	Covered	T67,T131,T136
NoError->FsmStateError	289	Covered	T1,T2,T5
NoError->MacroEccCorrError	221	Covered	T22,T129,T130

---

Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T4,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T4,T6

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T4,T6

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T61,T96
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T70,T37,T44
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T61,T127,T128
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T5,T4,T6
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T5,T4,T6
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T4,T6,T32
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T4,T6,T9
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T22,T129,T130
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T5,T4,T6
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T129,T130,T188
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T5,T4,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T16,T17,T18
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T8,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T8,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T5
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T67,T131,T136
1	0	Covered	T67,T131,T136
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T5,T8
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	399965531	399073108	0	0
DigestKnown_A	399965531	399073108	0	0
DigestOffsetMustBeRepresentable_A	1142	1142	0	0
EccErrorState_A	399965531	14882	0	0
ErrorKnown_A	399965531	399073108	0	0
FsmStateKnown_A	399965531	399073108	0	0
InitDoneKnown_A	399965531	399073108	0	0
InitReadLocksPartition_A	399965531	92545819	0	0
InitWriteLocksPartition_A	399965531	92545819	0	0
OffsetMustBeBlockAligned_A	1142	1142	0	0
OtpAddrKnown_A	399965531	399073108	0	0
OtpCmdKnown_A	399965531	399073108	0	0
OtpErrorState_A	399965531	45	0	0
OtpReqKnown_A	399965531	399073108	0	0
OtpSizeKnown_A	399965531	399073108	0	0
OtpWdataKnown_A	399965531	399073108	0	0
ReadLockPropagation_A	399965531	172385104	0	0
SizeMustBeBlockAligned_A	1142	1142	0	0
TlulGntKnown_A	399965531	399073108	0	0
TlulRdataKnown_A	399965531	399073108	0	0
TlulReadOnReadLock_A	399965531	7750	0	0
TlulRerrorKnown_A	399965531	399073108	0	0
TlulRvalidKnown_A	399965531	399073108	0	0
WriteLockPropagation_A	399965531	925326	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	399965531	15006060	0	0
u_state_regs_A	399965531	399073108	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399965531	399073108	0	0
T1	10055	9769	0	0
T2	9936	9727	0	0
T3	41851	40978	0	0
T4	921446	913870	0	0
T5	14868	14613	0	0
T6	739260	739216	0	0
T7	27558	27277	0	0
T8	9789	9613	0	0
T9	25330	24928	0	0
T10	17432	17044	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399965531	399073108	0	0
T1	10055	9769	0	0
T2	9936	9727	0	0
T3	41851	40978	0	0
T4	921446	913870	0	0
T5	14868	14613	0	0
T6	739260	739216	0	0
T7	27558	27277	0	0
T8	9789	9613	0	0
T9	25330	24928	0	0
T10	17432	17044	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1142	1142	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399965531	14882	0	0
T43	15210	0	0	0
T67	13286	3863	0	0
T68	15494	0	0	0
T110	826113	0	0	0
T114	30137	0	0	0
T131	0	2118	0	0
T133	0	2585	0	0
T136	0	3309	0	0
T141	0	3007	0	0
T142	28920	0	0	0
T143	11017	0	0	0
T144	180918	0	0	0
T145	242897	0	0	0
T146	840965	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399965531	399073108	0	0
T1	10055	9769	0	0
T2	9936	9727	0	0
T3	41851	40978	0	0
T4	921446	913870	0	0
T5	14868	14613	0	0
T6	739260	739216	0	0
T7	27558	27277	0	0
T8	9789	9613	0	0
T9	25330	24928	0	0
T10	17432	17044	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399965531	399073108	0	0
T1	10055	9769	0	0
T2	9936	9727	0	0
T3	41851	40978	0	0
T4	921446	913870	0	0
T5	14868	14613	0	0
T6	739260	739216	0	0
T7	27558	27277	0	0
T8	9789	9613	0	0
T9	25330	24928	0	0
T10	17432	17044	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399965531	399073108	0	0
T1	10055	9769	0	0
T2	9936	9727	0	0
T3	41851	40978	0	0
T4	921446	913870	0	0
T5	14868	14613	0	0
T6	739260	739216	0	0
T7	27558	27277	0	0
T8	9789	9613	0	0
T9	25330	24928	0	0
T10	17432	17044	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399965531	92545819	0	0
T1	10055	2587	0	0
T2	9936	3603	0	0
T3	41851	1536	0	0
T4	921446	298278	0	0
T5	14868	5176	0	0
T6	739260	64380	0	0
T7	27558	14518	0	0
T8	9789	4554	0	0
T9	25330	9841	0	0
T10	17432	6344	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399965531	92545819	0	0
T1	10055	2587	0	0
T2	9936	3603	0	0
T3	41851	1536	0	0
T4	921446	298278	0	0
T5	14868	5176	0	0
T6	739260	64380	0	0
T7	27558	14518	0	0
T8	9789	4554	0	0
T9	25330	9841	0	0
T10	17432	6344	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1142	1142	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399965531	399073108	0	0
T1	10055	9769	0	0
T2	9936	9727	0	0
T3	41851	40978	0	0
T4	921446	913870	0	0
T5	14868	14613	0	0
T6	739260	739216	0	0
T7	27558	27277	0	0
T8	9789	9613	0	0
T9	25330	24928	0	0
T10	17432	17044	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399965531	399073108	0	0
T1	10055	9769	0	0
T2	9936	9727	0	0
T3	41851	40978	0	0
T4	921446	913870	0	0
T5	14868	14613	0	0
T6	739260	739216	0	0
T7	27558	27277	0	0
T8	9789	9613	0	0
T9	25330	24928	0	0
T10	17432	17044	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399965531	45	0	0
T22	54725	0	0	0
T61	7787	1	0	0
T95	12835	0	0	0
T96	13671	0	0	0
T97	49851	0	0	0
T98	13325	0	0	0
T103	11410	0	0	0
T104	16032	0	0	0
T127	0	1	0	0
T128	0	1	0	0
T129	0	1	0	0
T130	0	1	0	0
T167	89611	0	0	0
T168	20699	0	0	0
T188	0	1	0	0
T189	0	1	0	0
T190	0	1	0	0
T191	0	1	0	0
T192	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399965531	399073108	0	0
T1	10055	9769	0	0
T2	9936	9727	0	0
T3	41851	40978	0	0
T4	921446	913870	0	0
T5	14868	14613	0	0
T6	739260	739216	0	0
T7	27558	27277	0	0
T8	9789	9613	0	0
T9	25330	24928	0	0
T10	17432	17044	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399965531	399073108	0	0
T1	10055	9769	0	0
T2	9936	9727	0	0
T3	41851	40978	0	0
T4	921446	913870	0	0
T5	14868	14613	0	0
T6	739260	739216	0	0
T7	27558	27277	0	0
T8	9789	9613	0	0
T9	25330	24928	0	0
T10	17432	17044	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399965531	399073108	0	0
T1	10055	9769	0	0
T2	9936	9727	0	0
T3	41851	40978	0	0
T4	921446	913870	0	0
T5	14868	14613	0	0
T6	739260	739216	0	0
T7	27558	27277	0	0
T8	9789	9613	0	0
T9	25330	24928	0	0
T10	17432	17044	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399965531	172385104	0	0
T3	41851	2688	0	0
T4	921446	257416	0	0
T5	14868	0	0	0
T6	739260	198193	0	0
T7	27558	16934	0	0
T8	9789	0	0	0
T9	25330	3249	0	0
T10	17432	2821	0	0
T22	0	2765	0	0
T61	7787	0	0	0
T95	12835	0	0	0
T96	0	3362	0	0
T97	0	41616	0	0
T167	0	71563	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1142	1142	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399965531	399073108	0	0
T1	10055	9769	0	0
T2	9936	9727	0	0
T3	41851	40978	0	0
T4	921446	913870	0	0
T5	14868	14613	0	0
T6	739260	739216	0	0
T7	27558	27277	0	0
T8	9789	9613	0	0
T9	25330	24928	0	0
T10	17432	17044	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399965531	399073108	0	0
T1	10055	9769	0	0
T2	9936	9727	0	0
T3	41851	40978	0	0
T4	921446	913870	0	0
T5	14868	14613	0	0
T6	739260	739216	0	0
T7	27558	27277	0	0
T8	9789	9613	0	0
T9	25330	24928	0	0
T10	17432	17044	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399965531	7750	0	0
T1	10055	7	0	0
T2	9936	0	0	0
T3	41851	0	0	0
T4	921446	64	0	0
T5	14868	0	0	0
T6	739260	64	0	0
T7	27558	12	0	0
T8	9789	3	0	0
T9	25330	10	0	0
T10	17432	28	0	0
T22	0	12	0	0
T96	0	3	0	0
T97	0	10	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399965531	399073108	0	0
T1	10055	9769	0	0
T2	9936	9727	0	0
T3	41851	40978	0	0
T4	921446	913870	0	0
T5	14868	14613	0	0
T6	739260	739216	0	0
T7	27558	27277	0	0
T8	9789	9613	0	0
T9	25330	24928	0	0
T10	17432	17044	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399965531	399073108	0	0
T1	10055	9769	0	0
T2	9936	9727	0	0
T3	41851	40978	0	0
T4	921446	913870	0	0
T5	14868	14613	0	0
T6	739260	739216	0	0
T7	27558	27277	0	0
T8	9789	9613	0	0
T9	25330	24928	0	0
T10	17432	17044	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399965531	925326	0	0
T4	921446	19857	0	0
T6	739260	0	0	0
T7	27558	0	0	0
T9	25330	0	0	0
T10	17432	0	0	0
T22	54725	0	0	0
T32	0	4743	0	0
T61	7787	0	0	0
T91	0	4810	0	0
T92	0	25360	0	0
T93	0	22092	0	0
T94	0	10245	0	0
T95	12835	0	0	0
T96	13671	0	0	0
T97	49851	0	0	0
T110	0	27498	0	0
T174	0	1595	0	0
T175	0	2080	0	0
T177	0	11023	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399965531	15006060	0	0
T4	921446	143668	0	0
T6	739260	0	0	0
T7	27558	0	0	0
T9	25330	0	0	0
T10	17432	0	0	0
T22	54725	0	0	0
T23	0	19741	0	0
T32	0	55728	0	0
T61	7787	2565	0	0
T81	0	45968	0	0
T91	0	87869	0	0
T92	0	135899	0	0
T93	0	193958	0	0
T95	12835	0	0	0
T96	13671	5805	0	0
T97	49851	0	0	0
T130	0	4535	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399965531	399073108	0	0
T1	10055	9769	0	0
T2	9936	9727	0	0
T3	41851	40978	0	0
T4	921446	913870	0	0
T5	14868	14613	0	0
T6	739260	739216	0	0
T7	27558	27277	0	0
T8	9789	9613	0	0
T9	25330	24928	0	0
T10	17432	17044	0	0