Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
32.54	21.48	30.76	13.06	0.00	21.87	99.69	40.96

Total tests in report: 174

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
31.00	31.00	20.77	20.77	24.48	24.48	35.30	35.30	0.00	0.00	20.81	20.81	93.00	93.00	22.66	22.66	/workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.1772968327
33.56	2.55	21.17	0.39	28.47	3.99	35.50	0.20	0.00	0.00	21.20	0.38	94.40	1.40	34.17	11.51	/workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.3652890042
34.21	0.65	21.30	0.13	29.68	1.21	35.52	0.02	0.00	0.00	21.87	0.67	96.58	2.18	34.52	0.36	/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.2633631010
34.67	0.46	21.30	0.00	29.93	0.25	35.61	0.09	0.00	0.00	21.87	0.00	96.73	0.16	37.24	2.72	/workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.2887839337
35.07	0.40	21.30	0.00	29.93	0.00	35.61	0.00	0.00	0.00	21.87	0.00	98.60	1.87	38.17	0.93	/workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.299927015
35.32	0.26	21.30	0.00	29.95	0.03	35.61	0.00	0.00	0.00	21.87	0.00	99.38	0.78	39.17	1.00	/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.4143773533
35.42	0.10	21.30	0.00	30.03	0.08	35.65	0.04	0.00	0.00	21.87	0.00	99.38	0.00	39.74	0.57	/workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.867387087
35.49	0.06	21.30	0.00	30.20	0.18	35.78	0.13	0.00	0.00	21.87	0.00	99.38	0.00	39.89	0.14	/workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.3906826737
35.55	0.06	21.30	0.00	30.25	0.05	35.78	0.00	0.00	0.00	21.87	0.00	99.69	0.31	39.96	0.07	/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.1643347812
35.60	0.05	21.30	0.00	30.30	0.05	35.78	0.00	0.00	0.00	21.87	0.00	99.69	0.00	40.24	0.29	/workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.401747395
35.64	0.04	21.30	0.00	30.33	0.03	35.78	0.00	0.00	0.00	21.87	0.00	99.69	0.00	40.53	0.29	/workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.2691841498
35.68	0.04	21.30	0.00	30.45	0.13	35.78	0.00	0.00	0.00	21.87	0.00	99.69	0.00	40.67	0.14	/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.2809778169
35.70	0.02	21.33	0.03	30.48	0.03	35.78	0.00	0.00	0.00	21.87	0.00	99.69	0.00	40.74	0.07	/workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.2288221746
35.72	0.02	21.33	0.00	30.53	0.05	35.78	0.00	0.00	0.00	21.87	0.00	99.69	0.00	40.81	0.07	/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.178145810
35.73	0.01	21.38	0.05	30.58	0.05	35.78	0.00	0.00	0.00	21.87	0.00	99.69	0.00	40.81	0.00	/workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.1188255040
35.74	0.01	21.38	0.00	30.66	0.08	35.78	0.00	0.00	0.00	21.87	0.00	99.69	0.00	40.81	0.00	/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.680453651
35.75	0.01	21.38	0.00	30.66	0.00	35.78	0.00	0.00	0.00	21.87	0.00	99.69	0.00	40.89	0.07	/workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.343136742
35.76	0.01	21.38	0.00	30.66	0.00	35.78	0.00	0.00	0.00	21.87	0.00	99.69	0.00	40.96	0.07	/workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.1082777520
35.77	0.01	21.38	0.00	30.71	0.05	35.78	0.00	0.00	0.00	21.87	0.00	99.69	0.00	40.96	0.00	/workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.2679700575
35.77	0.01	21.40	0.02	30.73	0.03	35.78	0.00	0.00	0.00	21.87	0.00	99.69	0.00	40.96	0.00	/workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.66279756
35.78	0.01	21.40	0.00	30.76	0.03	35.78	0.00	0.00	0.00	21.87	0.00	99.69	0.00	40.96	0.00	/workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.235798838
35.78	0.01	21.41	0.02	30.76	0.00	35.78	0.00	0.00	0.00	21.87	0.00	99.69	0.00	40.96	0.00	/workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.4248717374
35.78	0.01	21.43	0.02	30.76	0.00	35.78	0.00	0.00	0.00	21.87	0.00	99.69	0.00	40.96	0.00	/workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.2281086767
35.78	0.01	21.44	0.02	30.76	0.00	35.78	0.00	0.00	0.00	21.87	0.00	99.69	0.00	40.96	0.00	/workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.2210978896
35.79	0.01	21.46	0.02	30.76	0.00	35.78	0.00	0.00	0.00	21.87	0.00	99.69	0.00	40.96	0.00	/workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.37936549
35.79	0.01	21.48	0.02	30.76	0.00	35.78	0.00	0.00	0.00	21.87	0.00	99.69	0.00	40.96	0.00	/workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.338554219

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.2931120257
/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.2772939990
/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.1191337760
/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.138962892
/workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.3486828652
/workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.349904802
/workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.3886726637
/workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.869963595
/workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.3408070269
/workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.722395170
/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.1457144974
/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.1757591948
/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.3921430042
/workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.1445803957
/workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.1642764244
/workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.4140341213
/workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.1564423428
/workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.1088826868
/workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.602852674
/workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.3847295524
/workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.990774599
/workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.2829688573
/workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.3010721240
/workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.2343927738
/workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.3086042933
/workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.1823031452
/workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.1104675590
/workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.1085567
/workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.2783214753
/workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.248837580
/workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.2297634343
/workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.1185367815
/workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.2409872757
/workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.1730624983
/workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.208719707
/workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.1384782450
/workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.1382409272
/workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.220136157
/workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.1585309131
/workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.3651415228
/workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.1490437702
/workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.2964097463
/workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.2745840186
/workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.3841819827
/workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.436819891
/workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.3609650317
/workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.842525493
/workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.602687170
/workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.1566364967
/workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.1570986883
/workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.3655015845
/workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.3385786893
/workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.888176945
/workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.875397848
/workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.3558237887
/workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.411375971
/workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.1626910983
/workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.1644017339
/workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.1490333984
/workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.3719936843
/workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.2911917386
/workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.1184459582
/workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.4076563462
/workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.3673856464
/workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.1921982999
/workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.1638293805
/workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.3317685774
/workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.3380045000
/workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.1851701202
/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.305222194
/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.638977041
/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.3950983431
/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.1022635192
/workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.2170530333
/workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.2505447124
/workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.2861260421
/workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.1562924056
/workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.538585342
/workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.3486967915
/workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.338331477
/workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.1656297004
/workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.2497982745
/workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.344909759
/workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.549831244
/workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.2577088327
/workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.3522625622
/workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.1646856752
/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.2769786310
/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.2006453177
/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.756319379
/workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.2378852877
/workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.2295265384
/workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.2814371925
/workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.4163120469
/workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.595836326
/workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.322063675
/workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.3779694962
/workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.1584664147
/workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.3728174402
/workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.1575856553
/workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.3178715962
/workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.521463475
/workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.3916558005
/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.3538785286
/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.2335099176
/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.677736601
/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.689018223
/workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.1301643797
/workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.1461152349
/workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.3048880085
/workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.624277350
/workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.1660544755
/workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.869398259
/workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.3844285990
/workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.2156159083
/workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.2161617689
/workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.850029794
/workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.3491893825
/workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.1729251821
/workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.3590764423
/workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.1902444651
/workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.930969389
/workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.229493445
/workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.2693784023
/workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.4016902667
/workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.3754936862
/workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.2153295649
/workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.4146295377
/workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.1750117946
/workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.1045038906
/workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.262007096
/workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.2610534286
/workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.1747137179
/workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.3935369842
/workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.2104970065
/workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.279981635
/workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.3963987192
/workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.1045572363
/workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.3821551137
/workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.1901156097
/workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.544973368
/workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.2899195762
/workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.557539011
/workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.825894291
/workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.1186863596
/workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.2894410431
/workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.532468194
/workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.1818478821

Total test records in report: 174

tests.html | tests1.html | tests2.html

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.1575856553	Mar 14 01:08:11 PM PDT 24	Mar 14 01:08:12 PM PDT 24	43896364 ps
T2	/workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.1185367815	Mar 14 01:08:00 PM PDT 24	Mar 14 01:08:02 PM PDT 24	78883364 ps
T3	/workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.2577088327	Mar 14 01:08:11 PM PDT 24	Mar 14 01:08:12 PM PDT 24	57416570 ps
T15	/workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.4140341213	Mar 14 01:06:55 PM PDT 24	Mar 14 01:06:57 PM PDT 24	142729469 ps
T4	/workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.2153295649	Mar 14 01:07:42 PM PDT 24	Mar 14 01:07:59 PM PDT 24	10330947145 ps
T9	/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.4143773533	Mar 14 01:06:54 PM PDT 24	Mar 14 01:07:05 PM PDT 24	791109630 ps
T5	/workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.1490333984	Mar 14 01:07:56 PM PDT 24	Mar 14 01:07:59 PM PDT 24	265896910 ps
T10	/workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.3655015845	Mar 14 01:08:00 PM PDT 24	Mar 14 01:08:02 PM PDT 24	41713315 ps
T12	/workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.1570986883	Mar 14 01:08:01 PM PDT 24	Mar 14 01:08:04 PM PDT 24	574295695 ps
T6	/workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.1772968327	Mar 14 01:07:57 PM PDT 24	Mar 14 01:08:10 PM PDT 24	10272413237 ps
T8	/workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.349904802	Mar 14 01:06:52 PM PDT 24	Mar 14 01:06:54 PM PDT 24	127108711 ps
T7	/workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.3652890042	Mar 14 01:07:39 PM PDT 24	Mar 14 01:07:43 PM PDT 24	98625301 ps
T16	/workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.3385786893	Mar 14 01:07:59 PM PDT 24	Mar 14 01:08:02 PM PDT 24	97729928 ps
T11	/workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.401747395	Mar 14 01:08:17 PM PDT 24	Mar 14 01:08:18 PM PDT 24	68226628 ps
T26	/workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.2295265384	Mar 14 01:07:10 PM PDT 24	Mar 14 01:07:12 PM PDT 24	70431481 ps
T19	/workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.1045572363	Mar 14 01:07:41 PM PDT 24	Mar 14 01:07:45 PM PDT 24	1194745411 ps
T27	/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.2772939990	Mar 14 01:06:52 PM PDT 24	Mar 14 01:07:01 PM PDT 24	861395939 ps
T40	/workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.1902444651	Mar 14 01:08:17 PM PDT 24	Mar 14 01:08:18 PM PDT 24	157907236 ps
T29	/workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.1750117946	Mar 14 01:07:38 PM PDT 24	Mar 14 01:07:40 PM PDT 24	147170776 ps
T49	/workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.3728174402	Mar 14 01:08:10 PM PDT 24	Mar 14 01:08:12 PM PDT 24	577075889 ps
T13	/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.2633631010	Mar 14 01:07:05 PM PDT 24	Mar 14 01:07:08 PM PDT 24	95448995 ps
T30	/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.3921430042	Mar 14 01:06:54 PM PDT 24	Mar 14 01:06:57 PM PDT 24	679888570 ps
T31	/workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.1823031452	Mar 14 01:07:42 PM PDT 24	Mar 14 01:07:44 PM PDT 24	538579376 ps
T50	/workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.2887839337	Mar 14 01:08:17 PM PDT 24	Mar 14 01:08:19 PM PDT 24	43344185 ps
T20	/workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.3754936862	Mar 14 01:07:38 PM PDT 24	Mar 14 01:07:41 PM PDT 24	189148187 ps
T21	/workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.1188255040	Mar 14 01:06:51 PM PDT 24	Mar 14 01:06:58 PM PDT 24	449212182 ps
T51	/workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.1656297004	Mar 14 01:08:00 PM PDT 24	Mar 14 01:08:02 PM PDT 24	584189849 ps
T22	/workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.2610534286	Mar 14 01:07:42 PM PDT 24	Mar 14 01:07:47 PM PDT 24	131768326 ps
T69	/workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.1445803957	Mar 14 01:06:54 PM PDT 24	Mar 14 01:06:56 PM PDT 24	41587201 ps
T70	/workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.3486967915	Mar 14 01:07:59 PM PDT 24	Mar 14 01:08:01 PM PDT 24	578550070 ps
T18	/workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.299927015	Mar 14 01:07:40 PM PDT 24	Mar 14 01:07:44 PM PDT 24	128433778 ps
T14	/workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.1566364967	Mar 14 01:07:59 PM PDT 24	Mar 14 01:08:03 PM PDT 24	106679620 ps
T62	/workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.3522625622	Mar 14 01:08:11 PM PDT 24	Mar 14 01:08:13 PM PDT 24	56885140 ps
T23	/workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.2288221746	Mar 14 01:08:00 PM PDT 24	Mar 14 01:08:03 PM PDT 24	330294826 ps
T52	/workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.1730624983	Mar 14 01:07:57 PM PDT 24	Mar 14 01:07:59 PM PDT 24	75525873 ps
T32	/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.1457144974	Mar 14 01:06:51 PM PDT 24	Mar 14 01:06:55 PM PDT 24	278571050 ps
T63	/workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.538585342	Mar 14 01:08:00 PM PDT 24	Mar 14 01:08:02 PM PDT 24	37146867 ps
T17	/workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.1818478821	Mar 14 01:07:39 PM PDT 24	Mar 14 01:08:00 PM PDT 24	4864497891 ps
T28	/workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.1660544755	Mar 14 01:07:22 PM PDT 24	Mar 14 01:07:34 PM PDT 24	662539939 ps
T24	/workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.4248717374	Mar 14 01:06:53 PM PDT 24	Mar 14 01:06:57 PM PDT 24	114092541 ps
T84	/workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.1104675590	Mar 14 01:07:40 PM PDT 24	Mar 14 01:07:42 PM PDT 24	39545437 ps
T25	/workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.3906826737	Mar 14 01:07:08 PM PDT 24	Mar 14 01:07:12 PM PDT 24	1532869788 ps
T33	/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.2769786310	Mar 14 01:07:20 PM PDT 24	Mar 14 01:07:26 PM PDT 24	273931928 ps
T53	/workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.1626910983	Mar 14 01:07:59 PM PDT 24	Mar 14 01:08:02 PM PDT 24	138442461 ps
T85	/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.677736601	Mar 14 01:07:39 PM PDT 24	Mar 14 01:07:42 PM PDT 24	75130416 ps
T72	/workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.888176945	Mar 14 01:07:59 PM PDT 24	Mar 14 01:08:06 PM PDT 24	593133374 ps
T54	/workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.1085567	Mar 14 01:07:39 PM PDT 24	Mar 14 01:07:42 PM PDT 24	105795822 ps
T86	/workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.2894410431	Mar 14 01:07:41 PM PDT 24	Mar 14 01:07:43 PM PDT 24	45815879 ps
T87	/workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.3178715962	Mar 14 01:08:12 PM PDT 24	Mar 14 01:08:14 PM PDT 24	44628044 ps
T78	/workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.867387087	Mar 14 01:06:51 PM PDT 24	Mar 14 01:07:13 PM PDT 24	4566135568 ps
T34	/workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.3847295524	Mar 14 01:07:39 PM PDT 24	Mar 14 01:07:41 PM PDT 24	80248842 ps
T57	/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.1757591948	Mar 14 01:06:52 PM PDT 24	Mar 14 01:06:55 PM PDT 24	168507267 ps
T35	/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.178145810	Mar 14 01:06:54 PM PDT 24	Mar 14 01:06:56 PM PDT 24	98586398 ps
T58	/workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.3673856464	Mar 14 01:08:02 PM PDT 24	Mar 14 01:08:07 PM PDT 24	1723170835 ps
T65	/workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.2814371925	Mar 14 01:07:05 PM PDT 24	Mar 14 01:07:07 PM PDT 24	63198491 ps
T36	/workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.1585309131	Mar 14 01:08:00 PM PDT 24	Mar 14 01:08:02 PM PDT 24	131322446 ps
T66	/workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.2505447124	Mar 14 01:07:05 PM PDT 24	Mar 14 01:07:06 PM PDT 24	67299958 ps
T67	/workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.1901156097	Mar 14 01:07:41 PM PDT 24	Mar 14 01:07:45 PM PDT 24	204139583 ps
T37	/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.756319379	Mar 14 01:07:09 PM PDT 24	Mar 14 01:07:10 PM PDT 24	73169292 ps
T55	/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.689018223	Mar 14 01:07:21 PM PDT 24	Mar 14 01:07:23 PM PDT 24	76422009 ps
T68	/workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.2497982745	Mar 14 01:08:00 PM PDT 24	Mar 14 01:08:02 PM PDT 24	68236735 ps
T88	/workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.1301643797	Mar 14 01:07:21 PM PDT 24	Mar 14 01:07:22 PM PDT 24	43184918 ps
T56	/workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.1562924056	Mar 14 01:07:10 PM PDT 24	Mar 14 01:07:13 PM PDT 24	1461443293 ps
T38	/workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.3558237887	Mar 14 01:07:58 PM PDT 24	Mar 14 01:08:00 PM PDT 24	63853781 ps
T77	/workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.624277350	Mar 14 01:07:21 PM PDT 24	Mar 14 01:07:26 PM PDT 24	1437149149 ps
T73	/workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.3408070269	Mar 14 01:06:51 PM PDT 24	Mar 14 01:06:55 PM PDT 24	92837820 ps
T79	/workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.1088826868	Mar 14 01:06:54 PM PDT 24	Mar 14 01:07:14 PM PDT 24	1399919819 ps
T89	/workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.3844285990	Mar 14 01:08:17 PM PDT 24	Mar 14 01:08:18 PM PDT 24	40552846 ps
T90	/workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.3590764423	Mar 14 01:08:11 PM PDT 24	Mar 14 01:08:13 PM PDT 24	143382114 ps
T91	/workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.850029794	Mar 14 01:08:16 PM PDT 24	Mar 14 01:08:18 PM PDT 24	141117957 ps
T39	/workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.1921982999	Mar 14 01:07:59 PM PDT 24	Mar 14 01:08:00 PM PDT 24	39413077 ps
T92	/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.1191337760	Mar 14 01:06:53 PM PDT 24	Mar 14 01:06:58 PM PDT 24	1624638428 ps
T71	/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.2809778169	Mar 14 01:07:22 PM PDT 24	Mar 14 01:07:24 PM PDT 24	106268625 ps
T93	/workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.1638293805	Mar 14 01:08:01 PM PDT 24	Mar 14 01:08:02 PM PDT 24	152715773 ps
T41	/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.2335099176	Mar 14 01:07:21 PM PDT 24	Mar 14 01:07:28 PM PDT 24	131177997 ps
T94	/workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.411375971	Mar 14 01:07:59 PM PDT 24	Mar 14 01:08:00 PM PDT 24	36609090 ps
T95	/workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.3935369842	Mar 14 01:07:41 PM PDT 24	Mar 14 01:07:45 PM PDT 24	1164205342 ps
T81	/workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.248837580	Mar 14 01:07:40 PM PDT 24	Mar 14 01:07:51 PM PDT 24	1083602075 ps
T96	/workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.1184459582	Mar 14 01:08:01 PM PDT 24	Mar 14 01:08:04 PM PDT 24	1026662178 ps
T97	/workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.322063675	Mar 14 01:08:17 PM PDT 24	Mar 14 01:08:18 PM PDT 24	584273897 ps
T42	/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.680453651	Mar 14 01:07:09 PM PDT 24	Mar 14 01:07:12 PM PDT 24	193353967 ps
T98	/workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.842525493	Mar 14 01:07:57 PM PDT 24	Mar 14 01:08:01 PM PDT 24	460925188 ps
T99	/workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.2156159083	Mar 14 01:08:11 PM PDT 24	Mar 14 01:08:13 PM PDT 24	47660865 ps
T100	/workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.3380045000	Mar 14 01:07:59 PM PDT 24	Mar 14 01:08:05 PM PDT 24	103703093 ps
T101	/workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.521463475	Mar 14 01:08:11 PM PDT 24	Mar 14 01:08:13 PM PDT 24	144718040 ps
T102	/workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.208719707	Mar 14 01:07:59 PM PDT 24	Mar 14 01:08:02 PM PDT 24	139164483 ps
T103	/workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.1461152349	Mar 14 01:07:21 PM PDT 24	Mar 14 01:07:23 PM PDT 24	40572232 ps
T59	/workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.3841819827	Mar 14 01:07:58 PM PDT 24	Mar 14 01:08:01 PM PDT 24	154434197 ps
T104	/workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.4016902667	Mar 14 01:07:40 PM PDT 24	Mar 14 01:07:42 PM PDT 24	70214165 ps
T105	/workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.2899195762	Mar 14 01:07:41 PM PDT 24	Mar 14 01:07:42 PM PDT 24	69929441 ps
T106	/workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.602852674	Mar 14 01:07:40 PM PDT 24	Mar 14 01:07:45 PM PDT 24	1640761375 ps
T107	/workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.4163120469	Mar 14 01:07:20 PM PDT 24	Mar 14 01:07:23 PM PDT 24	92428095 ps
T108	/workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.1186863596	Mar 14 01:07:40 PM PDT 24	Mar 14 01:07:42 PM PDT 24	51456374 ps
T60	/workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.930969389	Mar 14 01:07:39 PM PDT 24	Mar 14 01:07:42 PM PDT 24	181045548 ps
T109	/workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.544973368	Mar 14 01:07:39 PM PDT 24	Mar 14 01:07:40 PM PDT 24	63681433 ps
T110	/workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.1564423428	Mar 14 01:06:52 PM PDT 24	Mar 14 01:06:55 PM PDT 24	177256111 ps
T111	/workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.875397848	Mar 14 01:07:59 PM PDT 24	Mar 14 01:08:03 PM PDT 24	105002125 ps
T112	/workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.262007096	Mar 14 01:07:38 PM PDT 24	Mar 14 01:07:41 PM PDT 24	958442405 ps
T113	/workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.338554219	Mar 14 01:07:41 PM PDT 24	Mar 14 01:07:44 PM PDT 24	64547650 ps
T114	/workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.2409872757	Mar 14 01:08:00 PM PDT 24	Mar 14 01:08:02 PM PDT 24	38782907 ps
T115	/workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.3779694962	Mar 14 01:08:15 PM PDT 24	Mar 14 01:08:17 PM PDT 24	41224905 ps
T43	/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.138962892	Mar 14 01:06:53 PM PDT 24	Mar 14 01:06:55 PM PDT 24	45933480 ps
T116	/workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.1747137179	Mar 14 01:07:40 PM PDT 24	Mar 14 01:07:50 PM PDT 24	1205355017 ps
T117	/workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.3491893825	Mar 14 01:08:18 PM PDT 24	Mar 14 01:08:19 PM PDT 24	72999738 ps
T118	/workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.2911917386	Mar 14 01:07:59 PM PDT 24	Mar 14 01:08:01 PM PDT 24	50116416 ps
T119	/workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.825894291	Mar 14 01:07:39 PM PDT 24	Mar 14 01:07:41 PM PDT 24	1043788715 ps
T120	/workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.3719936843	Mar 14 01:07:58 PM PDT 24	Mar 14 01:08:00 PM PDT 24	76107478 ps
T121	/workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.2281086767	Mar 14 01:07:57 PM PDT 24	Mar 14 01:08:03 PM PDT 24	291212138 ps
T122	/workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.595836326	Mar 14 01:08:12 PM PDT 24	Mar 14 01:08:14 PM PDT 24	73511883 ps
T123	/workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.2297634343	Mar 14 01:07:59 PM PDT 24	Mar 14 01:08:03 PM PDT 24	122391875 ps
T75	/workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.2691841498	Mar 14 01:07:59 PM PDT 24	Mar 14 01:08:20 PM PDT 24	2429055921 ps
T45	/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.1022635192	Mar 14 01:07:07 PM PDT 24	Mar 14 01:07:09 PM PDT 24	120084987 ps
T124	/workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.1644017339	Mar 14 01:07:58 PM PDT 24	Mar 14 01:08:03 PM PDT 24	150677911 ps
T74	/workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.66279756	Mar 14 01:07:59 PM PDT 24	Mar 14 01:08:20 PM PDT 24	2539339314 ps
T125	/workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.3886726637	Mar 14 01:06:51 PM PDT 24	Mar 14 01:06:53 PM PDT 24	116855123 ps
T126	/workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.3317685774	Mar 14 01:07:58 PM PDT 24	Mar 14 01:08:02 PM PDT 24	157866517 ps
T127	/workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.722395170	Mar 14 01:06:52 PM PDT 24	Mar 14 01:07:10 PM PDT 24	1187347369 ps
T128	/workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.4076563462	Mar 14 01:07:58 PM PDT 24	Mar 14 01:08:03 PM PDT 24	432381418 ps
T61	/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.3538785286	Mar 14 01:07:21 PM PDT 24	Mar 14 01:07:26 PM PDT 24	475504044 ps
T44	/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.2931120257	Mar 14 01:06:51 PM PDT 24	Mar 14 01:06:58 PM PDT 24	190147413 ps
T129	/workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.1729251821	Mar 14 01:08:15 PM PDT 24	Mar 14 01:08:17 PM PDT 24	136890584 ps
T130	/workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.3609650317	Mar 14 01:08:02 PM PDT 24	Mar 14 01:08:03 PM PDT 24	41154414 ps
T131	/workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.2161617689	Mar 14 01:08:13 PM PDT 24	Mar 14 01:08:14 PM PDT 24	36227828 ps
T80	/workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.1082777520	Mar 14 01:07:09 PM PDT 24	Mar 14 01:07:32 PM PDT 24	5181901734 ps
T132	/workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.602687170	Mar 14 01:07:58 PM PDT 24	Mar 14 01:08:11 PM PDT 24	2465740067 ps
T133	/workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.2378852877	Mar 14 01:07:04 PM PDT 24	Mar 14 01:07:06 PM PDT 24	40649948 ps
T134	/workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.1646856752	Mar 14 01:08:16 PM PDT 24	Mar 14 01:08:18 PM PDT 24	40194839 ps
T64	/workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.2679700575	Mar 14 01:07:41 PM PDT 24	Mar 14 01:08:01 PM PDT 24	1419252953 ps
T135	/workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.3086042933	Mar 14 01:07:39 PM PDT 24	Mar 14 01:07:42 PM PDT 24	1009925696 ps
T136	/workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.4146295377	Mar 14 01:07:40 PM PDT 24	Mar 14 01:07:43 PM PDT 24	405832197 ps
T137	/workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.3963987192	Mar 14 01:07:40 PM PDT 24	Mar 14 01:07:43 PM PDT 24	996486595 ps
T76	/workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.235798838	Mar 14 01:07:59 PM PDT 24	Mar 14 01:08:21 PM PDT 24	1687996802 ps
T138	/workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.1490437702	Mar 14 01:07:57 PM PDT 24	Mar 14 01:08:00 PM PDT 24	119309971 ps
T139	/workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.1382409272	Mar 14 01:07:56 PM PDT 24	Mar 14 01:07:58 PM PDT 24	46134864 ps
T140	/workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.3048880085	Mar 14 01:07:20 PM PDT 24	Mar 14 01:07:22 PM PDT 24	129684040 ps
T82	/workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.343136742	Mar 14 01:07:56 PM PDT 24	Mar 14 01:08:07 PM PDT 24	1002093533 ps
T141	/workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.2693784023	Mar 14 01:07:41 PM PDT 24	Mar 14 01:07:43 PM PDT 24	144684537 ps
T142	/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.3950983431	Mar 14 01:07:10 PM PDT 24	Mar 14 01:07:12 PM PDT 24	239302645 ps
T143	/workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.990774599	Mar 14 01:07:39 PM PDT 24	Mar 14 01:07:41 PM PDT 24	41554007 ps
T144	/workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.2170530333	Mar 14 01:06:54 PM PDT 24	Mar 14 01:06:56 PM PDT 24	75170691 ps
T145	/workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.2343927738	Mar 14 01:07:39 PM PDT 24	Mar 14 01:07:50 PM PDT 24	657339419 ps
T146	/workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.2104970065	Mar 14 01:07:41 PM PDT 24	Mar 14 01:07:43 PM PDT 24	37155097 ps
T147	/workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.557539011	Mar 14 01:07:38 PM PDT 24	Mar 14 01:07:42 PM PDT 24	237291796 ps
T148	/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.305222194	Mar 14 01:07:08 PM PDT 24	Mar 14 01:07:13 PM PDT 24	154623714 ps
T149	/workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.2964097463	Mar 14 01:07:57 PM PDT 24	Mar 14 01:08:01 PM PDT 24	182903162 ps
T150	/workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.338331477	Mar 14 01:07:59 PM PDT 24	Mar 14 01:08:01 PM PDT 24	49432685 ps
T151	/workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.3486828652	Mar 14 01:06:53 PM PDT 24	Mar 14 01:06:55 PM PDT 24	556475458 ps
T152	/workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.279981635	Mar 14 01:07:38 PM PDT 24	Mar 14 01:07:40 PM PDT 24	140873009 ps
T153	/workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.436819891	Mar 14 01:07:56 PM PDT 24	Mar 14 01:07:58 PM PDT 24	118135684 ps
T154	/workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.869963595	Mar 14 01:06:52 PM PDT 24	Mar 14 01:06:54 PM PDT 24	47773521 ps
T155	/workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.1642764244	Mar 14 01:06:52 PM PDT 24	Mar 14 01:06:54 PM PDT 24	69354212 ps
T83	/workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.2745840186	Mar 14 01:07:57 PM PDT 24	Mar 14 01:08:22 PM PDT 24	19605201421 ps
T48	/workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.229493445	Mar 14 01:07:40 PM PDT 24	Mar 14 01:07:42 PM PDT 24	569535531 ps
T46	/workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.1384782450	Mar 14 01:07:59 PM PDT 24	Mar 14 01:08:01 PM PDT 24	47351340 ps
T156	/workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.2861260421	Mar 14 01:07:07 PM PDT 24	Mar 14 01:07:09 PM PDT 24	74862061 ps
T157	/workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.220136157	Mar 14 01:07:57 PM PDT 24	Mar 14 01:07:59 PM PDT 24	170439007 ps
T158	/workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.549831244	Mar 14 01:08:11 PM PDT 24	Mar 14 01:08:12 PM PDT 24	37375005 ps
T159	/workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.344909759	Mar 14 01:08:00 PM PDT 24	Mar 14 01:08:01 PM PDT 24	37529159 ps
T160	/workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.2829688573	Mar 14 01:07:38 PM PDT 24	Mar 14 01:07:41 PM PDT 24	700808449 ps
T161	/workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.3916558005	Mar 14 01:08:11 PM PDT 24	Mar 14 01:08:12 PM PDT 24	138285125 ps
T162	/workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.2783214753	Mar 14 01:07:41 PM PDT 24	Mar 14 01:07:46 PM PDT 24	73756763 ps
T47	/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.1643347812	Mar 14 01:06:54 PM PDT 24	Mar 14 01:06:57 PM PDT 24	97837660 ps
T163	/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.2006453177	Mar 14 01:07:19 PM PDT 24	Mar 14 01:07:25 PM PDT 24	242834747 ps
T164	/workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.869398259	Mar 14 01:08:12 PM PDT 24	Mar 14 01:08:14 PM PDT 24	510115990 ps
T165	/workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.532468194	Mar 14 01:07:39 PM PDT 24	Mar 14 01:07:41 PM PDT 24	655586616 ps
T166	/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.638977041	Mar 14 01:07:09 PM PDT 24	Mar 14 01:07:14 PM PDT 24	470328750 ps
T167	/workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.37936549	Mar 14 01:08:00 PM PDT 24	Mar 14 01:08:06 PM PDT 24	172557860 ps
T168	/workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.3821551137	Mar 14 01:07:39 PM PDT 24	Mar 14 01:08:01 PM PDT 24	4856490972 ps
T169	/workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.3010721240	Mar 14 01:07:39 PM PDT 24	Mar 14 01:07:43 PM PDT 24	191505219 ps
T170	/workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.1584664147	Mar 14 01:08:16 PM PDT 24	Mar 14 01:08:18 PM PDT 24	138344702 ps
T171	/workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.2210978896	Mar 14 01:07:57 PM PDT 24	Mar 14 01:08:01 PM PDT 24	406162606 ps
T172	/workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.3651415228	Mar 14 01:07:58 PM PDT 24	Mar 14 01:07:59 PM PDT 24	39141863 ps
T173	/workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.1851701202	Mar 14 01:08:00 PM PDT 24	Mar 14 01:08:11 PM PDT 24	647696266 ps
T174	/workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.1045038906	Mar 14 01:07:39 PM PDT 24	Mar 14 01:07:41 PM PDT 24	41388098 ps

Test location	/workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.1772968327
Short name	T6
Test name
Test status
Simulation time	10272413237 ps
CPU time	12.36 seconds
Started	Mar 14 01:07:57 PM PDT 24
Finished	Mar 14 01:08:10 PM PDT 24
Peak memory	243520 kb
Host	smart-73f34c35-97b6-41ed-a563-45bc22180afa
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772968327 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_i ntg_err.1772968327
Directory	/workspace/18.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.3652890042
Short name	T7
Test name
Test status
Simulation time	98625301 ps
CPU time	3.95 seconds
Started	Mar 14 01:07:39 PM PDT 24
Finished	Mar 14 01:07:43 PM PDT 24
Peak memory	245024 kb
Host	smart-ff277c2d-a4a8-48e3-b8b9-e1d8bf88384a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652890042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_errors.3652890042
Directory	/workspace/9.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.2633631010
Short name	T13
Test name
Test status
Simulation time	95448995 ps
CPU time	2.27 seconds
Started	Mar 14 01:07:05 PM PDT 24
Finished	Mar 14 01:07:08 PM PDT 24
Peak memory	240132 kb
Host	smart-af3d4e17-872e-4442-89a9-b8fabfa5ceac
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633631010 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_hw_r eset.2633631010
Directory	/workspace/2.otp_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.2887839337
Short name	T50
Test name
Test status
Simulation time	43344185 ps
CPU time	1.5 seconds
Started	Mar 14 01:08:17 PM PDT 24
Finished	Mar 14 01:08:19 PM PDT 24
Peak memory	229264 kb
Host	smart-606a4c97-39bb-43b4-b6fb-25bb5d19a330
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887839337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_intr_test.2887839337
Directory	/workspace/30.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.299927015
Short name	T18
Test name
Test status
Simulation time	128433778 ps
CPU time	3.44 seconds
Started	Mar 14 01:07:40 PM PDT 24
Finished	Mar 14 01:07:44 PM PDT 24
Peak memory	238368 kb
Host	smart-e623f751-abfe-4f65-9321-320c7374108f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299927015 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ct rl_same_csr_outstanding.299927015
Directory	/workspace/4.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.4143773533
Short name	T9
Test name
Test status
Simulation time	791109630 ps
CPU time	10.03 seconds
Started	Mar 14 01:06:54 PM PDT 24
Finished	Mar 14 01:07:05 PM PDT 24
Peak memory	238376 kb
Host	smart-11a3c88d-2314-4b8e-8944-9edf54d50f1e
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143773533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_bit_ bash.4143773533
Directory	/workspace/1.otp_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.867387087
Short name	T78
Test name
Test status
Simulation time	4566135568 ps
CPU time	21.66 seconds
Started	Mar 14 01:06:51 PM PDT 24
Finished	Mar 14 01:07:13 PM PDT 24
Peak memory	243936 kb
Host	smart-5f92d8d3-1280-427e-b160-f3970676c6cd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867387087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_int g_err.867387087
Directory	/workspace/2.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.3906826737
Short name	T25
Test name
Test status
Simulation time	1532869788 ps
CPU time	3.7 seconds
Started	Mar 14 01:07:08 PM PDT 24
Finished	Mar 14 01:07:12 PM PDT 24
Peak memory	245056 kb
Host	smart-0f6f4cf3-7b1a-4788-ae5a-17d22d90fce5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906826737 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_errors.3906826737
Directory	/workspace/3.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.1643347812
Short name	T47
Test name
Test status
Simulation time	97837660 ps
CPU time	2.4 seconds
Started	Mar 14 01:06:54 PM PDT 24
Finished	Mar 14 01:06:57 PM PDT 24
Peak memory	240424 kb
Host	smart-391f75d7-b22d-48b4-bf51-8e9ff13fa84d
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643347812 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_hw_r eset.1643347812
Directory	/workspace/0.otp_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.401747395
Short name	T11
Test name
Test status
Simulation time	68226628 ps
CPU time	1.44 seconds
Started	Mar 14 01:08:17 PM PDT 24
Finished	Mar 14 01:08:18 PM PDT 24
Peak memory	229684 kb
Host	smart-8d84d366-f2fd-43f7-a6e3-16d4fc022aa1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401747395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_intr_test.401747395
Directory	/workspace/41.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.2691841498
Short name	T75
Test name
Test status
Simulation time	2429055921 ps
CPU time	20.92 seconds
Started	Mar 14 01:07:59 PM PDT 24
Finished	Mar 14 01:08:20 PM PDT 24
Peak memory	238272 kb
Host	smart-32702cf6-47f2-4aea-83cc-6f01c2b24fd0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691841498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_i ntg_err.2691841498
Directory	/workspace/12.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.2809778169
Short name	T71
Test name
Test status
Simulation time	106268625 ps
CPU time	2.45 seconds
Started	Mar 14 01:07:22 PM PDT 24
Finished	Mar 14 01:07:24 PM PDT 24
Peak memory	238384 kb
Host	smart-28641d96-64d4-45a2-a1ec-dcbaf8f719e9
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809778169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_hw_r eset.2809778169
Directory	/workspace/4.otp_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.2288221746
Short name	T23
Test name
Test status
Simulation time	330294826 ps
CPU time	3.65 seconds
Started	Mar 14 01:08:00 PM PDT 24
Finished	Mar 14 01:08:03 PM PDT 24
Peak memory	238520 kb
Host	smart-336e9928-2014-4341-962a-67b74dc5451d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288221746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_errors.2288221746
Directory	/workspace/13.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.178145810
Short name	T35
Test name
Test status
Simulation time	98586398 ps
CPU time	2.11 seconds
Started	Mar 14 01:06:54 PM PDT 24
Finished	Mar 14 01:06:56 PM PDT 24
Peak memory	238348 kb
Host	smart-1b6989b7-5197-4356-a3e4-1dba20704d40
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178145810 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_hw_re set.178145810
Directory	/workspace/1.otp_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.1188255040
Short name	T21
Test name
Test status
Simulation time	449212182 ps
CPU time	6.46 seconds
Started	Mar 14 01:06:51 PM PDT 24
Finished	Mar 14 01:06:58 PM PDT 24
Peak memory	245232 kb
Host	smart-3ab959e7-44e4-46a6-a73f-f4c4c51ef5a0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188255040 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_errors.1188255040
Directory	/workspace/2.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.680453651
Short name	T42
Test name
Test status
Simulation time	193353967 ps
CPU time	2.56 seconds
Started	Mar 14 01:07:09 PM PDT 24
Finished	Mar 14 01:07:12 PM PDT 24
Peak memory	240496 kb
Host	smart-6ed6db5b-d7d4-49d6-b0fe-19cef0ba768c
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680453651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_hw_re set.680453651
Directory	/workspace/3.otp_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.343136742
Short name	T82
Test name
Test status
Simulation time	1002093533 ps
CPU time	10.68 seconds
Started	Mar 14 01:07:56 PM PDT 24
Finished	Mar 14 01:08:07 PM PDT 24
Peak memory	242896 kb
Host	smart-2b701c72-5097-428d-bc87-9d116dfc5521
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343136742 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_in tg_err.343136742
Directory	/workspace/17.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.1082777520
Short name	T80
Test name
Test status
Simulation time	5181901734 ps
CPU time	22.95 seconds
Started	Mar 14 01:07:09 PM PDT 24
Finished	Mar 14 01:07:32 PM PDT 24
Peak memory	243572 kb
Host	smart-dde45546-f3c3-44b8-8261-a36999d4221e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082777520 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_in tg_err.1082777520
Directory	/workspace/3.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.2679700575
Short name	T64
Test name
Test status
Simulation time	1419252953 ps
CPU time	19.77 seconds
Started	Mar 14 01:07:41 PM PDT 24
Finished	Mar 14 01:08:01 PM PDT 24
Peak memory	238372 kb
Host	smart-30614045-a0dd-44d8-a240-15040f2ae493
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679700575 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_in tg_err.2679700575
Directory	/workspace/8.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.66279756
Short name	T74
Test name
Test status
Simulation time	2539339314 ps
CPU time	20.52 seconds
Started	Mar 14 01:07:59 PM PDT 24
Finished	Mar 14 01:08:20 PM PDT 24
Peak memory	244604 kb
Host	smart-463f5c33-9c88-4216-bb0f-d5417a3a0e55
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66279756 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_int g_err.66279756
Directory	/workspace/16.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.235798838
Short name	T76
Test name
Test status
Simulation time	1687996802 ps
CPU time	21.16 seconds
Started	Mar 14 01:07:59 PM PDT 24
Finished	Mar 14 01:08:21 PM PDT 24
Peak memory	238368 kb
Host	smart-84209f2d-d4d2-4104-b876-5ead5036bc5b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235798838 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_in tg_err.235798838
Directory	/workspace/13.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.4248717374
Short name	T24
Test name
Test status
Simulation time	114092541 ps
CPU time	3.77 seconds
Started	Mar 14 01:06:53 PM PDT 24
Finished	Mar 14 01:06:57 PM PDT 24
Peak memory	245376 kb
Host	smart-369b59a7-1a49-4193-b92c-8a0d36892ff4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248717374 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_errors.4248717374
Directory	/workspace/1.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.2281086767
Short name	T121
Test name
Test status
Simulation time	291212138 ps
CPU time	6.42 seconds
Started	Mar 14 01:07:57 PM PDT 24
Finished	Mar 14 01:08:03 PM PDT 24
Peak memory	245396 kb
Host	smart-10115709-7856-485e-b8f2-a31f6bcd61a9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281086767 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_errors.2281086767
Directory	/workspace/12.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.2210978896
Short name	T171
Test name
Test status
Simulation time	406162606 ps
CPU time	3.43 seconds
Started	Mar 14 01:07:57 PM PDT 24
Finished	Mar 14 01:08:01 PM PDT 24
Peak memory	246468 kb
Host	smart-1a4340a3-14b7-4594-b768-7733d47bf578
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210978896 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_mem_rw_with_rand_reset.2210978896
Directory	/workspace/14.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.37936549
Short name	T167
Test name
Test status
Simulation time	172557860 ps
CPU time	6.29 seconds
Started	Mar 14 01:08:00 PM PDT 24
Finished	Mar 14 01:08:06 PM PDT 24
Peak memory	245864 kb
Host	smart-7cd70033-33fb-47a4-b421-196e6149ee1c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37936549 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_errors.37936549
Directory	/workspace/15.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.338554219
Short name	T113
Test name
Test status
Simulation time	64547650 ps
CPU time	3.4 seconds
Started	Mar 14 01:07:41 PM PDT 24
Finished	Mar 14 01:07:44 PM PDT 24
Peak memory	245128 kb
Host	smart-926ebbd3-2dff-456c-a495-d27b4717c6d0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338554219 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_errors.338554219
Directory	/workspace/8.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.2931120257
Short name	T44
Test name
Test status
Simulation time	190147413 ps
CPU time	6.05 seconds
Started	Mar 14 01:06:51 PM PDT 24
Finished	Mar 14 01:06:58 PM PDT 24
Peak memory	240924 kb
Host	smart-92dfb256-28b1-4dc6-a675-8703d122681e
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931120257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_alia sing.2931120257
Directory	/workspace/0.otp_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.2772939990
Short name	T27
Test name
Test status
Simulation time	861395939 ps
CPU time	9.28 seconds
Started	Mar 14 01:06:52 PM PDT 24
Finished	Mar 14 01:07:01 PM PDT 24
Peak memory	238348 kb
Host	smart-ac8555fd-4542-427a-a476-9342c3970dd9
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772939990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_bit_ bash.2772939990
Directory	/workspace/0.otp_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.1191337760
Short name	T92
Test name
Test status
Simulation time	1624638428 ps
CPU time	4.95 seconds
Started	Mar 14 01:06:53 PM PDT 24
Finished	Mar 14 01:06:58 PM PDT 24
Peak memory	246488 kb
Host	smart-3c0a4950-dfaf-4ec3-8f82-867e659d76ff
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191337760 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_mem_rw_with_rand_reset.1191337760
Directory	/workspace/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.138962892
Short name	T43
Test name
Test status
Simulation time	45933480 ps
CPU time	1.71 seconds
Started	Mar 14 01:06:53 PM PDT 24
Finished	Mar 14 01:06:55 PM PDT 24
Peak memory	240136 kb
Host	smart-7989456d-4c2e-49b4-ad2c-ca9da094a573
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138962892 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_rw.138962892
Directory	/workspace/0.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.3486828652
Short name	T151
Test name
Test status
Simulation time	556475458 ps
CPU time	1.51 seconds
Started	Mar 14 01:06:53 PM PDT 24
Finished	Mar 14 01:06:55 PM PDT 24
Peak memory	229256 kb
Host	smart-ba1a3424-de17-4d39-8a1a-27dba8242f58
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486828652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_intr_test.3486828652
Directory	/workspace/0.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.349904802
Short name	T8
Test name
Test status
Simulation time	127108711 ps
CPU time	1.37 seconds
Started	Mar 14 01:06:52 PM PDT 24
Finished	Mar 14 01:06:54 PM PDT 24
Peak memory	229280 kb
Host	smart-e28c5733-eaff-473c-a141-6c91841ee575
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349904802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl _mem_partial_access.349904802
Directory	/workspace/0.otp_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.3886726637
Short name	T125
Test name
Test status
Simulation time	116855123 ps
CPU time	1.38 seconds
Started	Mar 14 01:06:51 PM PDT 24
Finished	Mar 14 01:06:53 PM PDT 24
Peak memory	229964 kb
Host	smart-e849a70b-070f-4501-9ca9-76aef64935b3
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886726637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_walk .3886726637
Directory	/workspace/0.otp_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.869963595
Short name	T154
Test name
Test status
Simulation time	47773521 ps
CPU time	2.13 seconds
Started	Mar 14 01:06:52 PM PDT 24
Finished	Mar 14 01:06:54 PM PDT 24
Peak memory	238276 kb
Host	smart-1ec15b2e-82e0-4f2c-af2e-592f43b03029
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869963595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ct rl_same_csr_outstanding.869963595
Directory	/workspace/0.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.3408070269
Short name	T73
Test name
Test status
Simulation time	92837820 ps
CPU time	3.08 seconds
Started	Mar 14 01:06:51 PM PDT 24
Finished	Mar 14 01:06:55 PM PDT 24
Peak memory	245068 kb
Host	smart-49951481-9d68-418c-888d-cfc7472290c9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408070269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_errors.3408070269
Directory	/workspace/0.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.722395170
Short name	T127
Test name
Test status
Simulation time	1187347369 ps
CPU time	17.65 seconds
Started	Mar 14 01:06:52 PM PDT 24
Finished	Mar 14 01:07:10 PM PDT 24
Peak memory	243188 kb
Host	smart-e5a70900-c64e-4ac1-8b91-b86c4c25487b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722395170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_int g_err.722395170
Directory	/workspace/0.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.1457144974
Short name	T32
Test name
Test status
Simulation time	278571050 ps
CPU time	3.76 seconds
Started	Mar 14 01:06:51 PM PDT 24
Finished	Mar 14 01:06:55 PM PDT 24
Peak memory	240808 kb
Host	smart-1636d90d-e5b2-4fd7-8689-9479d30b3301
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457144974 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_alia sing.1457144974
Directory	/workspace/1.otp_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.1757591948
Short name	T57
Test name
Test status
Simulation time	168507267 ps
CPU time	2.72 seconds
Started	Mar 14 01:06:52 PM PDT 24
Finished	Mar 14 01:06:55 PM PDT 24
Peak memory	244476 kb
Host	smart-7b0552f8-d5f5-4e03-9413-fa42f5426380
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757591948 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_mem_rw_with_rand_reset.1757591948
Directory	/workspace/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.3921430042
Short name	T30
Test name
Test status
Simulation time	679888570 ps
CPU time	2.78 seconds
Started	Mar 14 01:06:54 PM PDT 24
Finished	Mar 14 01:06:57 PM PDT 24
Peak memory	240556 kb
Host	smart-e7641bab-3091-4781-b0ee-098ff1d2be7b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921430042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_rw.3921430042
Directory	/workspace/1.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.1445803957
Short name	T69
Test name
Test status
Simulation time	41587201 ps
CPU time	1.44 seconds
Started	Mar 14 01:06:54 PM PDT 24
Finished	Mar 14 01:06:56 PM PDT 24
Peak memory	229216 kb
Host	smart-0499c075-2509-4078-b3e1-80e9eb2790c7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445803957 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_intr_test.1445803957
Directory	/workspace/1.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.1642764244
Short name	T155
Test name
Test status
Simulation time	69354212 ps
CPU time	1.37 seconds
Started	Mar 14 01:06:52 PM PDT 24
Finished	Mar 14 01:06:54 PM PDT 24
Peak memory	228940 kb
Host	smart-ffce6ad0-9e15-4a29-ba1e-56d23fc1afd7
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642764244 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctr l_mem_partial_access.1642764244
Directory	/workspace/1.otp_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.4140341213
Short name	T15
Test name
Test status
Simulation time	142729469 ps
CPU time	1.36 seconds
Started	Mar 14 01:06:55 PM PDT 24
Finished	Mar 14 01:06:57 PM PDT 24
Peak memory	229172 kb
Host	smart-08c803ef-0750-41aa-8041-f0429ba7ee02
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140341213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_walk .4140341213
Directory	/workspace/1.otp_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.1564423428
Short name	T110
Test name
Test status
Simulation time	177256111 ps
CPU time	1.86 seconds
Started	Mar 14 01:06:52 PM PDT 24
Finished	Mar 14 01:06:55 PM PDT 24
Peak memory	238428 kb
Host	smart-0e3f37b1-06a4-487d-b66c-e1fe15f0a640
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564423428 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_c trl_same_csr_outstanding.1564423428
Directory	/workspace/1.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.1088826868
Short name	T79
Test name
Test status
Simulation time	1399919819 ps
CPU time	19.35 seconds
Started	Mar 14 01:06:54 PM PDT 24
Finished	Mar 14 01:07:14 PM PDT 24
Peak memory	238324 kb
Host	smart-7e3d6081-3a35-4bb4-8881-d367bcc7a443
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088826868 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_in tg_err.1088826868
Directory	/workspace/1.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.602852674
Short name	T106
Test name
Test status
Simulation time	1640761375 ps
CPU time	4.59 seconds
Started	Mar 14 01:07:40 PM PDT 24
Finished	Mar 14 01:07:45 PM PDT 24
Peak memory	246408 kb
Host	smart-4428c250-f408-4a81-9e37-921de544ab60
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602852674 -assert nopostproc +UVM_TESTNAME= otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_mem_rw_with_rand_reset.602852674
Directory	/workspace/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.3847295524
Short name	T34
Test name
Test status
Simulation time	80248842 ps
CPU time	1.51 seconds
Started	Mar 14 01:07:39 PM PDT 24
Finished	Mar 14 01:07:41 PM PDT 24
Peak memory	240148 kb
Host	smart-e5c45958-4561-476f-8db0-88c67f8f1287
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847295524 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_rw.3847295524
Directory	/workspace/10.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.990774599
Short name	T143
Test name
Test status
Simulation time	41554007 ps
CPU time	1.42 seconds
Started	Mar 14 01:07:39 PM PDT 24
Finished	Mar 14 01:07:41 PM PDT 24
Peak memory	229116 kb
Host	smart-a1cfa604-58f7-442f-b2e8-a5949f05ab2a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990774599 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_intr_test.990774599
Directory	/workspace/10.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.2829688573
Short name	T160
Test name
Test status
Simulation time	700808449 ps
CPU time	2.31 seconds
Started	Mar 14 01:07:38 PM PDT 24
Finished	Mar 14 01:07:41 PM PDT 24
Peak memory	238388 kb
Host	smart-77bcd114-81e3-470a-b3a5-201acebb324d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829688573 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ ctrl_same_csr_outstanding.2829688573
Directory	/workspace/10.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.3010721240
Short name	T169
Test name
Test status
Simulation time	191505219 ps
CPU time	3.42 seconds
Started	Mar 14 01:07:39 PM PDT 24
Finished	Mar 14 01:07:43 PM PDT 24
Peak memory	245316 kb
Host	smart-2af77400-6673-4e4e-837f-dd55b37c9104
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010721240 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_errors.3010721240
Directory	/workspace/10.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.2343927738
Short name	T145
Test name
Test status
Simulation time	657339419 ps
CPU time	10.9 seconds
Started	Mar 14 01:07:39 PM PDT 24
Finished	Mar 14 01:07:50 PM PDT 24
Peak memory	242848 kb
Host	smart-3d27b760-485e-4a88-84d1-842c86fe26e0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343927738 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_i ntg_err.2343927738
Directory	/workspace/10.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.3086042933
Short name	T135
Test name
Test status
Simulation time	1009925696 ps
CPU time	2.87 seconds
Started	Mar 14 01:07:39 PM PDT 24
Finished	Mar 14 01:07:42 PM PDT 24
Peak memory	243572 kb
Host	smart-3ca68e3b-925c-42fb-aa72-3fb6b23281dd
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086042933 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_mem_rw_with_rand_reset.3086042933
Directory	/workspace/11.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.1823031452
Short name	T31
Test name
Test status
Simulation time	538579376 ps
CPU time	1.88 seconds
Started	Mar 14 01:07:42 PM PDT 24
Finished	Mar 14 01:07:44 PM PDT 24
Peak memory	238372 kb
Host	smart-d3a05bb2-0542-4b8f-aedc-250d6e0ecd2c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823031452 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_rw.1823031452
Directory	/workspace/11.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.1104675590
Short name	T84
Test name
Test status
Simulation time	39545437 ps
CPU time	1.46 seconds
Started	Mar 14 01:07:40 PM PDT 24
Finished	Mar 14 01:07:42 PM PDT 24
Peak memory	230080 kb
Host	smart-014ae3db-7c0c-48c5-887f-414b5964a108
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104675590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_intr_test.1104675590
Directory	/workspace/11.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.1085567
Short name	T54
Test name
Test status
Simulation time	105795822 ps
CPU time	3.1 seconds
Started	Mar 14 01:07:39 PM PDT 24
Finished	Mar 14 01:07:42 PM PDT 24
Peak memory	238360 kb
Host	smart-74fa56c6-9494-4925-acfe-361c8aa7a232
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085567 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctr l_same_csr_outstanding.1085567
Directory	/workspace/11.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.2783214753
Short name	T162
Test name
Test status
Simulation time	73756763 ps
CPU time	4.96 seconds
Started	Mar 14 01:07:41 PM PDT 24
Finished	Mar 14 01:07:46 PM PDT 24
Peak memory	238496 kb
Host	smart-6fd4fd9b-7739-4a92-a927-80ca10a8d88d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783214753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_errors.2783214753
Directory	/workspace/11.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.248837580
Short name	T81
Test name
Test status
Simulation time	1083602075 ps
CPU time	10.9 seconds
Started	Mar 14 01:07:40 PM PDT 24
Finished	Mar 14 01:07:51 PM PDT 24
Peak memory	242952 kb
Host	smart-304ba30c-b972-441e-a9f5-c8eeb32a0b5d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248837580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_in tg_err.248837580
Directory	/workspace/11.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.2297634343
Short name	T123
Test name
Test status
Simulation time	122391875 ps
CPU time	3.39 seconds
Started	Mar 14 01:07:59 PM PDT 24
Finished	Mar 14 01:08:03 PM PDT 24
Peak memory	246588 kb
Host	smart-78f4947f-fda2-4582-893c-2dc5f8b8197f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297634343 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_mem_rw_with_rand_reset.2297634343
Directory	/workspace/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.1185367815
Short name	T2
Test name
Test status
Simulation time	78883364 ps
CPU time	1.56 seconds
Started	Mar 14 01:08:00 PM PDT 24
Finished	Mar 14 01:08:02 PM PDT 24
Peak memory	239992 kb
Host	smart-f611d2d3-9cc9-4084-86b5-97f4df7b9d4f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185367815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_rw.1185367815
Directory	/workspace/12.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.2409872757
Short name	T114
Test name
Test status
Simulation time	38782907 ps
CPU time	1.41 seconds
Started	Mar 14 01:08:00 PM PDT 24
Finished	Mar 14 01:08:02 PM PDT 24
Peak memory	230068 kb
Host	smart-d202953a-0200-462f-b761-5d18cf079ae9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409872757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_intr_test.2409872757
Directory	/workspace/12.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.1730624983
Short name	T52
Test name
Test status
Simulation time	75525873 ps
CPU time	2.46 seconds
Started	Mar 14 01:07:57 PM PDT 24
Finished	Mar 14 01:07:59 PM PDT 24
Peak memory	241028 kb
Host	smart-43b04a05-7c99-440a-b1df-c813a8159a6b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730624983 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ ctrl_same_csr_outstanding.1730624983
Directory	/workspace/12.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.208719707
Short name	T102
Test name
Test status
Simulation time	139164483 ps
CPU time	2.4 seconds
Started	Mar 14 01:07:59 PM PDT 24
Finished	Mar 14 01:08:02 PM PDT 24
Peak memory	244172 kb
Host	smart-38b6eb01-3bfd-462c-89ea-0df16812f52c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208719707 -assert nopostproc +UVM_TESTNAME= otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_mem_rw_with_rand_reset.208719707
Directory	/workspace/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.1384782450
Short name	T46
Test name
Test status
Simulation time	47351340 ps
CPU time	1.84 seconds
Started	Mar 14 01:07:59 PM PDT 24
Finished	Mar 14 01:08:01 PM PDT 24
Peak memory	240528 kb
Host	smart-ee35fca2-13b3-4e01-bb86-0afbda205dad
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384782450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_rw.1384782450
Directory	/workspace/13.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.1382409272
Short name	T139
Test name
Test status
Simulation time	46134864 ps
CPU time	1.56 seconds
Started	Mar 14 01:07:56 PM PDT 24
Finished	Mar 14 01:07:58 PM PDT 24
Peak memory	229148 kb
Host	smart-f5a04598-cd2e-44cc-8fbc-3a49e8420401
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382409272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_intr_test.1382409272
Directory	/workspace/13.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.220136157
Short name	T157
Test name
Test status
Simulation time	170439007 ps
CPU time	1.91 seconds
Started	Mar 14 01:07:57 PM PDT 24
Finished	Mar 14 01:07:59 PM PDT 24
Peak memory	241144 kb
Host	smart-a9207527-4d19-45ff-83a3-252eb8990e1b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220136157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_c trl_same_csr_outstanding.220136157
Directory	/workspace/13.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.1585309131
Short name	T36
Test name
Test status
Simulation time	131322446 ps
CPU time	1.87 seconds
Started	Mar 14 01:08:00 PM PDT 24
Finished	Mar 14 01:08:02 PM PDT 24
Peak memory	240288 kb
Host	smart-eccee8c3-8cc8-4bee-84eb-5f9b11565543
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585309131 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_rw.1585309131
Directory	/workspace/14.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.3651415228
Short name	T172
Test name
Test status
Simulation time	39141863 ps
CPU time	1.42 seconds
Started	Mar 14 01:07:58 PM PDT 24
Finished	Mar 14 01:07:59 PM PDT 24
Peak memory	230184 kb
Host	smart-e7b1046e-8442-4429-b49e-280c33d6780b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651415228 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_intr_test.3651415228
Directory	/workspace/14.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.1490437702
Short name	T138
Test name
Test status
Simulation time	119309971 ps
CPU time	2.68 seconds
Started	Mar 14 01:07:57 PM PDT 24
Finished	Mar 14 01:08:00 PM PDT 24
Peak memory	238368 kb
Host	smart-d3a6b889-5805-4dae-b856-45ed2c9c9d1e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490437702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ ctrl_same_csr_outstanding.1490437702
Directory	/workspace/14.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.2964097463
Short name	T149
Test name
Test status
Simulation time	182903162 ps
CPU time	3.82 seconds
Started	Mar 14 01:07:57 PM PDT 24
Finished	Mar 14 01:08:01 PM PDT 24
Peak memory	245476 kb
Host	smart-631b4e64-1b42-483a-b143-d2b1c983451b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964097463 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_errors.2964097463
Directory	/workspace/14.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.2745840186
Short name	T83
Test name
Test status
Simulation time	19605201421 ps
CPU time	24.31 seconds
Started	Mar 14 01:07:57 PM PDT 24
Finished	Mar 14 01:08:22 PM PDT 24
Peak memory	244984 kb
Host	smart-56418aec-8f59-4bdb-99f0-fc7ac84b9e9a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745840186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_i ntg_err.2745840186
Directory	/workspace/14.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.3841819827
Short name	T59
Test name
Test status
Simulation time	154434197 ps
CPU time	2.12 seconds
Started	Mar 14 01:07:58 PM PDT 24
Finished	Mar 14 01:08:01 PM PDT 24
Peak memory	243880 kb
Host	smart-2974f392-972d-41ed-8770-ad69e2f67159
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841819827 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_mem_rw_with_rand_reset.3841819827
Directory	/workspace/15.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.436819891
Short name	T153
Test name
Test status
Simulation time	118135684 ps
CPU time	1.73 seconds
Started	Mar 14 01:07:56 PM PDT 24
Finished	Mar 14 01:07:58 PM PDT 24
Peak memory	240352 kb
Host	smart-c3c2a5d5-c89a-46a2-987e-c22f387e54b0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436819891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_rw.436819891
Directory	/workspace/15.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.3609650317
Short name	T130
Test name
Test status
Simulation time	41154414 ps
CPU time	1.55 seconds
Started	Mar 14 01:08:02 PM PDT 24
Finished	Mar 14 01:08:03 PM PDT 24
Peak memory	229236 kb
Host	smart-461bcb1a-007b-4859-8f65-52b9d25a70a6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609650317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_intr_test.3609650317
Directory	/workspace/15.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.842525493
Short name	T98
Test name
Test status
Simulation time	460925188 ps
CPU time	3.69 seconds
Started	Mar 14 01:07:57 PM PDT 24
Finished	Mar 14 01:08:01 PM PDT 24
Peak memory	238320 kb
Host	smart-518f2350-6349-46d5-8c23-db1c1beeb13f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842525493 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_c trl_same_csr_outstanding.842525493
Directory	/workspace/15.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.602687170
Short name	T132
Test name
Test status
Simulation time	2465740067 ps
CPU time	12.41 seconds
Started	Mar 14 01:07:58 PM PDT 24
Finished	Mar 14 01:08:11 PM PDT 24
Peak memory	243352 kb
Host	smart-4a49d542-2231-4918-aca2-6dc6888e5868
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602687170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_in tg_err.602687170
Directory	/workspace/15.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.1566364967
Short name	T14
Test name
Test status
Simulation time	106679620 ps
CPU time	3.03 seconds
Started	Mar 14 01:07:59 PM PDT 24
Finished	Mar 14 01:08:03 PM PDT 24
Peak memory	246632 kb
Host	smart-24d5ff51-96ff-4991-96a4-62859707b615
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566364967 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_mem_rw_with_rand_reset.1566364967
Directory	/workspace/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.1570986883
Short name	T12
Test name
Test status
Simulation time	574295695 ps
CPU time	2 seconds
Started	Mar 14 01:08:01 PM PDT 24
Finished	Mar 14 01:08:04 PM PDT 24
Peak memory	240260 kb
Host	smart-7f2e609a-17ee-419c-b224-ad995e03c26e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570986883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_rw.1570986883
Directory	/workspace/16.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.3655015845
Short name	T10
Test name
Test status
Simulation time	41713315 ps
CPU time	1.48 seconds
Started	Mar 14 01:08:00 PM PDT 24
Finished	Mar 14 01:08:02 PM PDT 24
Peak memory	229296 kb
Host	smart-cec5d09d-9eaa-4905-a946-0eaacd6ecb59
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655015845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_intr_test.3655015845
Directory	/workspace/16.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.3385786893
Short name	T16
Test name
Test status
Simulation time	97729928 ps
CPU time	2.82 seconds
Started	Mar 14 01:07:59 PM PDT 24
Finished	Mar 14 01:08:02 PM PDT 24
Peak memory	238360 kb
Host	smart-57db2f97-8cb8-441f-95f7-5d8597819112
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385786893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ ctrl_same_csr_outstanding.3385786893
Directory	/workspace/16.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.888176945
Short name	T72
Test name
Test status
Simulation time	593133374 ps
CPU time	6.17 seconds
Started	Mar 14 01:07:59 PM PDT 24
Finished	Mar 14 01:08:06 PM PDT 24
Peak memory	245416 kb
Host	smart-4acaf9c9-bc0e-485c-9a6f-47e0560fea68
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888176945 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_errors.888176945
Directory	/workspace/16.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.875397848
Short name	T111
Test name
Test status
Simulation time	105002125 ps
CPU time	3.06 seconds
Started	Mar 14 01:07:59 PM PDT 24
Finished	Mar 14 01:08:03 PM PDT 24
Peak memory	246504 kb
Host	smart-08c771fe-32f2-40df-8a10-999c7ccceb9d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875397848 -assert nopostproc +UVM_TESTNAME= otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_mem_rw_with_rand_reset.875397848
Directory	/workspace/17.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.3558237887
Short name	T38
Test name
Test status
Simulation time	63853781 ps
CPU time	1.65 seconds
Started	Mar 14 01:07:58 PM PDT 24
Finished	Mar 14 01:08:00 PM PDT 24
Peak memory	238428 kb
Host	smart-1da870d0-7344-4cea-8484-2e4c6f116e64
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558237887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_rw.3558237887
Directory	/workspace/17.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.411375971
Short name	T94
Test name
Test status
Simulation time	36609090 ps
CPU time	1.41 seconds
Started	Mar 14 01:07:59 PM PDT 24
Finished	Mar 14 01:08:00 PM PDT 24
Peak memory	230176 kb
Host	smart-24662906-6dc8-496b-85aa-29f3040f6fad
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411375971 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_intr_test.411375971
Directory	/workspace/17.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.1626910983
Short name	T53
Test name
Test status
Simulation time	138442461 ps
CPU time	2.22 seconds
Started	Mar 14 01:07:59 PM PDT 24
Finished	Mar 14 01:08:02 PM PDT 24
Peak memory	238448 kb
Host	smart-b15d5125-a849-4327-9334-b0764cff7c4f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626910983 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ ctrl_same_csr_outstanding.1626910983
Directory	/workspace/17.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.1644017339
Short name	T124
Test name
Test status
Simulation time	150677911 ps
CPU time	4.18 seconds
Started	Mar 14 01:07:58 PM PDT 24
Finished	Mar 14 01:08:03 PM PDT 24
Peak memory	246088 kb
Host	smart-560e3554-1f4c-41df-b999-fb48db377391
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644017339 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_errors.1644017339
Directory	/workspace/17.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.1490333984
Short name	T5
Test name
Test status
Simulation time	265896910 ps
CPU time	2.42 seconds
Started	Mar 14 01:07:56 PM PDT 24
Finished	Mar 14 01:07:59 PM PDT 24
Peak memory	245636 kb
Host	smart-0a6da7f9-25a0-4a8f-ae64-0b441160ffaf
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490333984 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_mem_rw_with_rand_reset.1490333984
Directory	/workspace/18.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.3719936843
Short name	T120
Test name
Test status
Simulation time	76107478 ps
CPU time	1.55 seconds
Started	Mar 14 01:07:58 PM PDT 24
Finished	Mar 14 01:08:00 PM PDT 24
Peak memory	238432 kb
Host	smart-36c25c79-ca9f-4197-ac47-37ab6f3a32a0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719936843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_rw.3719936843
Directory	/workspace/18.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.2911917386
Short name	T118
Test name
Test status
Simulation time	50116416 ps
CPU time	1.55 seconds
Started	Mar 14 01:07:59 PM PDT 24
Finished	Mar 14 01:08:01 PM PDT 24
Peak memory	229608 kb
Host	smart-546d07d9-fd25-4228-9ce0-932e84f4ca6f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911917386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_intr_test.2911917386
Directory	/workspace/18.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.1184459582
Short name	T96
Test name
Test status
Simulation time	1026662178 ps
CPU time	2.94 seconds
Started	Mar 14 01:08:01 PM PDT 24
Finished	Mar 14 01:08:04 PM PDT 24
Peak memory	238364 kb
Host	smart-aacf516f-f02c-401a-b7d4-5c0580eb1487
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184459582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ ctrl_same_csr_outstanding.1184459582
Directory	/workspace/18.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.4076563462
Short name	T128
Test name
Test status
Simulation time	432381418 ps
CPU time	4.48 seconds
Started	Mar 14 01:07:58 PM PDT 24
Finished	Mar 14 01:08:03 PM PDT 24
Peak memory	245484 kb
Host	smart-07b8edae-5a03-4b9e-b5e9-b54e7ec60267
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076563462 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_errors.4076563462
Directory	/workspace/18.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.3673856464
Short name	T58
Test name
Test status
Simulation time	1723170835 ps
CPU time	5.72 seconds
Started	Mar 14 01:08:02 PM PDT 24
Finished	Mar 14 01:08:07 PM PDT 24
Peak memory	246688 kb
Host	smart-47d8e5ba-b2ea-4c52-919a-987bc366b230
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673856464 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_mem_rw_with_rand_reset.3673856464
Directory	/workspace/19.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.1921982999
Short name	T39
Test name
Test status
Simulation time	39413077 ps
CPU time	1.53 seconds
Started	Mar 14 01:07:59 PM PDT 24
Finished	Mar 14 01:08:00 PM PDT 24
Peak memory	240384 kb
Host	smart-01a9d10e-ef70-48fb-9862-f6e61aae7449
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921982999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_rw.1921982999
Directory	/workspace/19.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.1638293805
Short name	T93
Test name
Test status
Simulation time	152715773 ps
CPU time	1.63 seconds
Started	Mar 14 01:08:01 PM PDT 24
Finished	Mar 14 01:08:02 PM PDT 24
Peak memory	229208 kb
Host	smart-974fba30-211f-4a22-bb0c-88423d503a9d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638293805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_intr_test.1638293805
Directory	/workspace/19.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.3317685774
Short name	T126
Test name
Test status
Simulation time	157866517 ps
CPU time	3.28 seconds
Started	Mar 14 01:07:58 PM PDT 24
Finished	Mar 14 01:08:02 PM PDT 24
Peak memory	238328 kb
Host	smart-364d01ba-4f57-4c81-b97e-8b72594c0570
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317685774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ ctrl_same_csr_outstanding.3317685774
Directory	/workspace/19.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.3380045000
Short name	T100
Test name
Test status
Simulation time	103703093 ps
CPU time	5.27 seconds
Started	Mar 14 01:07:59 PM PDT 24
Finished	Mar 14 01:08:05 PM PDT 24
Peak memory	245480 kb
Host	smart-d6494bf9-2a7f-4bbd-b2c1-9c8df8ac9dd7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380045000 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_errors.3380045000
Directory	/workspace/19.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.1851701202
Short name	T173
Test name
Test status
Simulation time	647696266 ps
CPU time	10.64 seconds
Started	Mar 14 01:08:00 PM PDT 24
Finished	Mar 14 01:08:11 PM PDT 24
Peak memory	242952 kb
Host	smart-ff1e7c59-4938-4d8d-8ecf-b26c810129e4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851701202 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_i ntg_err.1851701202
Directory	/workspace/19.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.305222194
Short name	T148
Test name
Test status
Simulation time	154623714 ps
CPU time	5.05 seconds
Started	Mar 14 01:07:08 PM PDT 24
Finished	Mar 14 01:07:13 PM PDT 24
Peak memory	238264 kb
Host	smart-20358f8b-8e72-4fc8-b882-819f4d4b70b7
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305222194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_alias ing.305222194
Directory	/workspace/2.otp_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.638977041
Short name	T166
Test name
Test status
Simulation time	470328750 ps
CPU time	5.47 seconds
Started	Mar 14 01:07:09 PM PDT 24
Finished	Mar 14 01:07:14 PM PDT 24
Peak memory	238376 kb
Host	smart-c3e71344-bbaa-4e92-a396-5d285a88a93f
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638977041 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_bit_b ash.638977041
Directory	/workspace/2.otp_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.3950983431
Short name	T142
Test name
Test status
Simulation time	239302645 ps
CPU time	2.32 seconds
Started	Mar 14 01:07:10 PM PDT 24
Finished	Mar 14 01:07:12 PM PDT 24
Peak memory	238520 kb
Host	smart-54e1d8e7-9501-4cc4-b168-d432d9ca8487
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950983431 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_mem_rw_with_rand_reset.3950983431
Directory	/workspace/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.1022635192
Short name	T45
Test name
Test status
Simulation time	120084987 ps
CPU time	1.78 seconds
Started	Mar 14 01:07:07 PM PDT 24
Finished	Mar 14 01:07:09 PM PDT 24
Peak memory	238360 kb
Host	smart-6f469ab6-2643-4fae-854f-73921fe8fc5d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022635192 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_rw.1022635192
Directory	/workspace/2.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.2170530333
Short name	T144
Test name
Test status
Simulation time	75170691 ps
CPU time	1.4 seconds
Started	Mar 14 01:06:54 PM PDT 24
Finished	Mar 14 01:06:56 PM PDT 24
Peak memory	229476 kb
Host	smart-6edd7aa9-d0ba-44c1-8dd6-089a53a4002e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170530333 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_intr_test.2170530333
Directory	/workspace/2.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.2505447124
Short name	T66
Test name
Test status
Simulation time	67299958 ps
CPU time	1.37 seconds
Started	Mar 14 01:07:05 PM PDT 24
Finished	Mar 14 01:07:06 PM PDT 24
Peak memory	229972 kb
Host	smart-25a3df76-599f-46a9-ac5d-77d1e23c7496
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505447124 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctr l_mem_partial_access.2505447124
Directory	/workspace/2.otp_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.2861260421
Short name	T156
Test name
Test status
Simulation time	74862061 ps
CPU time	1.47 seconds
Started	Mar 14 01:07:07 PM PDT 24
Finished	Mar 14 01:07:09 PM PDT 24
Peak memory	229100 kb
Host	smart-23d80bb7-6d41-4451-87ff-f6ffcedfbaca
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861260421 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_walk .2861260421
Directory	/workspace/2.otp_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.1562924056
Short name	T56
Test name
Test status
Simulation time	1461443293 ps
CPU time	3.51 seconds
Started	Mar 14 01:07:10 PM PDT 24
Finished	Mar 14 01:07:13 PM PDT 24
Peak memory	238408 kb
Host	smart-4e51db5b-e9d7-41b2-b99c-a8928c41bdcf
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562924056 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_c trl_same_csr_outstanding.1562924056
Directory	/workspace/2.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.538585342
Short name	T63
Test name
Test status
Simulation time	37146867 ps
CPU time	1.42 seconds
Started	Mar 14 01:08:00 PM PDT 24
Finished	Mar 14 01:08:02 PM PDT 24
Peak memory	229644 kb
Host	smart-3f7c724d-89ee-445f-9f45-0581914b3307
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538585342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_intr_test.538585342
Directory	/workspace/20.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.3486967915
Short name	T70
Test name
Test status
Simulation time	578550070 ps
CPU time	1.48 seconds
Started	Mar 14 01:07:59 PM PDT 24
Finished	Mar 14 01:08:01 PM PDT 24
Peak memory	229296 kb
Host	smart-1a3483f0-6c9c-445b-9c44-00aaf1642098
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486967915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_intr_test.3486967915
Directory	/workspace/21.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.338331477
Short name	T150
Test name
Test status
Simulation time	49432685 ps
CPU time	1.58 seconds
Started	Mar 14 01:07:59 PM PDT 24
Finished	Mar 14 01:08:01 PM PDT 24
Peak memory	229252 kb
Host	smart-00bee64e-aad7-4a62-8f00-1b2c61a8a95a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338331477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_intr_test.338331477
Directory	/workspace/22.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.1656297004
Short name	T51
Test name
Test status
Simulation time	584189849 ps
CPU time	1.53 seconds
Started	Mar 14 01:08:00 PM PDT 24
Finished	Mar 14 01:08:02 PM PDT 24
Peak memory	229548 kb
Host	smart-c8ddec95-003d-4599-a07c-332bfa1b9907
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656297004 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_intr_test.1656297004
Directory	/workspace/23.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.2497982745
Short name	T68
Test name
Test status
Simulation time	68236735 ps
CPU time	1.48 seconds
Started	Mar 14 01:08:00 PM PDT 24
Finished	Mar 14 01:08:02 PM PDT 24
Peak memory	229548 kb
Host	smart-c849f8eb-7ade-4e11-8b85-e120040a1aae
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497982745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_intr_test.2497982745
Directory	/workspace/24.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.344909759
Short name	T159
Test name
Test status
Simulation time	37529159 ps
CPU time	1.35 seconds
Started	Mar 14 01:08:00 PM PDT 24
Finished	Mar 14 01:08:01 PM PDT 24
Peak memory	229492 kb
Host	smart-24466a31-004a-4fd7-a024-4da8662e546c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344909759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_intr_test.344909759
Directory	/workspace/25.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.549831244
Short name	T158
Test name
Test status
Simulation time	37375005 ps
CPU time	1.39 seconds
Started	Mar 14 01:08:11 PM PDT 24
Finished	Mar 14 01:08:12 PM PDT 24
Peak memory	229496 kb
Host	smart-4739e4b8-8fed-4d73-ad18-a4e082b64d18
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549831244 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_intr_test.549831244
Directory	/workspace/26.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.2577088327
Short name	T3
Test name
Test status
Simulation time	57416570 ps
CPU time	1.39 seconds
Started	Mar 14 01:08:11 PM PDT 24
Finished	Mar 14 01:08:12 PM PDT 24
Peak memory	229536 kb
Host	smart-f654afd1-15f1-4366-a42b-4be228a478c6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577088327 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_intr_test.2577088327
Directory	/workspace/27.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.3522625622
Short name	T62
Test name
Test status
Simulation time	56885140 ps
CPU time	1.39 seconds
Started	Mar 14 01:08:11 PM PDT 24
Finished	Mar 14 01:08:13 PM PDT 24
Peak memory	229424 kb
Host	smart-bf88e530-0539-45e9-9852-3b0d48949d72
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522625622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_intr_test.3522625622
Directory	/workspace/28.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.1646856752
Short name	T134
Test name
Test status
Simulation time	40194839 ps
CPU time	1.47 seconds
Started	Mar 14 01:08:16 PM PDT 24
Finished	Mar 14 01:08:18 PM PDT 24
Peak memory	230044 kb
Host	smart-62da4514-b056-411e-9d7c-12106a018a9a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646856752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_intr_test.1646856752
Directory	/workspace/29.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.2769786310
Short name	T33
Test name
Test status
Simulation time	273931928 ps
CPU time	6.4 seconds
Started	Mar 14 01:07:20 PM PDT 24
Finished	Mar 14 01:07:26 PM PDT 24
Peak memory	238268 kb
Host	smart-701ef433-cbac-4cb7-85d2-cde988a9d625
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769786310 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_alia sing.2769786310
Directory	/workspace/3.otp_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.2006453177
Short name	T163
Test name
Test status
Simulation time	242834747 ps
CPU time	6.3 seconds
Started	Mar 14 01:07:19 PM PDT 24
Finished	Mar 14 01:07:25 PM PDT 24
Peak memory	238348 kb
Host	smart-94be7057-ebaf-4b94-882a-d596e4cda5e2
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006453177 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_bit_ bash.2006453177
Directory	/workspace/3.otp_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.756319379
Short name	T37
Test name
Test status
Simulation time	73169292 ps
CPU time	1.5 seconds
Started	Mar 14 01:07:09 PM PDT 24
Finished	Mar 14 01:07:10 PM PDT 24
Peak memory	239700 kb
Host	smart-cc585786-6dcb-4081-87b9-b34c99f41634
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756319379 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_rw.756319379
Directory	/workspace/3.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.2378852877
Short name	T133
Test name
Test status
Simulation time	40649948 ps
CPU time	1.44 seconds
Started	Mar 14 01:07:04 PM PDT 24
Finished	Mar 14 01:07:06 PM PDT 24
Peak memory	230128 kb
Host	smart-3cdddcf4-2799-4433-8ac5-b78c8f2966dd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378852877 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_intr_test.2378852877
Directory	/workspace/3.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.2295265384
Short name	T26
Test name
Test status
Simulation time	70431481 ps
CPU time	1.45 seconds
Started	Mar 14 01:07:10 PM PDT 24
Finished	Mar 14 01:07:12 PM PDT 24
Peak memory	228992 kb
Host	smart-751cadb3-2a52-48b1-85ff-0e467d59bf2c
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295265384 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctr l_mem_partial_access.2295265384
Directory	/workspace/3.otp_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.2814371925
Short name	T65
Test name
Test status
Simulation time	63198491 ps
CPU time	1.43 seconds
Started	Mar 14 01:07:05 PM PDT 24
Finished	Mar 14 01:07:07 PM PDT 24
Peak memory	229144 kb
Host	smart-1fc244b0-5271-4c87-ab26-6b1c2688923d
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814371925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_walk .2814371925
Directory	/workspace/3.otp_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.4163120469
Short name	T107
Test name
Test status
Simulation time	92428095 ps
CPU time	1.96 seconds
Started	Mar 14 01:07:20 PM PDT 24
Finished	Mar 14 01:07:23 PM PDT 24
Peak memory	238320 kb
Host	smart-d64b9936-54f2-422a-ae28-ce52bb79b88c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163120469 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_c trl_same_csr_outstanding.4163120469
Directory	/workspace/3.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.595836326
Short name	T122
Test name
Test status
Simulation time	73511883 ps
CPU time	1.55 seconds
Started	Mar 14 01:08:12 PM PDT 24
Finished	Mar 14 01:08:14 PM PDT 24
Peak memory	229260 kb
Host	smart-ea47df5f-321f-4891-854c-f57aae12d78c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595836326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_intr_test.595836326
Directory	/workspace/31.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.322063675
Short name	T97
Test name
Test status
Simulation time	584273897 ps
CPU time	1.57 seconds
Started	Mar 14 01:08:17 PM PDT 24
Finished	Mar 14 01:08:18 PM PDT 24
Peak memory	230112 kb
Host	smart-7b271067-73e0-4010-bd7f-77d9e5f86ff1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322063675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_intr_test.322063675
Directory	/workspace/32.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.3779694962
Short name	T115
Test name
Test status
Simulation time	41224905 ps
CPU time	1.47 seconds
Started	Mar 14 01:08:15 PM PDT 24
Finished	Mar 14 01:08:17 PM PDT 24
Peak memory	230096 kb
Host	smart-9efb4be5-c994-411a-a84f-f89e930a2b8b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779694962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_intr_test.3779694962
Directory	/workspace/33.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.1584664147
Short name	T170
Test name
Test status
Simulation time	138344702 ps
CPU time	1.5 seconds
Started	Mar 14 01:08:16 PM PDT 24
Finished	Mar 14 01:08:18 PM PDT 24
Peak memory	230128 kb
Host	smart-2e98be4f-3676-44bb-9bb8-f4aea3aa2202
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584664147 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_intr_test.1584664147
Directory	/workspace/34.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.3728174402
Short name	T49
Test name
Test status
Simulation time	577075889 ps
CPU time	2.11 seconds
Started	Mar 14 01:08:10 PM PDT 24
Finished	Mar 14 01:08:12 PM PDT 24
Peak memory	229296 kb
Host	smart-0553dcc4-4828-41d0-ae27-e042d7e5c76a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728174402 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_intr_test.3728174402
Directory	/workspace/35.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.1575856553
Short name	T1
Test name
Test status
Simulation time	43896364 ps
CPU time	1.51 seconds
Started	Mar 14 01:08:11 PM PDT 24
Finished	Mar 14 01:08:12 PM PDT 24
Peak memory	229252 kb
Host	smart-0e543f2d-9bcb-4e70-a908-582bf7e2f9d9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575856553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_intr_test.1575856553
Directory	/workspace/36.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.3178715962
Short name	T87
Test name
Test status
Simulation time	44628044 ps
CPU time	1.44 seconds
Started	Mar 14 01:08:12 PM PDT 24
Finished	Mar 14 01:08:14 PM PDT 24
Peak memory	229224 kb
Host	smart-cf8c00ae-b252-406c-96db-bbcb0dff5610
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178715962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_intr_test.3178715962
Directory	/workspace/37.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.521463475
Short name	T101
Test name
Test status
Simulation time	144718040 ps
CPU time	1.45 seconds
Started	Mar 14 01:08:11 PM PDT 24
Finished	Mar 14 01:08:13 PM PDT 24
Peak memory	230072 kb
Host	smart-573f72b8-eb8a-456f-98b9-e43d0f401ce8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521463475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_intr_test.521463475
Directory	/workspace/38.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.3916558005
Short name	T161
Test name
Test status
Simulation time	138285125 ps
CPU time	1.45 seconds
Started	Mar 14 01:08:11 PM PDT 24
Finished	Mar 14 01:08:12 PM PDT 24
Peak memory	229324 kb
Host	smart-a68adddb-08f0-4171-a410-e4a89928315d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916558005 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_intr_test.3916558005
Directory	/workspace/39.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.3538785286
Short name	T61
Test name
Test status
Simulation time	475504044 ps
CPU time	4.37 seconds
Started	Mar 14 01:07:21 PM PDT 24
Finished	Mar 14 01:07:26 PM PDT 24
Peak memory	240784 kb
Host	smart-8a2eaa20-d9ad-4ca0-b0af-a96be11874bf
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538785286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_alia sing.3538785286
Directory	/workspace/4.otp_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.2335099176
Short name	T41
Test name
Test status
Simulation time	131177997 ps
CPU time	6.55 seconds
Started	Mar 14 01:07:21 PM PDT 24
Finished	Mar 14 01:07:28 PM PDT 24
Peak memory	239728 kb
Host	smart-f1133f7b-0776-4a3d-abc2-d78405105468
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335099176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_bit_ bash.2335099176
Directory	/workspace/4.otp_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.677736601
Short name	T85
Test name
Test status
Simulation time	75130416 ps
CPU time	3.06 seconds
Started	Mar 14 01:07:39 PM PDT 24
Finished	Mar 14 01:07:42 PM PDT 24
Peak memory	246612 kb
Host	smart-cc43c887-b22c-4218-8890-07822a5e31ae
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677736601 -assert nopostproc +UVM_TESTNAME= otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_mem_rw_with_rand_reset.677736601
Directory	/workspace/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.689018223
Short name	T55
Test name
Test status
Simulation time	76422009 ps
CPU time	1.61 seconds
Started	Mar 14 01:07:21 PM PDT 24
Finished	Mar 14 01:07:23 PM PDT 24
Peak memory	240032 kb
Host	smart-e18793fa-c546-472f-821d-709e7418dd85
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689018223 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_rw.689018223
Directory	/workspace/4.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.1301643797
Short name	T88
Test name
Test status
Simulation time	43184918 ps
CPU time	1.38 seconds
Started	Mar 14 01:07:21 PM PDT 24
Finished	Mar 14 01:07:22 PM PDT 24
Peak memory	230160 kb
Host	smart-8c173a26-d4fe-4337-a25e-e8e2559b6265
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301643797 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_intr_test.1301643797
Directory	/workspace/4.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.1461152349
Short name	T103
Test name
Test status
Simulation time	40572232 ps
CPU time	1.35 seconds
Started	Mar 14 01:07:21 PM PDT 24
Finished	Mar 14 01:07:23 PM PDT 24
Peak memory	228964 kb
Host	smart-d9614454-455a-4398-8e6b-9c23bd0eabe2
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461152349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctr l_mem_partial_access.1461152349
Directory	/workspace/4.otp_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.3048880085
Short name	T140
Test name
Test status
Simulation time	129684040 ps
CPU time	1.4 seconds
Started	Mar 14 01:07:20 PM PDT 24
Finished	Mar 14 01:07:22 PM PDT 24
Peak memory	229468 kb
Host	smart-c6b8ea27-bb16-401b-999e-5d2674fa8436
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048880085 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_walk .3048880085
Directory	/workspace/4.otp_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.624277350
Short name	T77
Test name
Test status
Simulation time	1437149149 ps
CPU time	5 seconds
Started	Mar 14 01:07:21 PM PDT 24
Finished	Mar 14 01:07:26 PM PDT 24
Peak memory	246252 kb
Host	smart-07dc5736-6d67-4283-8cb0-8c95f8ee60e2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624277350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_errors.624277350
Directory	/workspace/4.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.1660544755
Short name	T28
Test name
Test status
Simulation time	662539939 ps
CPU time	11.37 seconds
Started	Mar 14 01:07:22 PM PDT 24
Finished	Mar 14 01:07:34 PM PDT 24
Peak memory	242928 kb
Host	smart-c6a065d3-9119-44ef-9b30-9dc75f9bd11c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660544755 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_in tg_err.1660544755
Directory	/workspace/4.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.869398259
Short name	T164
Test name
Test status
Simulation time	510115990 ps
CPU time	1.53 seconds
Started	Mar 14 01:08:12 PM PDT 24
Finished	Mar 14 01:08:14 PM PDT 24
Peak memory	229564 kb
Host	smart-bdf3dd8e-32c2-45b4-8fed-318af8ba2517
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869398259 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_intr_test.869398259
Directory	/workspace/40.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.3844285990
Short name	T89
Test name
Test status
Simulation time	40552846 ps
CPU time	1.43 seconds
Started	Mar 14 01:08:17 PM PDT 24
Finished	Mar 14 01:08:18 PM PDT 24
Peak memory	229304 kb
Host	smart-0fce8790-11f5-4e97-a2f4-3a92ac3e15c5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844285990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_intr_test.3844285990
Directory	/workspace/42.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.2156159083
Short name	T99
Test name
Test status
Simulation time	47660865 ps
CPU time	1.51 seconds
Started	Mar 14 01:08:11 PM PDT 24
Finished	Mar 14 01:08:13 PM PDT 24
Peak memory	229252 kb
Host	smart-536b0e2b-ad4c-47bd-8312-bda7e4d036e3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156159083 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_intr_test.2156159083
Directory	/workspace/43.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.2161617689
Short name	T131
Test name
Test status
Simulation time	36227828 ps
CPU time	1.38 seconds
Started	Mar 14 01:08:13 PM PDT 24
Finished	Mar 14 01:08:14 PM PDT 24
Peak memory	229520 kb
Host	smart-3249b8f7-9094-43c0-a051-b6bf754c9c04
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161617689 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_intr_test.2161617689
Directory	/workspace/44.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.850029794
Short name	T91
Test name
Test status
Simulation time	141117957 ps
CPU time	1.45 seconds
Started	Mar 14 01:08:16 PM PDT 24
Finished	Mar 14 01:08:18 PM PDT 24
Peak memory	230128 kb
Host	smart-541f61f8-2bef-4122-b332-b6b9645c3c65
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850029794 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_intr_test.850029794
Directory	/workspace/45.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.3491893825
Short name	T117
Test name
Test status
Simulation time	72999738 ps
CPU time	1.41 seconds
Started	Mar 14 01:08:18 PM PDT 24
Finished	Mar 14 01:08:19 PM PDT 24
Peak memory	229268 kb
Host	smart-d52dc257-23a4-4293-9a55-8a21caa72c93
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491893825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_intr_test.3491893825
Directory	/workspace/46.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.1729251821
Short name	T129
Test name
Test status
Simulation time	136890584 ps
CPU time	1.49 seconds
Started	Mar 14 01:08:15 PM PDT 24
Finished	Mar 14 01:08:17 PM PDT 24
Peak memory	230096 kb
Host	smart-f378f637-90ab-4073-8e71-dfeec22ac01d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729251821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_intr_test.1729251821
Directory	/workspace/47.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.3590764423
Short name	T90
Test name
Test status
Simulation time	143382114 ps
CPU time	1.6 seconds
Started	Mar 14 01:08:11 PM PDT 24
Finished	Mar 14 01:08:13 PM PDT 24
Peak memory	229520 kb
Host	smart-c3d4b01c-8803-4280-863d-ef11ac15c0dd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590764423 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_intr_test.3590764423
Directory	/workspace/48.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.1902444651
Short name	T40
Test name
Test status
Simulation time	157907236 ps
CPU time	1.52 seconds
Started	Mar 14 01:08:17 PM PDT 24
Finished	Mar 14 01:08:18 PM PDT 24
Peak memory	229316 kb
Host	smart-2d634959-ecf9-4368-9c6e-7fe76bbd7267
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902444651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_intr_test.1902444651
Directory	/workspace/49.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.930969389
Short name	T60
Test name
Test status
Simulation time	181045548 ps
CPU time	2.24 seconds
Started	Mar 14 01:07:39 PM PDT 24
Finished	Mar 14 01:07:42 PM PDT 24
Peak memory	243228 kb
Host	smart-ccd3d4ab-79b2-4f4f-a351-63e5e5813189
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930969389 -assert nopostproc +UVM_TESTNAME= otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_mem_rw_with_rand_reset.930969389
Directory	/workspace/5.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.229493445
Short name	T48
Test name
Test status
Simulation time	569535531 ps
CPU time	1.95 seconds
Started	Mar 14 01:07:40 PM PDT 24
Finished	Mar 14 01:07:42 PM PDT 24
Peak memory	240372 kb
Host	smart-870a85f8-4ba8-4ea5-8bec-d37d2a2720c4
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229493445 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_rw.229493445
Directory	/workspace/5.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.2693784023
Short name	T141
Test name
Test status
Simulation time	144684537 ps
CPU time	1.52 seconds
Started	Mar 14 01:07:41 PM PDT 24
Finished	Mar 14 01:07:43 PM PDT 24
Peak memory	230108 kb
Host	smart-ef3a034e-67ac-4f71-b5d2-01ac4ad8e6f3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693784023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_intr_test.2693784023
Directory	/workspace/5.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.4016902667
Short name	T104
Test name
Test status
Simulation time	70214165 ps
CPU time	2.22 seconds
Started	Mar 14 01:07:40 PM PDT 24
Finished	Mar 14 01:07:42 PM PDT 24
Peak memory	238352 kb
Host	smart-615fda57-9ef3-4503-8f7f-f9623ad844e8
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016902667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_c trl_same_csr_outstanding.4016902667
Directory	/workspace/5.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.3754936862
Short name	T20
Test name
Test status
Simulation time	189148187 ps
CPU time	2.89 seconds
Started	Mar 14 01:07:38 PM PDT 24
Finished	Mar 14 01:07:41 PM PDT 24
Peak memory	245060 kb
Host	smart-208904ed-6136-4a98-85d0-943ffd5febd2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754936862 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_errors.3754936862
Directory	/workspace/5.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.2153295649
Short name	T4
Test name
Test status
Simulation time	10330947145 ps
CPU time	16.73 seconds
Started	Mar 14 01:07:42 PM PDT 24
Finished	Mar 14 01:07:59 PM PDT 24
Peak memory	243348 kb
Host	smart-9576acd9-e035-4ea0-b1c2-2150a36f154e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153295649 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_in tg_err.2153295649
Directory	/workspace/5.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.4146295377
Short name	T136
Test name
Test status
Simulation time	405832197 ps
CPU time	2.9 seconds
Started	Mar 14 01:07:40 PM PDT 24
Finished	Mar 14 01:07:43 PM PDT 24
Peak memory	246648 kb
Host	smart-3bc79d71-fc88-4fdc-8676-cdf8fd85caac
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146295377 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_mem_rw_with_rand_reset.4146295377
Directory	/workspace/6.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.1750117946
Short name	T29
Test name
Test status
Simulation time	147170776 ps
CPU time	1.6 seconds
Started	Mar 14 01:07:38 PM PDT 24
Finished	Mar 14 01:07:40 PM PDT 24
Peak memory	240048 kb
Host	smart-b3eb3ff3-459f-4b2b-84b8-b3ed14339437
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750117946 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_rw.1750117946
Directory	/workspace/6.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.1045038906
Short name	T174
Test name
Test status
Simulation time	41388098 ps
CPU time	1.46 seconds
Started	Mar 14 01:07:39 PM PDT 24
Finished	Mar 14 01:07:41 PM PDT 24
Peak memory	229136 kb
Host	smart-347fd119-6c28-48cb-a80b-9476a50fca62
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045038906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_intr_test.1045038906
Directory	/workspace/6.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.262007096
Short name	T112
Test name
Test status
Simulation time	958442405 ps
CPU time	2.69 seconds
Started	Mar 14 01:07:38 PM PDT 24
Finished	Mar 14 01:07:41 PM PDT 24
Peak memory	238284 kb
Host	smart-93e8fc5f-32b1-409c-b6a6-1c646ec81a1f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262007096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ct rl_same_csr_outstanding.262007096
Directory	/workspace/6.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.2610534286
Short name	T22
Test name
Test status
Simulation time	131768326 ps
CPU time	4.81 seconds
Started	Mar 14 01:07:42 PM PDT 24
Finished	Mar 14 01:07:47 PM PDT 24
Peak memory	245612 kb
Host	smart-bd13fbbb-9fcd-478f-af29-a8d6905b3575
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610534286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_errors.2610534286
Directory	/workspace/6.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.1747137179
Short name	T116
Test name
Test status
Simulation time	1205355017 ps
CPU time	10.01 seconds
Started	Mar 14 01:07:40 PM PDT 24
Finished	Mar 14 01:07:50 PM PDT 24
Peak memory	242948 kb
Host	smart-e0a2a245-2dba-436d-b1d6-a3aab2d09d6e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747137179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_in tg_err.1747137179
Directory	/workspace/6.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.3935369842
Short name	T95
Test name
Test status
Simulation time	1164205342 ps
CPU time	3.58 seconds
Started	Mar 14 01:07:41 PM PDT 24
Finished	Mar 14 01:07:45 PM PDT 24
Peak memory	246652 kb
Host	smart-13696602-b7df-4a0e-877b-c6d2ff149ffd
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935369842 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_mem_rw_with_rand_reset.3935369842
Directory	/workspace/7.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.2104970065
Short name	T146
Test name
Test status
Simulation time	37155097 ps
CPU time	1.54 seconds
Started	Mar 14 01:07:41 PM PDT 24
Finished	Mar 14 01:07:43 PM PDT 24
Peak memory	239760 kb
Host	smart-b5a1a419-e929-4f5c-be82-70943ca99868
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104970065 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_rw.2104970065
Directory	/workspace/7.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.279981635
Short name	T152
Test name
Test status
Simulation time	140873009 ps
CPU time	1.44 seconds
Started	Mar 14 01:07:38 PM PDT 24
Finished	Mar 14 01:07:40 PM PDT 24
Peak memory	229408 kb
Host	smart-fc01514e-d104-4462-b2cc-6a13548bfd7f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279981635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_intr_test.279981635
Directory	/workspace/7.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.3963987192
Short name	T137
Test name
Test status
Simulation time	996486595 ps
CPU time	2.57 seconds
Started	Mar 14 01:07:40 PM PDT 24
Finished	Mar 14 01:07:43 PM PDT 24
Peak memory	241140 kb
Host	smart-56e3dbc0-805c-4c4a-b175-4e4edd196d88
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963987192 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_c trl_same_csr_outstanding.3963987192
Directory	/workspace/7.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.1045572363
Short name	T19
Test name
Test status
Simulation time	1194745411 ps
CPU time	3.94 seconds
Started	Mar 14 01:07:41 PM PDT 24
Finished	Mar 14 01:07:45 PM PDT 24
Peak memory	245312 kb
Host	smart-f511fd33-7763-405c-bc6e-8d2e6d052184
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045572363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_errors.1045572363
Directory	/workspace/7.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.3821551137
Short name	T168
Test name
Test status
Simulation time	4856490972 ps
CPU time	22.53 seconds
Started	Mar 14 01:07:39 PM PDT 24
Finished	Mar 14 01:08:01 PM PDT 24
Peak memory	238456 kb
Host	smart-7009c99b-1b79-423f-b0c9-929865ab81d8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821551137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_in tg_err.3821551137
Directory	/workspace/7.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.1901156097
Short name	T67
Test name
Test status
Simulation time	204139583 ps
CPU time	3.47 seconds
Started	Mar 14 01:07:41 PM PDT 24
Finished	Mar 14 01:07:45 PM PDT 24
Peak memory	246580 kb
Host	smart-0226006d-4e86-47f4-a301-9f89c95e0d49
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901156097 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_mem_rw_with_rand_reset.1901156097
Directory	/workspace/8.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.544973368
Short name	T109
Test name
Test status
Simulation time	63681433 ps
CPU time	1.52 seconds
Started	Mar 14 01:07:39 PM PDT 24
Finished	Mar 14 01:07:40 PM PDT 24
Peak memory	238196 kb
Host	smart-9f7c6f3b-a262-4b6b-bc8e-93a4480c1143
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544973368 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_rw.544973368
Directory	/workspace/8.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.2899195762
Short name	T105
Test name
Test status
Simulation time	69929441 ps
CPU time	1.42 seconds
Started	Mar 14 01:07:41 PM PDT 24
Finished	Mar 14 01:07:42 PM PDT 24
Peak memory	230180 kb
Host	smart-b8d0ddf2-256c-4e66-88eb-5c9dd9ad6f5e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899195762 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_intr_test.2899195762
Directory	/workspace/8.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.557539011
Short name	T147
Test name
Test status
Simulation time	237291796 ps
CPU time	3.56 seconds
Started	Mar 14 01:07:38 PM PDT 24
Finished	Mar 14 01:07:42 PM PDT 24
Peak memory	241384 kb
Host	smart-5fb5075b-773f-43ed-9717-0894a49f87b0
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557539011 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ct rl_same_csr_outstanding.557539011
Directory	/workspace/8.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.825894291
Short name	T119
Test name
Test status
Simulation time	1043788715 ps
CPU time	2.34 seconds
Started	Mar 14 01:07:39 PM PDT 24
Finished	Mar 14 01:07:41 PM PDT 24
Peak memory	238388 kb
Host	smart-07004a77-44df-49de-ab5a-54f4eaa94de5
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825894291 -assert nopostproc +UVM_TESTNAME= otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_mem_rw_with_rand_reset.825894291
Directory	/workspace/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.1186863596
Short name	T108
Test name
Test status
Simulation time	51456374 ps
CPU time	1.72 seconds
Started	Mar 14 01:07:40 PM PDT 24
Finished	Mar 14 01:07:42 PM PDT 24
Peak memory	240528 kb
Host	smart-9b3e2528-7ef0-4bfd-bf18-15f94f2e1936
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186863596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_rw.1186863596
Directory	/workspace/9.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.2894410431
Short name	T86
Test name
Test status
Simulation time	45815879 ps
CPU time	1.7 seconds
Started	Mar 14 01:07:41 PM PDT 24
Finished	Mar 14 01:07:43 PM PDT 24
Peak memory	229556 kb
Host	smart-08f75fc7-1730-4fbb-9c40-4945b0b3033e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894410431 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_intr_test.2894410431
Directory	/workspace/9.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.532468194
Short name	T165
Test name
Test status
Simulation time	655586616 ps
CPU time	2.09 seconds
Started	Mar 14 01:07:39 PM PDT 24
Finished	Mar 14 01:07:41 PM PDT 24
Peak memory	241124 kb
Host	smart-acf1f454-3cab-4cce-a3a3-b5301f89c4f4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532468194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ct rl_same_csr_outstanding.532468194
Directory	/workspace/9.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.1818478821
Short name	T17
Test name
Test status
Simulation time	4864497891 ps
CPU time	21.1 seconds
Started	Mar 14 01:07:39 PM PDT 24
Finished	Mar 14 01:08:00 PM PDT 24
Peak memory	244036 kb
Host	smart-88d7afd3-b117-4f04-9a8a-53bdda8ab09c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818478821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_in tg_err.1818478821
Directory	/workspace/9.otp_ctrl_tl_intg_err/latest