Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=65616,DigestOffset=56,StateWidth=10 )
Line Coverage for Module self-instances :
SCORELINE
97.23 100.00
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Line No.TotalCoveredPercent
TOTAL938692.47
CONT_ASSIGN13811100.00
ALWAYS15333100.00
ALWAYS164686189.71
CONT_ASSIGN33411100.00
CONT_ASSIGN33611100.00
CONT_ASSIGN33911100.00
CONT_ASSIGN34911100.00
CONT_ASSIGN35011100.00
CONT_ASSIGN35411100.00
CONT_ASSIGN35811100.00
CONT_ASSIGN39511100.00
CONT_ASSIGN42011100.00
CONT_ASSIGN45411100.00
ALWAYS46133100.00
ALWAYS46488100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
138 1 1
153 1 1
154 1 1
156 1 1
164 1 1
167 1 1
170 1 1
171 1 1
174 1 1
175 1 1
176 1 1
179 1 1
182 1 1
183 1 1
184 1 1
186 1 1
191 1 1
193 1 1
194 1 1
196 unreachable
MISSING_ELSE
205 1 1
206 1 1
207 1 1
==> MISSING_ELSE
215 1 1
216 1 1
217 1 1
218 1 1
220 1 1
221 0 1
MISSING_ELSE
224 0 1
225 0 1
MISSING_ELSE
233 1 1
234 1 1
235 1 1
236 1 1
237 1 1
MISSING_ELSE
246 1 1
248 1 1
249 1 1
250 1 1
251 1 1
252 1 1
MISSING_ELSE
255 1 1
256 1 1
257 1 1
258 1 1
266 1 1
267 1 1
268 1 1
269 1 1
270 1 1
272 1 1
273 0 1
MISSING_ELSE
276 0 1
277 0 1
279 0 1
MISSING_ELSE
288 1 1
289 1 1
MISSING_ELSE
293 1 1
294 1 1
295 1 1
296 1 1
297 1 1
298 1 1
MISSING_ELSE
314 1 1
315 1 1
316 1 1
317 1 1
MISSING_ELSE
MISSING_ELSE
321 1 1
322 1 1
323 1 1
324 1 1
325 1 1
MISSING_ELSE
MISSING_ELSE
334 1 1
336 1 1
339 1 1
349 1 1
350 1 1
354 1 1
358 1 1
395 1 1
420 1 1
454 1 1
461 3 3
464 1 1
465 1 1
466 1 1
467 1 1
469 1 1
470 1 1
471 1 1
472 1 1
MISSING_ELSE


Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=134651988,DigestOffset=480,StateWidth=10 )
Line Coverage for Module self-instances :
SCORELINE
98.33 100.00
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Line No.TotalCoveredPercent
TOTAL9191100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN14911100.00
ALWAYS1646868100.00
CONT_ASSIGN33411100.00
CONT_ASSIGN33611100.00
CONT_ASSIGN34211100.00
CONT_ASSIGN34911100.00
CONT_ASSIGN35011100.00
CONT_ASSIGN35411100.00
CONT_ASSIGN35811100.00
CONT_ASSIGN39511100.00
CONT_ASSIGN42011100.00
CONT_ASSIGN45411100.00
ALWAYS46133100.00
ALWAYS46488100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
138 1 1
149 1 1
164 1 1
167 1 1
170 1 1
171 1 1
174 1 1
175 1 1
176 1 1
179 1 1
182 1 1
183 1 1
184 1 1
186 1 1
191 1 1
193 1 1
194 1 1
196 unreachable
MISSING_ELSE
205 1 1
206 1 1
207 1 1
MISSING_ELSE
215 1 1
216 1 1
217 1 1
218 1 1
220 1 1
221 1 1
MISSING_ELSE
224 1 1
225 1 1
MISSING_ELSE
233 1 1
234 1 1
235 1 1
236 1 1
237 1 1
MISSING_ELSE
246 1 1
248 1 1
249 1 1
250 1 1
251 1 1
252 1 1
MISSING_ELSE
255 1 1
256 1 1
257 1 1
258 1 1
266 1 1
267 1 1
268 1 1
269 1 1
270 1 1
272 1 1
273 1 1
MISSING_ELSE
276 1 1
277 1 1
279 1 1
MISSING_ELSE
288 1 1
289 1 1
MISSING_ELSE
293 1 1
294 1 1
295 1 1
296 1 1
297 1 1
298 1 1
MISSING_ELSE
314 1 1
315 1 1
316 1 1
317 1 1
MISSING_ELSE
MISSING_ELSE
321 1 1
322 1 1
323 1 1
324 1 1
325 1 1
MISSING_ELSE
MISSING_ELSE
334 1 1
336 1 1
342 1 1
349 1 1
350 1 1
354 1 1
358 1 1
395 1 1
420 1 1
454 1 1
461 3 3
464 1 1
465 1 1
466 1 1
467 1 1
469 1 1
470 1 1
471 1 1
472 1 1
MISSING_ELSE


Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=1024082004,DigestOffset=1136,StateWidth=10 )
Line Coverage for Module self-instances :
SCORELINE
98.33 100.00
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Line No.TotalCoveredPercent
TOTAL9191100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN14911100.00
ALWAYS1646868100.00
CONT_ASSIGN33411100.00
CONT_ASSIGN33611100.00
CONT_ASSIGN34211100.00
CONT_ASSIGN34911100.00
CONT_ASSIGN35011100.00
CONT_ASSIGN35411100.00
CONT_ASSIGN35811100.00
CONT_ASSIGN39511100.00
CONT_ASSIGN42011100.00
CONT_ASSIGN45411100.00
ALWAYS46133100.00
ALWAYS46488100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
138 1 1
149 1 1
164 1 1
167 1 1
170 1 1
171 1 1
174 1 1
175 1 1
176 1 1
179 1 1
182 1 1
183 1 1
184 1 1
186 1 1
191 1 1
193 1 1
194 1 1
196 unreachable
MISSING_ELSE
205 1 1
206 1 1
207 1 1
MISSING_ELSE
215 1 1
216 1 1
217 1 1
218 1 1
220 1 1
221 1 1
MISSING_ELSE
224 1 1
225 1 1
MISSING_ELSE
233 1 1
234 1 1
235 1 1
236 1 1
237 1 1
MISSING_ELSE
246 1 1
248 1 1
249 1 1
250 1 1
251 1 1
252 1 1
MISSING_ELSE
255 1 1
256 1 1
257 1 1
258 1 1
266 1 1
267 1 1
268 1 1
269 1 1
270 1 1
272 1 1
273 1 1
MISSING_ELSE
276 1 1
277 1 1
279 1 1
MISSING_ELSE
288 1 1
289 1 1
MISSING_ELSE
293 1 1
294 1 1
295 1 1
296 1 1
297 1 1
298 1 1
MISSING_ELSE
314 1 1
315 1 1
316 1 1
317 1 1
MISSING_ELSE
MISSING_ELSE
321 1 1
322 1 1
323 1 1
324 1 1
325 1 1
MISSING_ELSE
MISSING_ELSE
334 1 1
336 1 1
342 1 1
349 1 1
350 1 1
354 1 1
358 1 1
395 1 1
420 1 1
454 1 1
461 3 3
464 1 1
465 1 1
466 1 1
467 1 1
469 1 1
470 1 1
471 1 1
472 1 1
MISSING_ELSE


Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=-1,DigestOffset=1608,StateWidth=10 )
Line Coverage for Module self-instances :
SCORELINE
93.12 96.70
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Line No.TotalCoveredPercent
TOTAL918896.70
CONT_ASSIGN13811100.00
CONT_ASSIGN14911100.00
ALWAYS164686595.59
CONT_ASSIGN33411100.00
CONT_ASSIGN33611100.00
CONT_ASSIGN34211100.00
CONT_ASSIGN34911100.00
CONT_ASSIGN35011100.00
CONT_ASSIGN35411100.00
CONT_ASSIGN35811100.00
CONT_ASSIGN39511100.00
CONT_ASSIGN42011100.00
CONT_ASSIGN45411100.00
ALWAYS46133100.00
ALWAYS46488100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
138 1 1
149 1 1
164 1 1
167 1 1
170 1 1
171 1 1
174 1 1
175 1 1
176 1 1
179 1 1
182 1 1
183 1 1
184 1 1
186 1 1
191 1 1
193 1 1
194 1 1
196 unreachable
MISSING_ELSE
205 1 1
206 1 1
207 1 1
MISSING_ELSE
215 1 1
216 1 1
217 1 1
218 1 1
220 1 1
221 1 1
MISSING_ELSE
224 1 1
225 1 1
MISSING_ELSE
233 1 1
234 1 1
235 1 1
236 1 1
237 1 1
MISSING_ELSE
246 1 1
248 1 1
249 1 1
250 1 1
251 1 1
252 1 1
MISSING_ELSE
255 1 1
256 1 1
257 1 1
258 1 1
266 1 1
267 1 1
268 1 1
269 1 1
270 1 1
272 1 1
273 1 1
MISSING_ELSE
276 1 1
277 1 1
279 1 1
MISSING_ELSE
288 1 1
289 1 1
MISSING_ELSE
293 1 1
294 1 1
295 1 1
296 1 1
297 1 1
298 1 1
MISSING_ELSE
314 1 1
315 0 1
316 0 1
317 0 1
==> MISSING_ELSE
MISSING_ELSE
321 1 1
322 1 1
323 1 1
324 1 1
325 1 1
MISSING_ELSE
MISSING_ELSE
334 1 1
336 1 1
342 1 1
349 1 1
350 1 1
354 1 1
358 1 1
395 1 1
420 1 1
454 1 1
461 3 3
464 1 1
465 1 1
466 1 1
467 1 1
469 1 1
470 1 1
471 1 1
472 1 1
MISSING_ELSE


Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=-1,DigestOffset=1648,StateWidth=10 )
Line Coverage for Module self-instances :
SCORELINE
98.33 100.00
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Line No.TotalCoveredPercent
TOTAL9191100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN14911100.00
ALWAYS1646868100.00
CONT_ASSIGN33411100.00
CONT_ASSIGN33611100.00
CONT_ASSIGN34211100.00
CONT_ASSIGN34911100.00
CONT_ASSIGN35011100.00
CONT_ASSIGN35411100.00
CONT_ASSIGN35811100.00
CONT_ASSIGN39511100.00
CONT_ASSIGN42011100.00
CONT_ASSIGN45411100.00
ALWAYS46133100.00
ALWAYS46488100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
138 1 1
149 1 1
164 1 1
167 1 1
170 1 1
171 1 1
174 1 1
175 1 1
176 1 1
179 1 1
182 1 1
183 1 1
184 1 1
186 1 1
191 1 1
193 1 1
194 1 1
196 unreachable
MISSING_ELSE
205 1 1
206 1 1
207 1 1
MISSING_ELSE
215 1 1
216 1 1
217 1 1
218 1 1
220 1 1
221 1 1
MISSING_ELSE
224 1 1
225 1 1
MISSING_ELSE
233 1 1
234 1 1
235 1 1
236 1 1
237 1 1
MISSING_ELSE
246 1 1
248 1 1
249 1 1
250 1 1
251 1 1
252 1 1
MISSING_ELSE
255 1 1
256 1 1
257 1 1
258 1 1
266 1 1
267 1 1
268 1 1
269 1 1
270 1 1
272 1 1
273 1 1
MISSING_ELSE
276 1 1
277 1 1
279 1 1
MISSING_ELSE
288 1 1
289 1 1
MISSING_ELSE
293 1 1
294 1 1
295 1 1
296 1 1
297 1 1
298 1 1
MISSING_ELSE
314 1 1
315 1 1
316 1 1
317 1 1
MISSING_ELSE
MISSING_ELSE
321 1 1
322 1 1
323 1 1
324 1 1
325 1 1
MISSING_ELSE
MISSING_ELSE
334 1 1
336 1 1
342 1 1
349 1 1
350 1 1
354 1 1
358 1 1
395 1 1
420 1 1
454 1 1
461 3 3
464 1 1
465 1 1
466 1 1
467 1 1
469 1 1
470 1 1
471 1 1
472 1 1
MISSING_ELSE


Cond Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=-1,DigestOffset=1608,StateWidth=10 )
Cond Coverage for Module self-instances :
SCORECOND
93.12 93.94
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

TotalCoveredPercent
Conditions343191.18
Logical343191.18
Non-Logical00
Event00

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT74,T76,T141

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------
-1-StatusTests
0CoveredT3,T4,T10
1CoveredT1,T93,T142

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT21,T22,T23

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T4

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T9
11CoveredT1,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b10001111000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T92,T28

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T92,T28

Cond Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=65616,DigestOffset=56,StateWidth=10 )
Cond Coverage for Module self-instances :
SCORECOND
97.23 100.00
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

TotalCoveredPercent
Conditions312993.55
Logical312993.55
Non-Logical00
Event00

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------
-1-StatusTests
0CoveredT1,T3,T9
1Not Covered

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT21,T22,T23

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------
-1-StatusTests
0CoveredT4,T72,T143
1CoveredT4,T72,T143

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T11

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T9

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T9,T5
11CoveredT1,T3,T9

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------
-1-StatusTests
0CoveredT1,T3,T9
1CoveredT1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))
-1-StatusTests
0CoveredT1,T3,T9
1CoveredT1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T5,T27

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T5,T27

Cond Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=134651988,DigestOffset=480,StateWidth=10 )
Cond Coverage for Module self-instances :
SCORECOND
98.33 100.00
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

TotalCoveredPercent
Conditions343397.06
Logical343397.06
Non-Logical00
Event00

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT11,T103,T144

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------
-1-StatusTests
0CoveredT3,T9,T4
1CoveredT93,T29,T145

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT21,T22,T23

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------
-1-StatusTests
0CoveredT4,T72,T143
1CoveredT4,T72,T143

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T11

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T9,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T9,T5
11CoveredT3,T9,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T3,T9

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------
-1-StatusTests
0CoveredT3,T9,T4
1CoveredT1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))
-1-StatusTests
0CoveredT3,T9,T4
1CoveredT1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T27,T92

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T27,T92

Cond Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=1024082004,DigestOffset=1136,StateWidth=10 )
Cond Coverage for Module self-instances :
SCORECOND
98.33 100.00
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

TotalCoveredPercent
Conditions343397.06
Logical343397.06
Non-Logical00
Event00

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT11,T73,T74

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------
-1-StatusTests
0CoveredT3,T4,T10
1CoveredT142,T29,T46

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT21,T22,T23

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------
-1-StatusTests
0CoveredT72,T146,T147
1CoveredT72,T146,T147

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T4

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T10

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T9
11CoveredT3,T4,T10

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00111101000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T5,T27

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T5,T27

Cond Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=-1,DigestOffset=1648,StateWidth=10 )
Cond Coverage for Module self-instances :
SCORECOND
98.33 100.00
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

TotalCoveredPercent
Conditions343397.06
Logical343397.06
Non-Logical00
Event00

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T25,T74

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------
-1-StatusTests
0CoveredT3,T4,T10
1CoveredT68,T29,T46

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT21,T22,T23

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------
-1-StatusTests
0CoveredT143,T147,T148
1CoveredT143,T147,T148

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T4

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T10

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T5
11CoveredT3,T4,T10

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b11001010000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT92,T100,T105

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT92,T100,T105

FSM Coverage for Module : otp_ctrl_part_unbuf
Summary for FSM :: state_q
TotalCoveredPercent
States 7 7 100.00 (Not included in score)
Transitions 14 12 85.71
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
ErrorSt 224 Covered T1,T2,T4
IdleSt 196 Covered T1,T2,T3
InitSt 194 Covered T1,T2,T3
InitWaitSt 207 Covered T1,T2,T3
ReadSt 236 Covered T1,T3,T9
ReadWaitSt 252 Covered T1,T3,T9
ResetSt 190 Covered T1,T2,T3


transitionsLine No.CoveredTests
IdleSt->ErrorSt 315 Covered T1,T11,T12
IdleSt->ReadSt 236 Covered T1,T3,T9
InitSt->ErrorSt 315 Covered T103,T115,T149
InitSt->InitWaitSt 207 Covered T1,T2,T3
InitWaitSt->ErrorSt 224 Covered T103,T115,T149
InitWaitSt->IdleSt 218 Covered T1,T2,T3
ReadSt->ErrorSt 315 Not Covered
ReadSt->IdleSt 255 Covered T9,T5,T6
ReadSt->ReadWaitSt 252 Covered T1,T3,T9
ReadWaitSt->ErrorSt 276 Covered T1,T145,T150
ReadWaitSt->IdleSt 270 Covered T1,T3,T9
ResetSt->ErrorSt 315 Covered T2,T4,T72
ResetSt->IdleSt 196 Not Covered
ResetSt->InitSt 194 Covered T1,T2,T3


Summary for FSM :: error_q
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 20 10 50.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: error_q
statesLine No.CoveredTests
AccessError 256 Covered T9,T5,T6
CheckFailError 317 Covered T4,T72,T143
FsmStateError 289 Covered T1,T2,T4
MacroEccCorrError 221 Covered T1,T11,T93
NoError 235 Covered T1,T2,T3


transitionsLine No.CoveredTests
AccessError->CheckFailError 317 Not Covered
AccessError->FsmStateError 325 Covered T6,T100,T14
AccessError->MacroEccCorrError 221 Not Covered
AccessError->NoError 235 Covered T9,T5,T6
CheckFailError->AccessError 256 Not Covered
CheckFailError->FsmStateError 325 Not Covered
CheckFailError->MacroEccCorrError 221 Not Covered
CheckFailError->NoError 235 Covered T4,T72,T143
FsmStateError->AccessError 256 Not Covered
FsmStateError->CheckFailError 317 Not Covered
FsmStateError->MacroEccCorrError 221 Not Covered
FsmStateError->NoError 235 Covered T1,T2,T4
MacroEccCorrError->AccessError 256 Not Covered
MacroEccCorrError->CheckFailError 317 Not Covered
MacroEccCorrError->FsmStateError 325 Covered T1,T11,T24
MacroEccCorrError->NoError 235 Covered T93,T68,T29
NoError->AccessError 256 Covered T9,T5,T6
NoError->CheckFailError 317 Covered T4,T72,T143
NoError->FsmStateError 289 Covered T1,T2,T4
NoError->MacroEccCorrError 221 Covered T1,T11,T93



Branch Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=65616,DigestOffset=56,StateWidth=10 )
Branch Coverage for Module self-instances :
SCOREBRANCH
97.23 100.00
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Line No.TotalCoveredPercent
Branches 46 41 89.13
TERNARY 336 2 2 100.00
TERNARY 349 2 2 100.00
TERNARY 358 2 2 100.00
TERNARY 395 2 2 100.00
TERNARY 420 2 2 100.00
CASE 186 23 18 78.26
IF 314 3 3 100.00
IF 321 3 3 100.00
IF 461 2 2 100.00
IF 464 3 3 100.00
IF 153 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 336 ((tlul_rvalid_o && (tlul_rerror_o == '0))) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 349 ((otp_addr_sel == DigestAddrSel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T3,T9


LineNo. Expression -1-: 358 ((otp_addr_sel == DigestAddrSel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T3,T9


LineNo. Expression -1-: 395 ((~init_done_o)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 420 ((digest_o != '0)) ?

Branches:
-1-StatusTests
1 Covered T2,T5,T27
0 Covered T1,T2,T3


LineNo. Expression -1-: 186 case (state_q) -2-: 191 if (init_req_i) -3-: 193 if (1'b1) -4-: 206 if (otp_gnt_i) -5-: 215 if (otp_rvalid_i) -6-: 217 if ((otp_err inside {NoError, MacroEccCorrError})) -7-: 220 if ((otp_err != NoError)) -8-: 234 if (tlul_req_i) -9-: 248 if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock))) -10-: 251 if (otp_gnt_i) -11-: 267 if (otp_rvalid_i) -12-: 269 if ((otp_err inside {NoError, MacroEccCorrError})) -13-: 272 if ((otp_err != NoError)) -14-: 288 if ((error_q == NoError)) -15-: 293 if (pending_tlul_error_q) -16-: 296 if (tlul_req_i)

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15--16-StatusTests
ResetSt 1 1 - - - - - - - - - - - - - Covered T1,T2,T3
ResetSt 1 0 - - - - - - - - - - - - - Unreachable
ResetSt 0 - - - - - - - - - - - - - - Covered T1,T2,T3
InitSt - - 1 - - - - - - - - - - - - Covered T1,T2,T3
InitSt - - 0 - - - - - - - - - - - - Not Covered
InitWaitSt - - - 1 1 1 - - - - - - - - - Not Covered
InitWaitSt - - - 1 1 0 - - - - - - - - - Covered T1,T2,T3
InitWaitSt - - - 1 0 - - - - - - - - - - Not Covered
InitWaitSt - - - 0 - - - - - - - - - - - Covered T1,T2,T3
IdleSt - - - - - - 1 - - - - - - - - Covered T1,T3,T9
IdleSt - - - - - - 0 - - - - - - - - Covered T1,T2,T3
ReadSt - - - - - - - 1 1 - - - - - - Covered T1,T3,T9
ReadSt - - - - - - - 1 0 - - - - - - Covered T27,T92,T106
ReadSt - - - - - - - 0 - - - - - - - Covered T9,T5,T6
ReadWaitSt - - - - - - - - - 1 1 1 - - - Not Covered
ReadWaitSt - - - - - - - - - 1 1 0 - - - Covered T1,T3,T9
ReadWaitSt - - - - - - - - - 1 0 - - - - Not Covered
ReadWaitSt - - - - - - - - - 0 - - - - - Covered T1,T3,T9
ErrorSt - - - - - - - - - - - - 1 - - Covered T21,T22,T23
ErrorSt - - - - - - - - - - - - 0 - - Covered T1,T2,T4
ErrorSt - - - - - - - - - - - - - 1 - Covered T1,T13,T6
ErrorSt - - - - - - - - - - - - - 0 1 Covered T1,T13,T6
ErrorSt - - - - - - - - - - - - - 0 0 Covered T1,T2,T4
default - - - - - - - - - - - - - - - Covered T21,T22,T23


LineNo. Expression -1-: 314 if (ecc_err) -2-: 316 if ((state_q != ErrorSt))

Branches:
-1--2-StatusTests
1 1 Covered T4,T72,T143
1 0 Covered T4,T72,T143
0 - Covered T1,T2,T3


LineNo. Expression -1-: 321 if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)) -2-: 324 if ((state_q != ErrorSt))

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T11
1 0 Covered T1,T2,T4
0 - Covered T1,T2,T3


LineNo. Expression -1-: 461 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 464 if ((!rst_ni)) -2-: 471 if (tlul_gnt_o)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T3,T9
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 153 if ((otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}))

Branches:
-1-StatusTests
1 Covered T1,T11,T6
0 Covered T1,T2,T3


Branch Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=134651988,DigestOffset=480,StateWidth=10 + Info=1024082004,DigestOffset=1136,StateWidth=10 + Info=-1,DigestOffset=1608,StateWidth=10 + Info=-1,DigestOffset=1648,StateWidth=10 )
Branch Coverage for Module self-instances :
SCOREBRANCH
98.33 100.00
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

SCOREBRANCH
98.33 100.00
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

SCOREBRANCH
93.12 95.45
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

SCOREBRANCH
98.33 100.00
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Line No.TotalCoveredPercent
Branches 44 44 100.00
TERNARY 336 2 2 100.00
TERNARY 349 2 2 100.00
TERNARY 358 2 2 100.00
TERNARY 395 2 2 100.00
TERNARY 420 2 2 100.00
CASE 186 23 23 100.00
IF 314 3 3 100.00
IF 321 3 3 100.00
IF 461 2 2 100.00
IF 464 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 336 ((tlul_rvalid_o && (tlul_rerror_o == '0))) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 349 ((otp_addr_sel == DigestAddrSel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T3,T9


LineNo. Expression -1-: 358 ((otp_addr_sel == DigestAddrSel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T3,T9


LineNo. Expression -1-: 395 ((~init_done_o)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 420 ((digest_o != '0)) ?

Branches:
-1-StatusTests
1 Covered T2,T5,T27
0 Covered T1,T2,T3


LineNo. Expression -1-: 186 case (state_q) -2-: 191 if (init_req_i) -3-: 193 if (1'b1) -4-: 206 if (otp_gnt_i) -5-: 215 if (otp_rvalid_i) -6-: 217 if ((otp_err inside {NoError, MacroEccCorrError})) -7-: 220 if ((otp_err != NoError)) -8-: 234 if (tlul_req_i) -9-: 248 if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock))) -10-: 251 if (otp_gnt_i) -11-: 267 if (otp_rvalid_i) -12-: 269 if ((otp_err inside {NoError, MacroEccCorrError})) -13-: 272 if ((otp_err != NoError)) -14-: 288 if ((error_q == NoError)) -15-: 293 if (pending_tlul_error_q) -16-: 296 if (tlul_req_i)

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15--16-StatusTests
ResetSt 1 1 - - - - - - - - - - - - - Covered T1,T2,T3
ResetSt 1 0 - - - - - - - - - - - - - Unreachable
ResetSt 0 - - - - - - - - - - - - - - Covered T1,T2,T3
InitSt - - 1 - - - - - - - - - - - - Covered T1,T2,T3
InitSt - - 0 - - - - - - - - - - - - Covered T1,T2,T3
InitWaitSt - - - 1 1 1 - - - - - - - - - Covered T11,T103,T144
InitWaitSt - - - 1 1 0 - - - - - - - - - Covered T1,T2,T3
InitWaitSt - - - 1 0 - - - - - - - - - - Covered T103,T110,T115
InitWaitSt - - - 0 - - - - - - - - - - - Covered T1,T2,T3
IdleSt - - - - - - 1 - - - - - - - - Covered T1,T3,T9
IdleSt - - - - - - 0 - - - - - - - - Covered T1,T2,T3
ReadSt - - - - - - - 1 1 - - - - - - Covered T1,T3,T9
ReadSt - - - - - - - 1 0 - - - - - - Covered T27,T92,T28
ReadSt - - - - - - - 0 - - - - - - - Covered T9,T5,T6
ReadWaitSt - - - - - - - - - 1 1 1 - - - Covered T1,T93,T142
ReadWaitSt - - - - - - - - - 1 1 0 - - - Covered T3,T9,T4
ReadWaitSt - - - - - - - - - 1 0 - - - - Covered T1,T145,T150
ReadWaitSt - - - - - - - - - 0 - - - - - Covered T1,T3,T9
ErrorSt - - - - - - - - - - - - 1 - - Covered T21,T22,T23
ErrorSt - - - - - - - - - - - - 0 - - Covered T1,T2,T4
ErrorSt - - - - - - - - - - - - - 1 - Covered T1,T2,T13
ErrorSt - - - - - - - - - - - - - 0 1 Covered T1,T2,T13
ErrorSt - - - - - - - - - - - - - 0 0 Covered T1,T2,T4
default - - - - - - - - - - - - - - - Covered T21,T22,T23


LineNo. Expression -1-: 314 if (ecc_err) -2-: 316 if ((state_q != ErrorSt))

Branches:
-1--2-StatusTests
1 1 Covered T4,T72,T143
1 0 Covered T4,T72,T143
0 - Covered T1,T2,T3


LineNo. Expression -1-: 321 if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)) -2-: 324 if ((state_q != ErrorSt))

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T4
1 0 Covered T1,T2,T4
0 - Covered T1,T2,T3


LineNo. Expression -1-: 461 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 464 if ((!rst_ni)) -2-: 471 if (tlul_gnt_o)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


Assert Coverage for Module : otp_ctrl_part_unbuf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 26 26 100.00 26 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 26 26 100.00 26 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AccessKnown_A 2147483647 2147483647 0 0
DigestKnown_A 2147483647 2147483647 0 0
DigestOffsetMustBeRepresentable_A 5735 5735 0 0
EccErrorState_A 2147483647 44865 0 0
ErrorKnown_A 2147483647 2147483647 0 0
FsmStateKnown_A 2147483647 2147483647 0 0
InitDoneKnown_A 2147483647 2147483647 0 0
InitReadLocksPartition_A 2147483647 431687086 0 0
InitWriteLocksPartition_A 2147483647 431687086 0 0
OffsetMustBeBlockAligned_A 5735 5735 0 0
OtpAddrKnown_A 2147483647 2147483647 0 0
OtpCmdKnown_A 2147483647 2147483647 0 0
OtpErrorState_A 2147483647 210 0 0
OtpReqKnown_A 2147483647 2147483647 0 0
OtpSizeKnown_A 2147483647 2147483647 0 0
OtpWdataKnown_A 2147483647 2147483647 0 0
ReadLockPropagation_A 2147483647 946242468 0 0
SizeMustBeBlockAligned_A 5735 5735 0 0
TlulGntKnown_A 2147483647 2147483647 0 0
TlulRdataKnown_A 2147483647 2147483647 0 0
TlulReadOnReadLock_A 2147483647 43774 0 0
TlulRerrorKnown_A 2147483647 2147483647 0 0
TlulRvalidKnown_A 2147483647 2147483647 0 0
WriteLockPropagation_A 2147483647 11161829 0 0
gen_digest_write_lock.DigestWriteLocksPartition_A 2147483647 119510283 0 0
u_state_regs_A 2147483647 2147483647 0 0


AccessKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 616680 609270 0 0
T2 75805 74340 0 0
T3 63320 62495 0 0
T4 53690 52390 0 0
T5 906870 900990 0 0
T9 48100 45475 0 0
T10 240870 240520 0 0
T11 91425 90245 0 0
T12 61585 60310 0 0
T13 72685 71165 0 0

DigestKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 616680 609270 0 0
T2 75805 74340 0 0
T3 63320 62495 0 0
T4 53690 52390 0 0
T5 906870 900990 0 0
T9 48100 45475 0 0
T10 240870 240520 0 0
T11 91425 90245 0 0
T12 61585 60310 0 0
T13 72685 71165 0 0

DigestOffsetMustBeRepresentable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 5735 5735 0 0
T1 5 5 0 0
T2 5 5 0 0
T3 5 5 0 0
T4 5 5 0 0
T5 5 5 0 0
T9 5 5 0 0
T10 5 5 0 0
T11 5 5 0 0
T12 5 5 0 0
T13 5 5 0 0

EccErrorState_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 44865 0 0
T4 21476 6834 0 0
T5 362748 0 0 0
T6 1350016 0 0 0
T10 96348 0 0 0
T11 36570 0 0 0
T12 24634 0 0 0
T13 29074 0 0 0
T27 134692 0 0 0
T50 61896 0 0 0
T72 11547 8466 0 0
T108 105114 0 0 0
T143 9254 6090 0 0
T146 0 5864 0 0
T147 0 5014 0 0
T148 0 8526 0 0
T151 0 4071 0 0
T152 198696 0 0 0
T153 16972 0 0 0
T154 254101 0 0 0
T155 17260 0 0 0
T156 10779 0 0 0
T157 89209 0 0 0
T158 33949 0 0 0
T159 83015 0 0 0
T160 243902 0 0 0

ErrorKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 616680 609270 0 0
T2 75805 74340 0 0
T3 63320 62495 0 0
T4 53690 52390 0 0
T5 906870 900990 0 0
T9 48100 45475 0 0
T10 240870 240520 0 0
T11 91425 90245 0 0
T12 61585 60310 0 0
T13 72685 71165 0 0

FsmStateKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 616680 609270 0 0
T2 75805 74340 0 0
T3 63320 62495 0 0
T4 53690 52390 0 0
T5 906870 900990 0 0
T9 48100 45475 0 0
T10 240870 240520 0 0
T11 91425 90245 0 0
T12 61585 60310 0 0
T13 72685 71165 0 0

InitDoneKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 616680 609270 0 0
T2 75805 74340 0 0
T3 63320 62495 0 0
T4 53690 52390 0 0
T5 906870 900990 0 0
T9 48100 45475 0 0
T10 240870 240520 0 0
T11 91425 90245 0 0
T12 61585 60310 0 0
T13 72685 71165 0 0

InitReadLocksPartition_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 431687086 0 0
T1 616680 168351 0 0
T2 75805 25135 0 0
T3 63320 1465 0 0
T4 53690 23355 0 0
T5 906870 104570 0 0
T9 48100 1020 0 0
T10 240870 400 0 0
T11 91425 23815 0 0
T12 61585 23550 0 0
T13 72685 38020 0 0

InitWriteLocksPartition_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 431687086 0 0
T1 616680 168351 0 0
T2 75805 25135 0 0
T3 63320 1465 0 0
T4 53690 23355 0 0
T5 906870 104570 0 0
T9 48100 1020 0 0
T10 240870 400 0 0
T11 91425 23815 0 0
T12 61585 23550 0 0
T13 72685 38020 0 0

OffsetMustBeBlockAligned_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 5735 5735 0 0
T1 5 5 0 0
T2 5 5 0 0
T3 5 5 0 0
T4 5 5 0 0
T5 5 5 0 0
T9 5 5 0 0
T10 5 5 0 0
T11 5 5 0 0
T12 5 5 0 0
T13 5 5 0 0

OtpAddrKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 616680 609270 0 0
T2 75805 74340 0 0
T3 63320 62495 0 0
T4 53690 52390 0 0
T5 906870 900990 0 0
T9 48100 45475 0 0
T10 240870 240520 0 0
T11 91425 90245 0 0
T12 61585 60310 0 0
T13 72685 71165 0 0

OtpCmdKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 616680 609270 0 0
T2 75805 74340 0 0
T3 63320 62495 0 0
T4 53690 52390 0 0
T5 906870 900990 0 0
T9 48100 45475 0 0
T10 240870 240520 0 0
T11 91425 90245 0 0
T12 61585 60310 0 0
T13 72685 71165 0 0

OtpErrorState_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 210 0 0
T1 370008 2 0 0
T2 45483 0 0 0
T3 37992 0 0 0
T4 32214 0 0 0
T5 544122 0 0 0
T9 28860 0 0 0
T10 144522 0 0 0
T11 54855 0 0 0
T12 36951 0 0 0
T13 43611 0 0 0
T47 12412 0 0 0
T85 0 1 0 0
T87 0 1 0 0
T97 41507 0 0 0
T103 0 1 0 0
T110 0 1 0 0
T115 8524 1 0 0
T144 13153 1 0 0
T145 0 1 0 0
T149 14833 1 0 0
T154 0 2 0 0
T161 0 1 0 0
T162 0 1 0 0
T163 0 1 0 0
T164 0 1 0 0
T165 0 1 0 0
T166 0 1 0 0
T167 0 2 0 0
T168 0 1 0 0
T169 0 1 0 0
T170 0 1 0 0
T171 0 1 0 0
T172 12628 0 0 0
T173 13877 0 0 0
T174 135168 0 0 0
T175 21475 0 0 0
T176 36720 0 0 0

OtpReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 616680 609270 0 0
T2 75805 74340 0 0
T3 63320 62495 0 0
T4 53690 52390 0 0
T5 906870 900990 0 0
T9 48100 45475 0 0
T10 240870 240520 0 0
T11 91425 90245 0 0
T12 61585 60310 0 0
T13 72685 71165 0 0

OtpSizeKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 616680 609270 0 0
T2 75805 74340 0 0
T3 63320 62495 0 0
T4 53690 52390 0 0
T5 906870 900990 0 0
T9 48100 45475 0 0
T10 240870 240520 0 0
T11 91425 90245 0 0
T12 61585 60310 0 0
T13 72685 71165 0 0

OtpWdataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 616680 609270 0 0
T2 75805 74340 0 0
T3 63320 62495 0 0
T4 53690 52390 0 0
T5 906870 900990 0 0
T9 48100 45475 0 0
T10 240870 240520 0 0
T11 91425 90245 0 0
T12 61585 60310 0 0
T13 72685 71165 0 0

ReadLockPropagation_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 946242468 0 0
T1 246672 5740 0 0
T2 30322 0 0 0
T3 25328 0 0 0
T4 53690 0 0 0
T5 906870 250730 0 0
T6 2025024 840846 0 0
T7 0 23319 0 0
T8 0 3397989 0 0
T9 48100 13533 0 0
T10 240870 0 0 0
T11 91425 0 0 0
T12 61585 0 0 0
T13 72685 0 0 0
T14 0 389801 0 0
T16 0 7378 0 0
T27 0 28756 0 0
T28 0 20574 0 0
T50 92844 0 0 0
T92 0 12252 0 0
T93 0 14097 0 0
T99 0 15706 0 0
T100 0 95615 0 0
T108 157671 0 0 0

SizeMustBeBlockAligned_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 5735 5735 0 0
T1 5 5 0 0
T2 5 5 0 0
T3 5 5 0 0
T4 5 5 0 0
T5 5 5 0 0
T9 5 5 0 0
T10 5 5 0 0
T11 5 5 0 0
T12 5 5 0 0
T13 5 5 0 0

TlulGntKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 616680 609270 0 0
T2 75805 74340 0 0
T3 63320 62495 0 0
T4 53690 52390 0 0
T5 906870 900990 0 0
T9 48100 45475 0 0
T10 240870 240520 0 0
T11 91425 90245 0 0
T12 61585 60310 0 0
T13 72685 71165 0 0

TlulRdataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 616680 609270 0 0
T2 75805 74340 0 0
T3 63320 62495 0 0
T4 53690 52390 0 0
T5 906870 900990 0 0
T9 48100 45475 0 0
T10 240870 240520 0 0
T11 91425 90245 0 0
T12 61585 60310 0 0
T13 72685 71165 0 0

TlulReadOnReadLock_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 43774 0 0
T1 616680 21 0 0
T2 75805 4 0 0
T3 63320 0 0 0
T4 53690 0 0 0
T5 906870 73 0 0
T6 0 275 0 0
T7 0 24 0 0
T8 0 45 0 0
T9 48100 10 0 0
T10 240870 0 0 0
T11 91425 0 0 0
T12 61585 0 0 0
T13 72685 5 0 0
T15 0 15 0 0
T27 0 37 0 0
T28 0 8 0 0
T92 0 6 0 0
T99 0 3 0 0
T108 0 65 0 0

TlulRerrorKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 616680 609270 0 0
T2 75805 74340 0 0
T3 63320 62495 0 0
T4 53690 52390 0 0
T5 906870 900990 0 0
T9 48100 45475 0 0
T10 240870 240520 0 0
T11 91425 90245 0 0
T12 61585 60310 0 0
T13 72685 71165 0 0

TlulRvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 616680 609270 0 0
T2 75805 74340 0 0
T3 63320 62495 0 0
T4 53690 52390 0 0
T5 906870 900990 0 0
T9 48100 45475 0 0
T10 240870 240520 0 0
T11 91425 90245 0 0
T12 61585 60310 0 0
T13 72685 71165 0 0

WriteLockPropagation_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 11161829 0 0
T5 725496 57453 0 0
T6 2700032 0 0 0
T7 54232 0 0 0
T12 49268 0 0 0
T13 58148 0 0 0
T16 0 23392 0 0
T17 470842 0 0 0
T27 269384 8834 0 0
T28 214368 6614 0 0
T29 0 22312 0 0
T50 123792 0 0 0
T67 0 1115939 0 0
T68 58680 3268 0 0
T89 0 2857 0 0
T92 150068 2895 0 0
T94 0 16045 0 0
T95 84121 32160 0 0
T96 0 37562 0 0
T98 0 12588 0 0
T101 37673 643 0 0
T102 0 39068 0 0
T105 55118 1637 0 0
T108 210228 0 0 0
T125 0 38813 0 0
T127 0 91535 0 0
T128 0 15440 0 0
T142 21224 0 0 0
T177 0 4247 0 0
T178 0 15162 0 0
T179 38486 0 0 0
T180 13531 0 0 0
T181 39067 0 0 0
T182 10954 0 0 0

gen_digest_write_lock.DigestWriteLocksPartition_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 119510283 0 0
T2 30322 5132 0 0
T3 25328 0 0 0
T4 21476 0 0 0
T5 725496 525804 0 0
T6 1350016 0 0 0
T7 27116 0 0 0
T8 571747 0 0 0
T9 19240 0 0 0
T10 96348 0 0 0
T11 36570 0 0 0
T12 49268 0 0 0
T13 58148 0 0 0
T16 0 216115 0 0
T24 12196 0 0 0
T27 134692 165270 0 0
T28 160776 169738 0 0
T29 0 73303 0 0
T42 21541 0 0 0
T50 123792 0 0 0
T67 0 785660 0 0
T68 0 15413 0 0
T88 0 4139 0 0
T92 112551 103551 0 0
T93 32872 39468 0 0
T94 0 362806 0 0
T95 0 190032 0 0
T99 16682 0 0 0
T100 0 15168 0 0
T101 0 69501 0 0
T103 0 3629 0 0
T105 0 183630 0 0
T106 0 20314 0 0
T108 105114 0 0 0
T110 0 2414 0 0
T150 0 9280 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 616680 609270 0 0
T2 75805 74340 0 0
T3 63320 62495 0 0
T4 53690 52390 0 0
T5 906870 900990 0 0
T9 48100 45475 0 0
T10 240870 240520 0 0
T11 91425 90245 0 0
T12 61585 60310 0 0
T13 72685 71165 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%