Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.12	96.70	93.94		83.33	95.45	96.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.27	97.83	93.94	98.55	83.33	94.74	97.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	96.75	96.15	96.85		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	94.64	100.00		98.55		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	96.75	96.15	96.85		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	88	96.70
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	65	95.59
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	0	1
316	0	1
317	0	1
			==> MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	31	93.94
Logical	33	31	93.94
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T74,T76,T141

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T4,T10
1	Covered	T1,T93,T142

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T21,T22,T23

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b10001111000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T92,T28

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T92,T28

---

FSM Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T4
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T3,T9
ReadWaitSt	252	Covered	T1,T3,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T11,T12
IdleSt->ReadSt	236	Covered	T1,T3,T9
InitSt->ErrorSt	315	Covered	T115,T149,T161
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T103,T110,T144
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T9,T5,T6
ReadSt->ReadWaitSt	252	Covered	T1,T3,T4
ReadWaitSt->ErrorSt	276	Covered	T1,T150,T167
ReadWaitSt->IdleSt	270	Covered	T1,T3,T4
ResetSt->ErrorSt	315	Covered	T2,T4,T72
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	4	80.00	(Not included in score)
Transitions	11	8	72.73
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T9,T5,T6
CheckFailError	317	Not Covered
FsmStateError	289	Covered	T1,T2,T4
MacroEccCorrError	221	Covered	T1,T93,T142
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T6,T14,T179
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T9,T5,T6
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Not Covered
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T2,T4
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T1,T142,T74
MacroEccCorrError->NoError	235	Covered	T93,T68,T29
NoError->AccessError	256	Covered	T9,T5,T6
NoError->CheckFailError	317	Not Covered
NoError->FsmStateError	289	Covered	T1,T2,T4
NoError->MacroEccCorrError	221	Covered	T1,T93,T142

---

Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	42	95.45
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	1	33.33
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T92,T28
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T74,T76,T141
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T144,T192,T193
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T3,T9
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T3,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T28,T105,T17
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T9,T5,T6
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T1,T93,T142
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T3,T4,T10
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T1,T150,T167
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T2,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T2,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T4
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	443767462	442850715	0	0
DigestKnown_A	443767462	442850715	0	0
DigestOffsetMustBeRepresentable_A	1147	1147	0	0
EccErrorState_A	443767462	0	0	0
ErrorKnown_A	443767462	442850715	0	0
FsmStateKnown_A	443767462	442850715	0	0
InitDoneKnown_A	443767462	442850715	0	0
InitReadLocksPartition_A	443767462	86528879	0	0
InitWriteLocksPartition_A	443767462	86528879	0	0
OffsetMustBeBlockAligned_A	1147	1147	0	0
OtpAddrKnown_A	443767462	442850715	0	0
OtpCmdKnown_A	443767462	442850715	0	0
OtpErrorState_A	443767462	37	0	0
OtpReqKnown_A	443767462	442850715	0	0
OtpSizeKnown_A	443767462	442850715	0	0
OtpWdataKnown_A	443767462	442850715	0	0
ReadLockPropagation_A	443767462	188663188	0	0
SizeMustBeBlockAligned_A	1147	1147	0	0
TlulGntKnown_A	443767462	442850715	0	0
TlulRdataKnown_A	443767462	442850715	0	0
TlulReadOnReadLock_A	443767462	8864	0	0
TlulRerrorKnown_A	443767462	442850715	0	0
TlulRvalidKnown_A	443767462	442850715	0	0
WriteLockPropagation_A	443767462	2480946	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	443767462	28481624	0	0
u_state_regs_A	443767462	442850715	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443767462	442850715	0	0
T1	123336	121854	0	0
T2	15161	14868	0	0
T3	12664	12499	0	0
T4	10738	10478	0	0
T5	181374	180198	0	0
T9	9620	9095	0	0
T10	48174	48104	0	0
T11	18285	18049	0	0
T12	12317	12062	0	0
T13	14537	14233	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443767462	442850715	0	0
T1	123336	121854	0	0
T2	15161	14868	0	0
T3	12664	12499	0	0
T4	10738	10478	0	0
T5	181374	180198	0	0
T9	9620	9095	0	0
T10	48174	48104	0	0
T11	18285	18049	0	0
T12	12317	12062	0	0
T13	14537	14233	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147	1147	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443767462	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443767462	442850715	0	0
T1	123336	121854	0	0
T2	15161	14868	0	0
T3	12664	12499	0	0
T4	10738	10478	0	0
T5	181374	180198	0	0
T9	9620	9095	0	0
T10	48174	48104	0	0
T11	18285	18049	0	0
T12	12317	12062	0	0
T13	14537	14233	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443767462	442850715	0	0
T1	123336	121854	0	0
T2	15161	14868	0	0
T3	12664	12499	0	0
T4	10738	10478	0	0
T5	181374	180198	0	0
T9	9620	9095	0	0
T10	48174	48104	0	0
T11	18285	18049	0	0
T12	12317	12062	0	0
T13	14537	14233	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443767462	442850715	0	0
T1	123336	121854	0	0
T2	15161	14868	0	0
T3	12664	12499	0	0
T4	10738	10478	0	0
T5	181374	180198	0	0
T9	9620	9095	0	0
T10	48174	48104	0	0
T11	18285	18049	0	0
T12	12317	12062	0	0
T13	14537	14233	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443767462	86528879	0	0
T1	123336	33960	0	0
T2	15161	5061	0	0
T3	12664	344	0	0
T4	10738	4705	0	0
T5	181374	21135	0	0
T9	9620	238	0	0
T10	48174	97	0	0
T11	18285	4814	0	0
T12	12317	4761	0	0
T13	14537	7655	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443767462	86528879	0	0
T1	123336	33960	0	0
T2	15161	5061	0	0
T3	12664	344	0	0
T4	10738	4705	0	0
T5	181374	21135	0	0
T9	9620	238	0	0
T10	48174	97	0	0
T11	18285	4814	0	0
T12	12317	4761	0	0
T13	14537	7655	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147	1147	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443767462	442850715	0	0
T1	123336	121854	0	0
T2	15161	14868	0	0
T3	12664	12499	0	0
T4	10738	10478	0	0
T5	181374	180198	0	0
T9	9620	9095	0	0
T10	48174	48104	0	0
T11	18285	18049	0	0
T12	12317	12062	0	0
T13	14537	14233	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443767462	442850715	0	0
T1	123336	121854	0	0
T2	15161	14868	0	0
T3	12664	12499	0	0
T4	10738	10478	0	0
T5	181374	180198	0	0
T9	9620	9095	0	0
T10	48174	48104	0	0
T11	18285	18049	0	0
T12	12317	12062	0	0
T13	14537	14233	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443767462	37	0	0
T1	123336	1	0	0
T2	15161	0	0	0
T3	12664	0	0	0
T4	10738	0	0	0
T5	181374	0	0	0
T9	9620	0	0	0
T10	48174	0	0	0
T11	18285	0	0	0
T12	12317	0	0	0
T13	14537	0	0	0
T144	0	1	0	0
T150	0	1	0	0
T167	0	1	0	0
T192	0	1	0	0
T193	0	1	0	0
T194	0	1	0	0
T195	0	1	0	0
T196	0	1	0	0
T197	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443767462	442850715	0	0
T1	123336	121854	0	0
T2	15161	14868	0	0
T3	12664	12499	0	0
T4	10738	10478	0	0
T5	181374	180198	0	0
T9	9620	9095	0	0
T10	48174	48104	0	0
T11	18285	18049	0	0
T12	12317	12062	0	0
T13	14537	14233	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443767462	442850715	0	0
T1	123336	121854	0	0
T2	15161	14868	0	0
T3	12664	12499	0	0
T4	10738	10478	0	0
T5	181374	180198	0	0
T9	9620	9095	0	0
T10	48174	48104	0	0
T11	18285	18049	0	0
T12	12317	12062	0	0
T13	14537	14233	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443767462	442850715	0	0
T1	123336	121854	0	0
T2	15161	14868	0	0
T3	12664	12499	0	0
T4	10738	10478	0	0
T5	181374	180198	0	0
T9	9620	9095	0	0
T10	48174	48104	0	0
T11	18285	18049	0	0
T12	12317	12062	0	0
T13	14537	14233	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443767462	188663188	0	0
T4	10738	0	0	0
T5	181374	49169	0	0
T6	675008	164805	0	0
T8	0	483735	0	0
T9	9620	3075	0	0
T10	48174	0	0	0
T11	18285	0	0	0
T12	12317	0	0	0
T13	14537	0	0	0
T14	0	389801	0	0
T16	0	7378	0	0
T27	0	5190	0	0
T28	0	5223	0	0
T50	30948	0	0	0
T92	0	2473	0	0
T93	0	3618	0	0
T108	52557	0	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147	1147	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443767462	442850715	0	0
T1	123336	121854	0	0
T2	15161	14868	0	0
T3	12664	12499	0	0
T4	10738	10478	0	0
T5	181374	180198	0	0
T9	9620	9095	0	0
T10	48174	48104	0	0
T11	18285	18049	0	0
T12	12317	12062	0	0
T13	14537	14233	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443767462	442850715	0	0
T1	123336	121854	0	0
T2	15161	14868	0	0
T3	12664	12499	0	0
T4	10738	10478	0	0
T5	181374	180198	0	0
T9	9620	9095	0	0
T10	48174	48104	0	0
T11	18285	18049	0	0
T12	12317	12062	0	0
T13	14537	14233	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443767462	8864	0	0
T1	123336	1	0	0
T2	15161	1	0	0
T3	12664	0	0	0
T4	10738	0	0	0
T5	181374	12	0	0
T6	0	55	0	0
T7	0	10	0	0
T9	9620	2	0	0
T10	48174	0	0	0
T11	18285	0	0	0
T12	12317	0	0	0
T13	14537	0	0	0
T27	0	7	0	0
T28	0	3	0	0
T92	0	2	0	0
T108	0	10	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443767462	442850715	0	0
T1	123336	121854	0	0
T2	15161	14868	0	0
T3	12664	12499	0	0
T4	10738	10478	0	0
T5	181374	180198	0	0
T9	9620	9095	0	0
T10	48174	48104	0	0
T11	18285	18049	0	0
T12	12317	12062	0	0
T13	14537	14233	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443767462	442850715	0	0
T1	123336	121854	0	0
T2	15161	14868	0	0
T3	12664	12499	0	0
T4	10738	10478	0	0
T5	181374	180198	0	0
T9	9620	9095	0	0
T10	48174	48104	0	0
T11	18285	18049	0	0
T12	12317	12062	0	0
T13	14537	14233	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443767462	2480946	0	0
T5	181374	15404	0	0
T6	675008	0	0	0
T7	13558	0	0	0
T12	12317	0	0	0
T13	14537	0	0	0
T16	0	3390	0	0
T27	67346	0	0	0
T28	53592	2971	0	0
T29	0	2796	0	0
T50	30948	0	0	0
T67	0	458932	0	0
T89	0	772	0	0
T92	37517	0	0	0
T96	0	15267	0	0
T98	0	12588	0	0
T102	0	12849	0	0
T105	0	810	0	0
T108	52557	0	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443767462	28481624	0	0
T5	181374	121875	0	0
T6	675008	0	0	0
T7	13558	0	0	0
T12	12317	0	0	0
T13	14537	0	0	0
T16	0	50273	0	0
T27	67346	0	0	0
T28	53592	43106	0	0
T50	30948	0	0	0
T92	37517	29427	0	0
T93	0	17428	0	0
T94	0	90421	0	0
T95	0	63242	0	0
T100	0	3758	0	0
T101	0	29601	0	0
T105	0	48704	0	0
T108	52557	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443767462	442850715	0	0
T1	123336	121854	0	0
T2	15161	14868	0	0
T3	12664	12499	0	0
T4	10738	10478	0	0
T5	181374	180198	0	0
T9	9620	9095	0	0
T10	48174	48104	0	0
T11	18285	18049	0	0
T12	12317	12062	0	0
T13	14537	14233	0	0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T24,T25,T74

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T4,T10
1	Covered	T68,T29,T46

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T21,T22,T23

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T143,T147,T148
1	Covered	T143,T147,T148

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T10

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T3,T4,T10

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b11001010000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T92,T100,T105

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T92,T100,T105

---

FSM Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T4
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T3,T4
ReadWaitSt	252	Covered	T1,T3,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T11,T12
IdleSt->ReadSt	236	Covered	T1,T3,T4
InitSt->ErrorSt	315	Covered	T103,T110,T115
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T144,T198,T141
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T5,T6,T27
ReadSt->ReadWaitSt	252	Covered	T1,T3,T4
ReadWaitSt->ErrorSt	276	Covered	T1,T194,T188
ReadWaitSt->IdleSt	270	Covered	T3,T4,T10
ResetSt->ErrorSt	315	Covered	T2,T4,T72
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T5,T6,T27
CheckFailError	317	Covered	T143,T147,T148
FsmStateError	289	Covered	T1,T2,T4
MacroEccCorrError	221	Covered	T24,T68,T29
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T6,T14,T17
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T5,T6,T27
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T143,T147,T148
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T2,T4
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T24,T25,T74
MacroEccCorrError->NoError	235	Covered	T68,T29,T46
NoError->AccessError	256	Covered	T5,T6,T27
NoError->CheckFailError	317	Covered	T143,T147,T148
NoError->FsmStateError	289	Covered	T1,T2,T4
NoError->MacroEccCorrError	221	Covered	T24,T68,T29

---

Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T92,T100,T105
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T24,T25,T74
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T198,T141,T199
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T3,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T27,T92,T28
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T5,T6,T27
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T68,T29,T46
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T3,T4,T10
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T1,T194,T188
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T2,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T2,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T4
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T143,T147,T148
1	0	Covered	T143,T147,T148
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	443767462	442850715	0	0
DigestKnown_A	443767462	442850715	0	0
DigestOffsetMustBeRepresentable_A	1147	1147	0	0
EccErrorState_A	443767462	7379	0	0
ErrorKnown_A	443767462	442850715	0	0
FsmStateKnown_A	443767462	442850715	0	0
InitDoneKnown_A	443767462	442850715	0	0
InitReadLocksPartition_A	443767462	86718708	0	0
InitWriteLocksPartition_A	443767462	86718708	0	0
OffsetMustBeBlockAligned_A	1147	1147	0	0
OtpAddrKnown_A	443767462	442850715	0	0
OtpCmdKnown_A	443767462	442850715	0	0
OtpErrorState_A	443767462	36	0	0
OtpReqKnown_A	443767462	442850715	0	0
OtpSizeKnown_A	443767462	442850715	0	0
OtpWdataKnown_A	443767462	442850715	0	0
ReadLockPropagation_A	443767462	191335312	0	0
SizeMustBeBlockAligned_A	1147	1147	0	0
TlulGntKnown_A	443767462	442850715	0	0
TlulRdataKnown_A	443767462	442850715	0	0
TlulReadOnReadLock_A	443767462	8640	0	0
TlulRerrorKnown_A	443767462	442850715	0	0
TlulRvalidKnown_A	443767462	442850715	0	0
WriteLockPropagation_A	443767462	966742	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	443767462	10336000	0	0
u_state_regs_A	443767462	442850715	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443767462	442850715	0	0
T1	123336	121854	0	0
T2	15161	14868	0	0
T3	12664	12499	0	0
T4	10738	10478	0	0
T5	181374	180198	0	0
T9	9620	9095	0	0
T10	48174	48104	0	0
T11	18285	18049	0	0
T12	12317	12062	0	0
T13	14537	14233	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443767462	442850715	0	0
T1	123336	121854	0	0
T2	15161	14868	0	0
T3	12664	12499	0	0
T4	10738	10478	0	0
T5	181374	180198	0	0
T9	9620	9095	0	0
T10	48174	48104	0	0
T11	18285	18049	0	0
T12	12317	12062	0	0
T13	14537	14233	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147	1147	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443767462	7379	0	0
T57	13028	0	0	0
T143	9254	2030	0	0
T147	0	2507	0	0
T148	0	2842	0	0
T183	15446	0	0	0
T200	25971	0	0	0
T201	77964	0	0	0
T202	230938	0	0	0
T203	15612	0	0	0
T204	6201	0	0	0
T205	118592	0	0	0
T206	154776	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443767462	442850715	0	0
T1	123336	121854	0	0
T2	15161	14868	0	0
T3	12664	12499	0	0
T4	10738	10478	0	0
T5	181374	180198	0	0
T9	9620	9095	0	0
T10	48174	48104	0	0
T11	18285	18049	0	0
T12	12317	12062	0	0
T13	14537	14233	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443767462	442850715	0	0
T1	123336	121854	0	0
T2	15161	14868	0	0
T3	12664	12499	0	0
T4	10738	10478	0	0
T5	181374	180198	0	0
T9	9620	9095	0	0
T10	48174	48104	0	0
T11	18285	18049	0	0
T12	12317	12062	0	0
T13	14537	14233	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443767462	442850715	0	0
T1	123336	121854	0	0
T2	15161	14868	0	0
T3	12664	12499	0	0
T4	10738	10478	0	0
T5	181374	180198	0	0
T9	9620	9095	0	0
T10	48174	48104	0	0
T11	18285	18049	0	0
T12	12317	12062	0	0
T13	14537	14233	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443767462	86718708	0	0
T1	123336	34249	0	0
T2	15161	5095	0	0
T3	12664	395	0	0
T4	10738	4739	0	0
T5	181374	21356	0	0
T9	9620	272	0	0
T10	48174	114	0	0
T11	18285	4865	0	0
T12	12317	4812	0	0
T13	14537	7706	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443767462	86718708	0	0
T1	123336	34249	0	0
T2	15161	5095	0	0
T3	12664	395	0	0
T4	10738	4739	0	0
T5	181374	21356	0	0
T9	9620	272	0	0
T10	48174	114	0	0
T11	18285	4865	0	0
T12	12317	4812	0	0
T13	14537	7706	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147	1147	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443767462	442850715	0	0
T1	123336	121854	0	0
T2	15161	14868	0	0
T3	12664	12499	0	0
T4	10738	10478	0	0
T5	181374	180198	0	0
T9	9620	9095	0	0
T10	48174	48104	0	0
T11	18285	18049	0	0
T12	12317	12062	0	0
T13	14537	14233	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443767462	442850715	0	0
T1	123336	121854	0	0
T2	15161	14868	0	0
T3	12664	12499	0	0
T4	10738	10478	0	0
T5	181374	180198	0	0
T9	9620	9095	0	0
T10	48174	48104	0	0
T11	18285	18049	0	0
T12	12317	12062	0	0
T13	14537	14233	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443767462	36	0	0
T1	123336	1	0	0
T2	15161	0	0	0
T3	12664	0	0	0
T4	10738	0	0	0
T5	181374	0	0	0
T9	9620	0	0	0
T10	48174	0	0	0
T11	18285	0	0	0
T12	12317	0	0	0
T13	14537	0	0	0
T141	0	1	0	0
T188	0	1	0	0
T194	0	1	0	0
T198	0	1	0	0
T199	0	1	0	0
T207	0	1	0	0
T208	0	1	0	0
T209	0	1	0	0
T210	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443767462	442850715	0	0
T1	123336	121854	0	0
T2	15161	14868	0	0
T3	12664	12499	0	0
T4	10738	10478	0	0
T5	181374	180198	0	0
T9	9620	9095	0	0
T10	48174	48104	0	0
T11	18285	18049	0	0
T12	12317	12062	0	0
T13	14537	14233	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443767462	442850715	0	0
T1	123336	121854	0	0
T2	15161	14868	0	0
T3	12664	12499	0	0
T4	10738	10478	0	0
T5	181374	180198	0	0
T9	9620	9095	0	0
T10	48174	48104	0	0
T11	18285	18049	0	0
T12	12317	12062	0	0
T13	14537	14233	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443767462	442850715	0	0
T1	123336	121854	0	0
T2	15161	14868	0	0
T3	12664	12499	0	0
T4	10738	10478	0	0
T5	181374	180198	0	0
T9	9620	9095	0	0
T10	48174	48104	0	0
T11	18285	18049	0	0
T12	12317	12062	0	0
T13	14537	14233	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443767462	191335312	0	0
T1	123336	2863	0	0
T2	15161	0	0	0
T3	12664	0	0	0
T4	10738	0	0	0
T5	181374	49513	0	0
T6	0	172568	0	0
T8	0	483749	0	0
T9	9620	3073	0	0
T10	48174	0	0	0
T11	18285	0	0	0
T12	12317	0	0	0
T13	14537	0	0	0
T27	0	7138	0	0
T28	0	1239	0	0
T92	0	1821	0	0
T93	0	2834	0	0
T100	0	47853	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147	1147	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443767462	442850715	0	0
T1	123336	121854	0	0
T2	15161	14868	0	0
T3	12664	12499	0	0
T4	10738	10478	0	0
T5	181374	180198	0	0
T9	9620	9095	0	0
T10	48174	48104	0	0
T11	18285	18049	0	0
T12	12317	12062	0	0
T13	14537	14233	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443767462	442850715	0	0
T1	123336	121854	0	0
T2	15161	14868	0	0
T3	12664	12499	0	0
T4	10738	10478	0	0
T5	181374	180198	0	0
T9	9620	9095	0	0
T10	48174	48104	0	0
T11	18285	18049	0	0
T12	12317	12062	0	0
T13	14537	14233	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443767462	8640	0	0
T1	123336	3	0	0
T2	15161	1	0	0
T3	12664	0	0	0
T4	10738	0	0	0
T5	181374	20	0	0
T6	0	51	0	0
T7	0	3	0	0
T8	0	45	0	0
T9	9620	0	0	0
T10	48174	0	0	0
T11	18285	0	0	0
T12	12317	0	0	0
T13	14537	0	0	0
T15	0	15	0	0
T27	0	7	0	0
T99	0	3	0	0
T108	0	10	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443767462	442850715	0	0
T1	123336	121854	0	0
T2	15161	14868	0	0
T3	12664	12499	0	0
T4	10738	10478	0	0
T5	181374	180198	0	0
T9	9620	9095	0	0
T10	48174	48104	0	0
T11	18285	18049	0	0
T12	12317	12062	0	0
T13	14537	14233	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443767462	442850715	0	0
T1	123336	121854	0	0
T2	15161	14868	0	0
T3	12664	12499	0	0
T4	10738	10478	0	0
T5	181374	180198	0	0
T9	9620	9095	0	0
T10	48174	48104	0	0
T11	18285	18049	0	0
T12	12317	12062	0	0
T13	14537	14233	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443767462	966742	0	0
T17	470842	0	0	0
T29	0	10886	0	0
T67	0	128416	0	0
T68	58680	3268	0	0
T95	84121	0	0	0
T101	37673	0	0	0
T105	55118	827	0	0
T125	0	10626	0	0
T127	0	9030	0	0
T128	0	15440	0	0
T142	21224	0	0	0
T177	0	4247	0	0
T178	0	15162	0	0
T179	38486	0	0	0
T180	13531	0	0	0
T181	39067	0	0	0
T182	10954	0	0	0
T211	0	4705	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443767462	10336000	0	0
T8	571747	0	0	0
T15	208961	0	0	0
T24	12196	0	0	0
T28	53592	0	0	0
T29	0	73303	0	0
T31	14828	0	0	0
T42	21541	0	0	0
T67	0	785660	0	0
T68	0	15413	0	0
T88	0	4139	0	0
T92	37517	29325	0	0
T93	32872	0	0	0
T99	16682	0	0	0
T100	56999	3724	0	0
T101	0	29431	0	0
T105	0	48449	0	0
T106	0	20314	0	0
T150	0	9280	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443767462	442850715	0	0
T1	123336	121854	0	0
T2	15161	14868	0	0
T3	12664	12499	0	0
T4	10738	10478	0	0
T5	181374	180198	0	0
T9	9620	9095	0	0
T10	48174	48104	0	0
T11	18285	18049	0	0
T12	12317	12062	0	0
T13	14537	14233	0	0