Assertions
dashboard | hierarchy | modlist | groups | tests | asserts
Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total1451020
Category 01451020

Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total1451020
Severity 01451020

Summary for Assertions
NUMBERPERCENT
Total Number1451100.00
Uncovered543.72
Success139796.28
Failure00.00
Incomplete110.76
Without Attempts50.34

Summary for Cover Sequences
NUMBERPERCENT
Total Number20100.00
Uncovered00.00
All Matches20100.00
First Matches20100.00
Go previous page
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETE
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.RDataOutKnown_A 0043145130143058706300
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.WidthMustBe64bit_A 001154115400
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre.OutputsKnown_A 0043145130143058706300
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre.OutputsKnown_A 0043145130143058706300
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_state_regs.AssertConnected_A 001154115400
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_state_regs_A 0043145130143058706300
tb.dut.gen_partitions[5].gen_buffered.FpvSecCmCntPartBufCheck_A 004314513015000
tb.dut.gen_partitions[5].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A 004314513015000
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.AccessKnown_A 0043145130143058706300
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.BypassEnable1_A 0043145130143058706300
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.CnstyChkAckKnown_A 0043145130143058706300
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.DataKnown_A 0043145130143058706300
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.DigestKnown_A 0043145130143058706300
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.DigestOffsetMustBeRepresentable_A 001154115400
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.ErrorKnown_A 0043145130143058706300
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.InitDoneKnown_A 0043145130143058706300
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.InitReadLocksPartition_A 0043145130110327655900
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.InitWriteLocksPartition_A 0043145130110327655900
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.IntegChkAckKnown_A 0043145130143058706300
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.OffsetMustBeBlockAligned_A 001154115400
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.OtpAddrKnown_A 0043145130143058706300
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.OtpCmdKnown_A 0043145130143058706300
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.OtpReqKnown_A 0043145130143058706300
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.OtpSizeKnown_A 0043145130143058706300
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.OtpWdataKnown_A 0043145130143058706300
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.ReadLockImpliesDigest_A 0043145130143058706300
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.ScrmblCmdKnown_A 0043145130143058706300
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.ScrmblDataKnown_A 0043117597543031173700
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.ScrmblModeKnown_A 0043145130143058706300
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.ScrmblMtxReqKnown_A 0043145130143058706300
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.ScrmblSelKnown_A 0043145130143058706300
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.ScrmblValidKnown_A 0043145130143058706300
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.SizeMustBeBlockAligned_A 001154115400
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.WriteLockPropagation_A 00431451301283744900
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.gen_digest_write_lock.DigestWriteLocksPartition_A 004314513012948348700
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock.OutputsKnown_A 0043145130143058706300
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.DataKnown_A 0043145130143058706300
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.DataOutKnown_A 0043145130143058706300
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.EccErrKnown_A 0043145130143058706300
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.EccKnown_A 0043145130143058706300
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.RDataOutKnown_A 0043145130143058706300
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.WidthMustBe64bit_A 001154115400
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre.OutputsKnown_A 0043145130143058706300
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre.OutputsKnown_A 0043145130143058706300
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_state_regs.AssertConnected_A 001154115400
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_state_regs_A 0043145130143058706300
tb.dut.gen_partitions[6].gen_buffered.FpvSecCmCntPartBufCheck_A 004314513015000
tb.dut.gen_partitions[6].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A 004314513015000
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.AccessKnown_A 0043145130143058706300
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.BypassEnable1_A 0043145130143058706300
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.CnstyChkAckKnown_A 0043145130143058706300
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.DataKnown_A 0043145130143058706300
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.DigestKnown_A 0043145130143058706300
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.DigestOffsetMustBeRepresentable_A 001154115400
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.ErrorKnown_A 0043145130143058706300
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.InitDoneKnown_A 0043145130143058706300
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.InitReadLocksPartition_A 004314513019575446100
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.InitWriteLocksPartition_A 004314513019575446100
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.IntegChkAckKnown_A 0043145130143058706300
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.OffsetMustBeBlockAligned_A 001154115400
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.OtpAddrKnown_A 0043145130143058706300
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.OtpCmdKnown_A 0043145130143058706300
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.OtpReqKnown_A 0043145130143058706300
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.OtpSizeKnown_A 0043145130143058706300
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.OtpWdataKnown_A 0043145130143058706300
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.ReadLockImpliesDigest_A 0043145130143058706300
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.ScrmblCmdKnown_A 0043145130143058706300
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.ScrmblDataKnown_A 0043117597543031173700
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.ScrmblModeKnown_A 0043145130143058706300
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.ScrmblMtxReqKnown_A 0043145130143058706300
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.ScrmblSelKnown_A 0043145130143058706300
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.ScrmblValidKnown_A 0043145130143058706300
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.SizeMustBeBlockAligned_A 001154115400
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.WriteLockPropagation_A 00431451301288075500
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.gen_digest_write_lock.DigestWriteLocksPartition_A 004314513013119085200
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock.OutputsKnown_A 0043145130143058706300
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.DataKnown_A 0043145130143058706300
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.DataOutKnown_A 0043145130143058706300
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.EccErrKnown_A 0043145130143058706300
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.EccKnown_A 0043145130143058706300
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.RDataOutKnown_A 0043145130143058706300
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.WidthMustBe64bit_A 001154115400
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre.OutputsKnown_A 0043145130143058706300
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre.OutputsKnown_A 0043145130143058706300
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_state_regs.AssertConnected_A 001154115400
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_state_regs_A 0043145130143058706300
tb.dut.gen_partitions[7].gen_buffered.FpvSecCmCntPartBufCheck_A 004314513015000
tb.dut.gen_partitions[7].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A 004314513015000
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.AccessKnown_A 0043145130143058706300
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.BypassEnable0_A 0043145130143058706300
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.BypassEnable1_A 0043145130143058706300
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.CnstyChkAckKnown_A 0043145130143058706300
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.DataKnown_A 0043145130143058706300
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.DigestKnown_A 0043145130143058706300
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.DigestOffsetMustBeRepresentable_A 001154115400
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.ErrorKnown_A 0043145130143058706300
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.InitDoneKnown_A 0043145130143058706300
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.InitReadLocksPartition_A 0043145130110109115700
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.InitWriteLocksPartition_A 0043145130110109115700
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.IntegChkAckKnown_A 0043145130143058706300
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.OffsetMustBeBlockAligned_A 001154115400
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.OtpAddrKnown_A 0043145130143058706300
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.OtpCmdKnown_A 0043145130143058706300
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.OtpReqKnown_A 0043145130143058706300
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.OtpSizeKnown_A 0043145130143058706300
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.OtpWdataKnown_A 0043145130143058706300
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.ReadLockImpliesDigest_A 0043145130143058706300
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.ReadLockPropagation_A 00431451301269927700
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.ScrambledImpliesDigest_A 0043145130143058706300
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.ScrmblCmdKnown_A 0043145130143058706300
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.ScrmblDataKnown_A 0043145130143058706300
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.ScrmblModeKnown_A 0043145130143058706300
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.ScrmblMtxReqKnown_A 0043145130143058706300
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.ScrmblSelKnown_A 0043145130143058706300
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.ScrmblValidKnown_A 0043145130143058706300
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.SizeMustBeBlockAligned_A 001154115400
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.WriteLockImpliesDigest_A 0043145130143058706300
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.WriteLockPropagation_A 00431451301214963300
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_read_lock.DigestReadLocksPartition_A 004314513012950203000
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock.OutputsKnown_A 0043145130143058706300
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_write_lock.DigestWriteLocksPartition_A 004314513012950203000
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock.OutputsKnown_A 0043145130143058706300
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.DataKnown_A 0043145130143058706300
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.DataOutKnown_A 0043145130143058706300
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.EccErrKnown_A 0043145130143058706300
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.EccKnown_A 0043145130143058706300
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.RDataOutKnown_A 0043145130143058706300
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.WidthMustBe64bit_A 001154115400
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre.OutputsKnown_A 0043145130143058706300
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre.OutputsKnown_A 0043145130143058706300
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_state_regs.AssertConnected_A 001154115400
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_state_regs_A 0043145130143058706300
tb.dut.gen_partitions[8].gen_buffered.FpvSecCmCntPartBufCheck_A 004314513015000
tb.dut.gen_partitions[8].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A 004314513015000
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.AccessKnown_A 0043145130143058706300
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.BypassEnable0_A 0043145130143058706300
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.BypassEnable1_A 0043145130143058706300
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.CnstyChkAckKnown_A 0043145130143058706300
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.DataKnown_A 0043145130143058706300
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.DigestKnown_A 0043145130143058706300
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.DigestOffsetMustBeRepresentable_A 001154115400
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.ErrorKnown_A 0043145130143058706300
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.InitDoneKnown_A 0043145130143058706300
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.InitReadLocksPartition_A 0043145130111087347900
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.InitWriteLocksPartition_A 0043145130111087347900
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.IntegChkAckKnown_A 0043145130143058706300
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.OffsetMustBeBlockAligned_A 001154115400
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.OtpAddrKnown_A 0043145130143058706300
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.OtpCmdKnown_A 0043145130143058706300
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.OtpReqKnown_A 0043145130143058706300
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.OtpSizeKnown_A 0043145130143058706300
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.OtpWdataKnown_A 0043145130143058706300
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.ReadLockImpliesDigest_A 0043145130143058706300
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.ReadLockPropagation_A 00431451301243695600
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.ScrambledImpliesDigest_A 0043145130143058706300
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.ScrmblCmdKnown_A 0043145130143058706300
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.ScrmblDataKnown_A 0043145130143058706300
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.ScrmblModeKnown_A 0043145130143058706300
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.ScrmblMtxReqKnown_A 0043145130143058706300
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.ScrmblSelKnown_A 0043145130143058706300
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.ScrmblValidKnown_A 0043145130143058706300
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.SizeMustBeBlockAligned_A 001154115400
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.WriteLockImpliesDigest_A 0043145130143058706300
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.WriteLockPropagation_A 00431451301243689300
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_read_lock.DigestReadLocksPartition_A 004314513012727068800
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock.OutputsKnown_A 0043145130143058706300
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_write_lock.DigestWriteLocksPartition_A 004314513012727068800
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock.OutputsKnown_A 0043145130143058706300
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.DataKnown_A 0043145130143058706300
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.DataOutKnown_A 0043145130143058706300
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.EccErrKnown_A 0043145130143058706300
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.EccKnown_A 0043145130143058706300
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.RDataOutKnown_A 0043145130143058706300
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.WidthMustBe64bit_A 001154115400
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre.OutputsKnown_A 0043145130143058706300
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre.OutputsKnown_A 0043145130143058706300
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_state_regs.AssertConnected_A 001154115400
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_state_regs_A 0043145130143058706300
tb.dut.gen_partitions[9].gen_buffered.FpvSecCmCntPartBufCheck_A 004314513015000
tb.dut.gen_partitions[9].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A 004314513015000
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.AccessKnown_A 0043145130143058706300
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.BypassEnable0_A 0043145130143058706300
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.BypassEnable1_A 0043145130143058706300
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.CnstyChkAckKnown_A 0043145130143058706300
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.DataKnown_A 0043145130143058706300
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.DigestKnown_A 0043145130143058706300
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.DigestOffsetMustBeRepresentable_A 001154115400
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.ErrorKnown_A 0043145130143058706300
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.InitDoneKnown_A 0043145130143058706300
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.InitReadLocksPartition_A 0043145130111522281200
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.InitWriteLocksPartition_A 0043145130111522281200
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.IntegChkAckKnown_A 0043145130143058706300
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.OffsetMustBeBlockAligned_A 001154115400
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.OtpAddrKnown_A 0043145130143058706300
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.OtpCmdKnown_A 0043145130143058706300
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.OtpReqKnown_A 0043145130143058706300
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.OtpSizeKnown_A 0043145130143058706300
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.OtpWdataKnown_A 0043145130143058706300
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.ReadLockImpliesDigest_A 0043145130143058706300
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.ReadLockPropagation_A 0043145130124281885800
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.ScrambledImpliesDigest_A 0043145130143058706300
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.ScrmblCmdKnown_A 0043145130143058706300
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.ScrmblDataKnown_A 0043145130143058706300
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.ScrmblModeKnown_A 0043145130143058706300
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.ScrmblMtxReqKnown_A 0043145130143058706300
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.ScrmblSelKnown_A 0043145130143058706300
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.ScrmblValidKnown_A 0043145130143058706300
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.SizeMustBeBlockAligned_A 001154115400
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.WriteLockImpliesDigest_A 0043145130143058706300
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.WriteLockPropagation_A 0043145130124276049400
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_read_lock.DigestReadLocksPartition_A 004314513011906526700
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock.OutputsKnown_A 0043145130143058706300
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_write_lock.DigestWriteLocksPartition_A 004314513011906526700
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock.OutputsKnown_A 0043145130143058706300
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.DataKnown_A 0043145130143058706300
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.DataOutKnown_A 0043145130143058706300
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.EccErrKnown_A 0043145130143058706300
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.EccKnown_A 0043145130143058706300
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.RDataOutKnown_A 0043145130143058706300
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.WidthMustBe64bit_A 001154115400
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre.OutputsKnown_A 0043145130143058706300
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre.OutputsKnown_A 0043145130143058706300
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_state_regs.AssertConnected_A 001154115400
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_state_regs_A 0043145130143058706300
tb.dut.gen_reg_we_assert_generic.FpvSecCmPrimFsmCheck_A 004314513015000
tb.dut.gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A 004314513015000
tb.dut.otp_ctrl_core_csr_assert.TlulOOBAddrErr_A 00434250508705741500
tb.dut.otp_ctrl_core_csr_assert.check_regwen_rd_A 00434250508354300
tb.dut.otp_ctrl_core_csr_assert.check_timeout_rd_A 00434250508347100
tb.dut.otp_ctrl_core_csr_assert.check_trigger_regwen_rd_A 00434250508360500
tb.dut.otp_ctrl_core_csr_assert.consistency_check_period_rd_A 00434250508362200
tb.dut.otp_ctrl_core_csr_assert.creator_sw_cfg_read_lock_rd_A 00434250508333800
tb.dut.otp_ctrl_core_csr_assert.direct_access_address_rd_A 00434250508291600
tb.dut.otp_ctrl_core_csr_assert.direct_access_wdata_0_rd_A 00434250508207200
tb.dut.otp_ctrl_core_csr_assert.direct_access_wdata_1_rd_A 00434250508214700
tb.dut.otp_ctrl_core_csr_assert.integrity_check_period_rd_A 00434250508353000
tb.dut.otp_ctrl_core_csr_assert.intr_enable_rd_A 00434250508460400
tb.dut.otp_ctrl_core_csr_assert.owner_sw_cfg_read_lock_rd_A 00434250508320200
tb.dut.otp_ctrl_core_csr_assert.rot_creator_auth_codesign_read_lock_rd_A 00434250508358300
tb.dut.otp_ctrl_core_csr_assert.rot_creator_auth_state_read_lock_rd_A 00434250508294800
tb.dut.otp_ctrl_core_csr_assert.vendor_test_read_lock_rd_A 00434250508298000
tb.dut.prim_tlul_assert_device.aKnown_A 004342505082315029400
tb.dut.prim_tlul_assert_device.aKnown_AKnownEnable 0043425050843333508100
tb.dut.prim_tlul_assert_device.aReadyKnown_A 0043425050843333508100
tb.dut.prim_tlul_assert_device.dKnown_A 004342505082993897500
tb.dut.prim_tlul_assert_device.dKnown_AKnownEnable 0043425050843333508100
tb.dut.prim_tlul_assert_device.dReadyKnown_A 0043425050843333508100
tb.dut.prim_tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A 001329132900
tb.dut.prim_tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A 001329132900
Go next page
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%