Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.86	97.40	96.15	97.12		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	476073319	8682771	0	0
check_regwen_rd_A	476073319	4391	0	0
check_timeout_rd_A	476073319	3231	0	0
check_trigger_regwen_rd_A	476073319	4721	0	0
consistency_check_period_rd_A	476073319	4579	0	0
creator_sw_cfg_read_lock_rd_A	476073319	3179	0	0
direct_access_address_rd_A	476073319	2330	0	0
direct_access_wdata_0_rd_A	476073319	1520	0	0
direct_access_wdata_1_rd_A	476073319	1892	0	0
integrity_check_period_rd_A	476073319	4125	0	0
intr_enable_rd_A	476073319	5439	0	0
owner_sw_cfg_read_lock_rd_A	476073319	2971	0	0
rot_creator_auth_codesign_read_lock_rd_A	476073319	3274	0	0
rot_creator_auth_state_read_lock_rd_A	476073319	2991	0	0
vendor_test_read_lock_rd_A	476073319	3030	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476073319	8682771	0	0
T8	104294	177330	0	0
T9	532014	94182	0	0
T13	808442	120543	0	0
T15	9461	0	0	0
T16	0	89525	0	0
T17	0	56668	0	0
T18	0	243092	0	0
T36	62070	0	0	0
T110	20566	0	0	0
T111	36286	0	0	0
T112	63940	0	0	0
T115	7702	0	0	0
T123	21579	0	0	0
T144	0	62185	0	0
T177	0	70114	0	0
T252	0	99653	0	0
T274	0	184063	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476073319	4391	0	0
T9	532014	102	0	0
T13	808442	0	0	0
T44	58924	0	0	0
T55	12701	0	0	0
T116	21348	0	0	0
T117	104247	0	0	0
T118	28229	0	0	0
T119	30460	0	0	0
T123	21579	0	0	0
T145	0	74	0	0
T210	8589	0	0	0
T252	0	59	0	0
T338	0	127	0	0
T339	0	124	0	0
T340	0	61	0	0
T341	0	33	0	0
T342	0	147	0	0
T343	0	49	0	0
T344	0	40	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476073319	3231	0	0
T9	532014	157	0	0
T13	808442	0	0	0
T44	58924	0	0	0
T55	12701	0	0	0
T116	21348	0	0	0
T117	104247	0	0	0
T118	28229	0	0	0
T119	30460	0	0	0
T123	21579	0	0	0
T145	0	69	0	0
T210	8589	0	0	0
T252	0	83	0	0
T338	0	53	0	0
T339	0	65	0	0
T340	0	49	0	0
T341	0	42	0	0
T342	0	146	0	0
T343	0	88	0	0
T344	0	49	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476073319	4721	0	0
T9	532014	105	0	0
T13	808442	0	0	0
T44	58924	0	0	0
T55	12701	0	0	0
T116	21348	0	0	0
T117	104247	0	0	0
T118	28229	0	0	0
T119	30460	0	0	0
T123	21579	0	0	0
T145	0	76	0	0
T210	8589	0	0	0
T252	0	57	0	0
T338	0	74	0	0
T339	0	85	0	0
T340	0	26	0	0
T341	0	33	0	0
T342	0	145	0	0
T343	0	42	0	0
T344	0	57	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476073319	4579	0	0
T9	532014	138	0	0
T13	808442	0	0	0
T44	58924	0	0	0
T55	12701	0	0	0
T116	21348	0	0	0
T117	104247	0	0	0
T118	28229	0	0	0
T119	30460	0	0	0
T123	21579	0	0	0
T145	0	71	0	0
T210	8589	0	0	0
T252	0	88	0	0
T338	0	92	0	0
T339	0	86	0	0
T340	0	44	0	0
T341	0	43	0	0
T342	0	185	0	0
T343	0	52	0	0
T344	0	54	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476073319	3179	0	0
T9	532014	132	0	0
T13	808442	0	0	0
T44	58924	0	0	0
T55	12701	0	0	0
T116	21348	0	0	0
T117	104247	0	0	0
T118	28229	0	0	0
T119	30460	0	0	0
T123	21579	0	0	0
T145	0	89	0	0
T210	8589	0	0	0
T252	0	108	0	0
T338	0	87	0	0
T339	0	71	0	0
T340	0	57	0	0
T341	0	28	0	0
T342	0	179	0	0
T343	0	45	0	0
T344	0	40	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476073319	2330	0	0
T9	532014	162	0	0
T13	808442	0	0	0
T44	58924	0	0	0
T55	12701	0	0	0
T116	21348	0	0	0
T117	104247	0	0	0
T118	28229	0	0	0
T119	30460	0	0	0
T123	21579	0	0	0
T145	0	68	0	0
T210	8589	0	0	0
T252	0	105	0	0
T338	0	74	0	0
T339	0	83	0	0
T340	0	42	0	0
T341	0	38	0	0
T342	0	211	0	0
T343	0	56	0	0
T344	0	72	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476073319	1520	0	0
T9	532014	95	0	0
T13	808442	0	0	0
T44	58924	0	0	0
T55	12701	0	0	0
T116	21348	0	0	0
T117	104247	0	0	0
T118	28229	0	0	0
T119	30460	0	0	0
T123	21579	0	0	0
T145	0	77	0	0
T210	8589	0	0	0
T252	0	76	0	0
T338	0	72	0	0
T339	0	60	0	0
T340	0	20	0	0
T341	0	8	0	0
T342	0	125	0	0
T343	0	43	0	0
T344	0	24	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476073319	1892	0	0
T9	532014	72	0	0
T13	808442	0	0	0
T44	58924	0	0	0
T55	12701	0	0	0
T116	21348	0	0	0
T117	104247	0	0	0
T118	28229	0	0	0
T119	30460	0	0	0
T123	21579	0	0	0
T145	0	107	0	0
T210	8589	0	0	0
T252	0	52	0	0
T338	0	52	0	0
T339	0	87	0	0
T340	0	41	0	0
T341	0	19	0	0
T342	0	143	0	0
T343	0	44	0	0
T344	0	34	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476073319	4125	0	0
T9	532014	88	0	0
T13	808442	0	0	0
T44	58924	0	0	0
T55	12701	0	0	0
T116	21348	0	0	0
T117	104247	0	0	0
T118	28229	0	0	0
T119	30460	0	0	0
T123	21579	0	0	0
T145	0	66	0	0
T210	8589	0	0	0
T252	0	52	0	0
T338	0	85	0	0
T339	0	67	0	0
T340	0	49	0	0
T341	0	21	0	0
T342	0	147	0	0
T343	0	67	0	0
T344	0	68	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476073319	5439	0	0
T9	532014	126	0	0
T13	808442	0	0	0
T44	58924	0	0	0
T55	12701	0	0	0
T99	0	43	0	0
T116	21348	0	0	0
T117	104247	0	0	0
T118	28229	0	0	0
T119	30460	0	0	0
T123	21579	0	0	0
T145	0	74	0	0
T210	8589	0	0	0
T250	0	13	0	0
T252	0	101	0	0
T338	0	42	0	0
T339	0	78	0	0
T340	0	55	0	0
T341	0	33	0	0
T342	0	219	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476073319	2971	0	0
T9	532014	119	0	0
T13	808442	0	0	0
T44	58924	0	0	0
T55	12701	0	0	0
T116	21348	0	0	0
T117	104247	0	0	0
T118	28229	0	0	0
T119	30460	0	0	0
T123	21579	0	0	0
T145	0	58	0	0
T210	8589	0	0	0
T252	0	75	0	0
T338	0	66	0	0
T339	0	65	0	0
T340	0	53	0	0
T341	0	16	0	0
T342	0	178	0	0
T343	0	83	0	0
T344	0	45	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476073319	3274	0	0
T9	532014	133	0	0
T13	808442	0	0	0
T44	58924	0	0	0
T55	12701	0	0	0
T116	21348	0	0	0
T117	104247	0	0	0
T118	28229	0	0	0
T119	30460	0	0	0
T123	21579	0	0	0
T145	0	72	0	0
T210	8589	0	0	0
T252	0	76	0	0
T338	0	53	0	0
T339	0	94	0	0
T340	0	48	0	0
T341	0	31	0	0
T342	0	211	0	0
T343	0	71	0	0
T344	0	54	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476073319	2991	0	0
T9	532014	96	0	0
T13	808442	0	0	0
T44	58924	0	0	0
T55	12701	0	0	0
T116	21348	0	0	0
T117	104247	0	0	0
T118	28229	0	0	0
T119	30460	0	0	0
T123	21579	0	0	0
T145	0	73	0	0
T210	8589	0	0	0
T252	0	78	0	0
T338	0	63	0	0
T339	0	76	0	0
T340	0	71	0	0
T341	0	32	0	0
T342	0	119	0	0
T343	0	53	0	0
T344	0	34	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476073319	3030	0	0
T9	532014	99	0	0
T13	808442	0	0	0
T44	58924	0	0	0
T55	12701	0	0	0
T116	21348	0	0	0
T117	104247	0	0	0
T118	28229	0	0	0
T119	30460	0	0	0
T123	21579	0	0	0
T145	0	65	0	0
T210	8589	0	0	0
T252	0	77	0	0
T338	0	52	0	0
T339	0	71	0	0
T340	0	50	0	0
T341	0	31	0	0
T342	0	176	0	0
T343	0	72	0	0
T344	0	39	0	0