Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : otp_ctrl
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.16 96.15 86.96 87.38 93.10 97.18

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 96.86 97.40 96.15 97.12 96.43 97.18



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.86 97.40 96.15 97.12 96.43 97.18


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 93.88 96.77 95.80 91.41 96.95 96.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
core_tlul_assert_device 100.00 100.00 100.00 100.00
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
gen_alert_tx[1].u_prim_alert_sender 100.00 100.00
gen_alert_tx[2].u_prim_alert_sender 100.00 100.00
gen_alert_tx[3].u_prim_alert_sender 100.00 100.00
gen_alert_tx[4].u_prim_alert_sender 100.00 100.00
gen_bufs[0].u_prim_mubi8_sender_read_lock 100.00 100.00 100.00 100.00
gen_bufs[0].u_prim_mubi8_sender_write_lock 79.17 37.50 100.00 100.00
gen_bufs[10].u_prim_mubi8_sender_read_lock 79.17 37.50 100.00 100.00
gen_bufs[10].u_prim_mubi8_sender_write_lock 79.17 37.50 100.00 100.00
gen_bufs[1].u_prim_mubi8_sender_read_lock 100.00 100.00 100.00 100.00
gen_bufs[1].u_prim_mubi8_sender_write_lock 79.17 37.50 100.00 100.00
gen_bufs[2].u_prim_mubi8_sender_read_lock 100.00 100.00 100.00 100.00
gen_bufs[2].u_prim_mubi8_sender_write_lock 79.17 37.50 100.00 100.00
gen_bufs[3].u_prim_mubi8_sender_read_lock 100.00 100.00 100.00 100.00
gen_bufs[3].u_prim_mubi8_sender_write_lock 79.17 37.50 100.00 100.00
gen_bufs[4].u_prim_mubi8_sender_read_lock 100.00 100.00 100.00 100.00
gen_bufs[4].u_prim_mubi8_sender_write_lock 79.17 37.50 100.00 100.00
gen_bufs[5].u_prim_mubi8_sender_read_lock 79.17 37.50 100.00 100.00
gen_bufs[5].u_prim_mubi8_sender_write_lock 79.17 37.50 100.00 100.00
gen_bufs[6].u_prim_mubi8_sender_read_lock 79.17 37.50 100.00 100.00
gen_bufs[6].u_prim_mubi8_sender_write_lock 79.17 37.50 100.00 100.00
gen_bufs[7].u_prim_mubi8_sender_read_lock 79.17 37.50 100.00 100.00
gen_bufs[7].u_prim_mubi8_sender_write_lock 79.17 37.50 100.00 100.00
gen_bufs[8].u_prim_mubi8_sender_read_lock 79.17 37.50 100.00 100.00
gen_bufs[8].u_prim_mubi8_sender_write_lock 79.17 37.50 100.00 100.00
gen_bufs[9].u_prim_mubi8_sender_read_lock 100.00 100.00 100.00 100.00
gen_bufs[9].u_prim_mubi8_sender_write_lock 100.00 100.00 100.00 100.00
gen_partitions[0].gen_unbuffered.u_part_unbuf 97.56 100.00 100.00 100.00 90.00 98.15 97.22
gen_partitions[10].gen_lifecycle.u_part_buf 90.88 90.44 100.00 75.87 95.24 98.00 85.71
gen_partitions[1].gen_unbuffered.u_part_unbuf 98.32 100.00 100.00 100.00 91.67 98.25 100.00
gen_partitions[2].gen_unbuffered.u_part_unbuf 98.32 100.00 100.00 100.00 91.67 98.25 100.00
gen_partitions[3].gen_unbuffered.u_part_unbuf 98.32 100.00 100.00 100.00 91.67 98.25 100.00
gen_partitions[4].gen_unbuffered.u_part_unbuf 98.32 100.00 100.00 100.00 91.67 98.25 100.00
gen_partitions[5].gen_buffered.u_part_buf 94.58 98.28 95.24 100.00 92.00 95.59 86.36
gen_partitions[6].gen_buffered.u_part_buf 93.35 96.65 92.86 100.00 91.67 92.54 86.36
gen_partitions[7].gen_buffered.u_part_buf 95.77 98.54 93.75 100.00 91.67 95.00 95.65
gen_partitions[8].gen_buffered.u_part_buf 95.77 98.54 93.75 100.00 91.67 95.00 95.65
gen_partitions[9].gen_buffered.u_part_buf 96.69 98.54 93.75 100.00 97.22 95.00 95.65
otp_ctrl_core_csr_assert 100.00 100.00
prim_tlul_assert_device 100.00 100.00 100.00 100.00
u_edn_arb 93.86 92.31 89.80 100.00 93.33
u_intr_error 100.00 100.00 100.00 100.00 100.00
u_intr_operation_done 100.00 100.00 100.00 100.00 100.00
u_keygmr_key_valid 100.00 100.00 100.00
u_otp 98.90 93.58 99.81 100.00 100.00 100.00 100.00
u_otp_arb 97.43 98.07 97.92 100.00 93.75
u_otp_ctrl_dai 86.21 85.64 91.96 80.95 82.46 89.04 87.23
u_otp_ctrl_kdi 94.60 99.63 99.64 88.89 86.36 95.70 97.37
u_otp_ctrl_lci 100.00 100.00 100.00 100.00 100.00 100.00 100.00
u_otp_ctrl_lfsr_timer 96.45 100.00 97.47 81.25 100.00 100.00 100.00
u_otp_ctrl_scrmbl 96.92 81.50 100.00 100.00 100.00 100.00 100.00
u_otp_init_sync 100.00 100.00 100.00
u_otp_rsp_fifo 96.83 100.00 92.31 95.00 100.00
u_part_sel_idx 74.55 65.65 89.83 88.89 53.85
u_prim_edn_req 92.19 100.00 93.75 100.00 75.00
u_prim_lc_sender_otp_broadcast_valid 100.00 100.00 100.00
u_prim_lc_sender_rma_token_valid 100.00 100.00 100.00
u_prim_lc_sender_secrets_valid 100.00 100.00 100.00
u_prim_lc_sender_test_tokens_valid 100.00 100.00 100.00
u_prim_lc_sync_check_byp_en 100.00 100.00 100.00 100.00
u_prim_lc_sync_creator_seed_sw_rw_en 100.00 100.00 100.00 100.00
u_prim_lc_sync_dft_en 100.00 100.00 100.00 100.00
u_prim_lc_sync_escalate_en 100.00 100.00 100.00 100.00
u_prim_lc_sync_owner_seed_sw_rw_en 100.00 100.00 100.00 100.00
u_prim_lc_sync_seed_hw_rd_en 100.00 100.00 100.00 100.00
u_reg_core 99.15 99.65 96.09 100.00 100.00 100.00
u_scrmbl_mtx 79.48 75.00 99.17 100.00 43.75
u_tlul_adapter_sram 93.12 89.71 93.00 89.77 100.00
u_tlul_lc_gate 92.41 99.21 92.86 85.71 96.77 87.50

Line Coverage for Module : otp_ctrl
Line No.TotalCoveredPercent
TOTAL15615096.15
CONT_ASSIGN24711100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN24911100.00
ALWAYS280141392.86
ALWAYS30433100.00
ALWAYS320111090.91
CONT_ASSIGN37811100.00
CONT_ASSIGN38211100.00
CONT_ASSIGN38611100.00
CONT_ASSIGN39011100.00
CONT_ASSIGN39111100.00
CONT_ASSIGN39911100.00
CONT_ASSIGN40011100.00
ALWAYS40355100.00
ALWAYS4301919100.00
CONT_ASSIGN48411100.00
CONT_ASSIGN49211100.00
ALWAYS49599100.00
ALWAYS5171010100.00
CONT_ASSIGN58111100.00
CONT_ASSIGN58911100.00
CONT_ASSIGN63611100.00
CONT_ASSIGN63811100.00
CONT_ASSIGN76111100.00
CONT_ASSIGN76211100.00
CONT_ASSIGN76311100.00
CONT_ASSIGN79311100.00
CONT_ASSIGN79511100.00
ALWAYS87222100.00
ALWAYS93022100.00
ALWAYS95744100.00
CONT_ASSIGN98411100.00
ALWAYS98733100.00
CONT_ASSIGN103911100.00
CONT_ASSIGN104111100.00
CONT_ASSIGN1075100.00
CONT_ASSIGN1126100.00
CONT_ASSIGN118111100.00
CONT_ASSIGN118111100.00
CONT_ASSIGN118111100.00
CONT_ASSIGN118111100.00
CONT_ASSIGN118111100.00
CONT_ASSIGN123611100.00
CONT_ASSIGN1236100.00
CONT_ASSIGN123611100.00
CONT_ASSIGN123611100.00
CONT_ASSIGN123611100.00
CONT_ASSIGN129611100.00
CONT_ASSIGN1308100.00
CONT_ASSIGN133211100.00
ALWAYS134422100.00
CONT_ASSIGN135811100.00
ALWAYS138699100.00
CONT_ASSIGN141711100.00
CONT_ASSIGN141811100.00
CONT_ASSIGN142011100.00
CONT_ASSIGN142211100.00
CONT_ASSIGN142611100.00
CONT_ASSIGN142811100.00
CONT_ASSIGN143011100.00
CONT_ASSIGN143511100.00
CONT_ASSIGN143711100.00
CONT_ASSIGN143911100.00
CONT_ASSIGN147111100.00
CONT_ASSIGN147311100.00
CONT_ASSIGN147711100.00
CONT_ASSIGN148111100.00
CONT_ASSIGN148511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
247 1 1
249 10 10
280 1 1
281 1 1
282 1 1
283 1 1
284 1 1
285 1 1
288 0 1
MISSING_ELSE
293 1 1
294 1 1
295 1 1
296 1 1
297 1 1
298 1 1
299 1 1
304 1 1
305 1 1
307 1 1
320 1 1
325 1 1
326 1 1
330 1 1
331 1 1
332 1 1
333 1 1
MISSING_ELSE
MISSING_ELSE
337 1 1
338 1 1
339 1 1
340 0 1
MISSING_ELSE
MISSING_ELSE
378 1 1
382 1 1
386 1 1
390 1 1
391 1 1
399 1 1
400 1 1
403 1 1
404 1 1
406 1 1
408 1 1
409 1 1
430 1 1
431 1 1
432 1 1
434 1 1
436 1 1
439 1 1
441 1 1
444 1 1
445 1 1
MISSING_ELSE
449 1 1
451 1 1
455 1 1
458 1 1
460 1 1
465 1 1
466 1 1
MISSING_ELSE
468 1 1
469 1 1
MISSING_ELSE
474 1 1
484 1 1
492 1 1
495 1 1
496 1 1
497 1 1
498 1 1
499 1 1
501 1 1
502 1 1
503 1 1
504 1 1
517 1 1
519 1 1
521 1 1
523 1 1
525 1 1
534 1 1
536 1 1
537 1 1
538 1 1
539 1 1
581 1 1
589 1 1
636 1 1
638 1 1
761 1 1
762 1 1
763 1 1
793 1 1
795 1 1
872 1 1
873 1 1
930 1 1
931 1 1
957 1 1
958 1 1
959 1 1
960 1 1
984 1 1
987 1 1
988 1 1
990 1 1
1039 1 1
1041 1 1
1075 0 1
1126 0 1
1181 5 5
1236 4 5
1296 1 1
1308 0 1
1332 1 1
1344 1 1
1345 1 1
1358 1 1
1386 1 1
1387 1 1
1388 1 1
1389 1 1
1391 1 1
1392 1 1
1393 1 1
1394 1 1
1395 1 1
1417 1 1
1418 1 1
1420 1 1
1422 1 1
1426 1 1
1428 1 1
1430 1 1
1435 1 1
1437 1 1
1439 1 1
1471 1 1
1473 1 1
1477 1 1
1481 1 1
1485 1 1


Cond Coverage for Module : otp_ctrl
TotalCoveredPercent
Conditions11510086.96
Logical11510086.96
Non-Logical00
Event00

 LINE       249
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b00001000000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[1].PartEnd))
             -------------------1------------------   --------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T7
11CoveredT1,T3,T7

 LINE       249
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b00111101000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[2].PartEnd))
             -------------------1------------------   --------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T7
11CoveredT1,T7,T4

 LINE       249
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b10001111000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[3].PartEnd))
             -------------------1------------------   --------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T7
11CoveredT1,T3,T7

 LINE       249
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11001010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[4].PartEnd))
             -------------------1------------------   --------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT8,T9,T13
11CoveredT1,T3,T7

 LINE       249
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11001111000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[5].PartEnd))
             -------------------1------------------   --------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT8,T9,T13
11CoveredT8,T9,T13

 LINE       249
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011000000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[6].PartEnd))
             -------------------1------------------   --------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT8,T9,T13
11CoveredT8,T9,T13

 LINE       249
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[7].PartEnd))
             -------------------1------------------   --------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT8,T9,T13
11CoveredT8,T9,T13

 LINE       249
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011111000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[8].PartEnd))
             -------------------1------------------   --------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT8,T9,T13
11CoveredT8,T9,T13

 LINE       249
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11101010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[9].PartEnd))
             -------------------1------------------   --------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT8,T9,T13
11CoveredT8,T9,T13

 LINE       249
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11110101000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[10].PartEnd))
             -------------------1------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT8,T9,T13

 LINE       284
 EXPRESSION (tlul_part_sel_oh != '0)
            ------------1-----------
-1-StatusTests
0Not Covered
1CoveredT1,T3,T7

 LINE       293
 EXPRESSION (((|part_tlul_gnt)) | tlul_oob_err_q)
             ---------1--------   -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T3,T7

 LINE       294
 EXPRESSION (((|part_tlul_rvalid)) | tlul_oob_err_q)
             ----------1----------   -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T3,T7

 LINE       378
 EXPRESSION ((reg2hw.direct_access_regwen.qe && ((!reg2hw.direct_access_regwen.q))) ? 1'b0 : direct_access_regwen_q)
             -----------------------------------1----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       378
 SUB-EXPRESSION (reg2hw.direct_access_regwen.qe && ((!reg2hw.direct_access_regwen.q)))
                 ---------------1--------------    -----------------2----------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       382
 EXPRESSION (reg2hw.direct_access_cmd.digest.qe | reg2hw.direct_access_cmd.wr.qe | reg2hw.direct_access_cmd.rd.qe)
             -----------------1----------------   ---------------2--------------   ---------------3--------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010Not Covered
100Not Covered

 LINE       399
 EXPRESSION (lci_prog_idle & dai_prog_idle)
             ------1------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T7
11CoveredT1,T2,T3

 LINE       432
 EXPRESSION (fatal_bus_integ_error_q | ((|intg_error)))
             -----------1-----------   -------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT22,T23,T24
10Not Covered

 LINE       441
 EXPRESSION (part_error[k] == MacroError)
            --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       445
 EXPRESSION (part_error[k] == MacroEccUncorrError)
            -------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T11

 LINE       465
 EXPRESSION (fatal_macro_error_q || fatal_check_error_q)
             ---------1---------    ---------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT7,T10,T5
10CoveredT1,T3,T11

 LINE       474
 EXPRESSION (chk_timeout | lfsr_fsm_err | scrmbl_fsm_err | ((|part_fsm_err)))
             -----1-----   ------2-----   -------3------   --------4--------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001CoveredT1,T3,T7
0010CoveredT22,T23,T24
0100CoveredT22,T23,T24
1000CoveredT5,T8,T36

 LINE       523
 EXPRESSION (direct_access_regwen_q & dai_idle)
             -----------1----------   ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       589
 SUB-EXPRESSION (reg2hw.alert_test.recov_prim_otp_alert.q & reg2hw.alert_test.recov_prim_otp_alert.qe)
                 --------------------1-------------------   --------------------2--------------------
-1--2-StatusTests
01CoveredT2,T208,T179
10CoveredT1,T2,T3
11CoveredT2,T208,T179

 LINE       589
 SUB-EXPRESSION (reg2hw.alert_test.fatal_prim_otp_alert.q & reg2hw.alert_test.fatal_prim_otp_alert.qe)
                 --------------------1-------------------   --------------------2--------------------
-1--2-StatusTests
01CoveredT2,T208,T179
10CoveredT1,T2,T3
11CoveredT2,T208,T179

 LINE       589
 SUB-EXPRESSION (reg2hw.alert_test.fatal_bus_integ_error.q & reg2hw.alert_test.fatal_bus_integ_error.qe)
                 --------------------1--------------------   ---------------------2--------------------
-1--2-StatusTests
01CoveredT2,T208,T179
10CoveredT1,T2,T3
11CoveredT2,T208,T179

 LINE       589
 SUB-EXPRESSION (reg2hw.alert_test.fatal_check_error.q & reg2hw.alert_test.fatal_check_error.qe)
                 ------------------1------------------   -------------------2------------------
-1--2-StatusTests
01CoveredT2,T208,T179
10CoveredT1,T2,T3
11CoveredT2,T208,T179

 LINE       589
 SUB-EXPRESSION (reg2hw.alert_test.fatal_macro_error.q & reg2hw.alert_test.fatal_macro_error.qe)
                 ------------------1------------------   -------------------2------------------
-1--2-StatusTests
01CoveredT2,T208,T179
10CoveredT1,T2,T3
11CoveredT2,T208,T179

 LINE       636
 EXPRESSION (reg2hw.check_trigger.integrity.q & reg2hw.check_trigger.integrity.qe)
             ----------------1---------------   ----------------2----------------
-1--2-StatusTests
01CoveredT4,T10,T5
10CoveredT1,T2,T3
11CoveredT4,T10,T5

 LINE       638
 EXPRESSION (reg2hw.check_trigger.consistency.q & reg2hw.check_trigger.consistency.qe)
             -----------------1----------------   -----------------2-----------------
-1--2-StatusTests
01CoveredT4,T10,T5
10CoveredT1,T2,T3
11CoveredT4,T10,T5

 LINE       761
 EXPRESSION (otp_prim_ready & otp_rsp_fifo_ready)
             -------1------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       762
 EXPRESSION (otp_arb_valid & otp_rsp_fifo_ready)
             ------1------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       763
 EXPRESSION (otp_prim_ready & otp_prim_valid)
             -------1------   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       873
 EXPRESSION (otp_rvalid & otp_fifo_valid)
             -----1----   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       1417
 EXPRESSION (part_digest[Secret1Idx] != '0)
            ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       1435
 EXPRESSION ((part_digest[Secret0Idx] != '0) ? On : Off)
             ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T4,T5

 LINE       1435
 SUB-EXPRESSION (part_digest[Secret0Idx] != '0)
                ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T4,T5

 LINE       1437
 EXPRESSION ((part_digest[Secret2Idx] != '0) ? On : Off)
             ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T36

 LINE       1437
 SUB-EXPRESSION (part_digest[Secret2Idx] != '0)
                ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T36

 LINE       1439
 EXPRESSION ((part_digest[Secret2Idx] != '0) ? On : Off)
             ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T36

 LINE       1439
 SUB-EXPRESSION (part_digest[Secret2Idx] != '0)
                ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T36

Toggle Coverage for Module : otp_ctrl
TotalCoveredPercent
Totals 156 142 91.03
Total Bits 11096 9696 87.38
Total Bits 0->1 5548 4848 87.38
Total Bits 1->0 5548 4848 87.38

Ports 156 142 91.03
Port Bits 11096 9696 87.38
Port Bits 0->1 5548 4848 87.38
Port Bits 1->0 5548 4848 87.38

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T3,T7 Yes T1,T2,T3 INPUT
clk_edn_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_edn_ni Yes Yes T1,T3,T7 Yes T1,T2,T3 INPUT
edn_o.edn_req Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_i.edn_bus[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
edn_i.edn_fips Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
edn_i.edn_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
core_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_user.instr_type[3:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
core_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
core_tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_address[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
core_tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
core_tl_o.d_error Yes Yes T4,T10,T5 Yes T4,T10,T5 OUTPUT
core_tl_o.d_user.data_intg[6:0] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
core_tl_o.d_user.rsp_intg[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
core_tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
core_tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T3,T7 OUTPUT
core_tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
core_tl_o.d_source[7:0] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
core_tl_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
core_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
core_tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
core_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
core_tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
prim_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
prim_tl_i.a_user.data_intg[6:0] Yes Yes T3,T4,T10 Yes T3,T4,T10 INPUT
prim_tl_i.a_user.cmd_intg[6:0] Yes Yes T3,T7,T4 Yes T3,T7,T4 INPUT
prim_tl_i.a_user.instr_type[3:0] Yes Yes T3,T7,T11 Yes T3,T7,T11 INPUT
prim_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
prim_tl_i.a_data[31:0] Yes Yes T3,T7,T4 Yes T7,T4,T10 INPUT
prim_tl_i.a_mask[3:0] Yes Yes T3,T7,T11 Yes T3,T7,T11 INPUT
prim_tl_i.a_address[31:0] Yes Yes T3,T11,T5 Yes T3,T7,T5 INPUT
prim_tl_i.a_source[7:0] Yes Yes T3,T7,T4 Yes T7,T4,T10 INPUT
prim_tl_i.a_size[1:0] Yes Yes T3,T7,T11 Yes T3,T7,T5 INPUT
prim_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
prim_tl_i.a_opcode[2:0] Yes Yes T3,T7,T4 Yes T3,T4,T10 INPUT
prim_tl_i.a_valid Yes Yes T4,T10,T5 Yes T4,T10,T5 INPUT
prim_tl_o.a_ready Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
prim_tl_o.d_error Yes Yes T2,T5,T6 Yes T5,T6,T8 OUTPUT
prim_tl_o.d_user.data_intg[6:0] Yes Yes T6,T15,T13 Yes T6,T15,T13 OUTPUT
prim_tl_o.d_user.rsp_intg[5:0] Yes Yes *T4,*T10,*T5 Yes T4,T10,T5 OUTPUT
prim_tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
prim_tl_o.d_data[31:0] Yes Yes T2,T5,T6 Yes T5,T6,T8 OUTPUT
prim_tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
prim_tl_o.d_source[7:0] Yes Yes T4,T10,T5 Yes T4,T10,T5 OUTPUT
prim_tl_o.d_size[1:0] Yes Yes T8,T9,T13 Yes T8,T9,T13 OUTPUT
prim_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
prim_tl_o.d_opcode[0] Yes Yes *T2,*T4,*T10 Yes T4,T10,T5 OUTPUT
prim_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
prim_tl_o.d_valid Yes Yes T4,T10,T5 Yes T4,T10,T5 OUTPUT
intr_otp_operation_done_o Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
intr_otp_error_o Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[2].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[2].ack_p Yes Yes T2,T208,T22 Yes T2,T208,T22 INPUT
alert_rx_i[2].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[2].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[3].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[3].ack_p Yes Yes T2,T208,T22 Yes T2,T208,T22 INPUT
alert_rx_i[3].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[3].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[4].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[4].ack_p Yes Yes T2,T208,T179 Yes T2,T208,T179 INPUT
alert_rx_i[4].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[4].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[2].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[2].alert_p Yes Yes T2,T208,T22 Yes T2,T208,T22 OUTPUT
alert_tx_o[3].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[3].alert_p Yes Yes T2,T208,T22 Yes T2,T208,T22 OUTPUT
alert_tx_o[4].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[4].alert_p Yes Yes T2,T208,T179 Yes T2,T208,T179 OUTPUT
obs_ctrl_i.obmen[3:0] No No No INPUT
obs_ctrl_i.obmsl[3:0] No No No INPUT
obs_ctrl_i.obgsl[3:0] No No No INPUT
otp_obs_o[7:0] Unreachable Unreachable Unreachable OUTPUT
otp_ast_pwr_seq_o.pwr_seq[1:0] No No No OUTPUT
otp_ast_pwr_seq_h_i.pwr_seq_h[1:0] Yes Yes T1,T4,T10 Yes T3,T4,T5 INPUT
pwr_otp_i.otp_init Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
pwr_otp_o.otp_idle Yes Yes T1,T3,T7 Yes T1,T2,T3 OUTPUT
pwr_otp_o.otp_done Yes Yes T1,T3,T7 Yes T1,T2,T3 OUTPUT
lc_otp_vendor_test_i.ctrl[31:0] No No No INPUT
lc_otp_vendor_test_o.status[31:0] No No No OUTPUT
lc_otp_program_i.count[383:0] Yes Yes T6,T8,T110 Yes T6,T16,T241 INPUT
lc_otp_program_i.state[319:0] Yes Yes T6,T8,T9 Yes T6,T9,T16 INPUT
lc_otp_program_i.req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
lc_otp_program_o.ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
lc_otp_program_o.err Yes Yes T110,T9,T113 Yes T110,T9,T113 OUTPUT
lc_creator_seed_sw_rw_en_i[3:0] Yes Yes T4,T10,T5 Yes T4,T10,T5 INPUT
lc_owner_seed_sw_rw_en_i[3:0] Yes Yes T4,T10,T5 Yes T4,T5,T6 INPUT
lc_seed_hw_rd_en_i[3:0] Yes Yes T4,T5,T6 Yes T3,T4,T11 INPUT
lc_dft_en_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T4 INPUT
lc_escalate_en_i[3:0] Yes Yes T10,T6,T109 Yes T10,T6,T109 INPUT
lc_check_byp_en_i[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
otp_lc_data_o.rma_token[127:0] Yes Yes T1,T3,T7 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.rma_token_valid[3:0] Yes Yes T5,T6,T36 Yes T5,T6,T36 OUTPUT
otp_lc_data_o.test_exit_token[127:0] Yes Yes T5,T6,T119 Yes T5,T6,T119 OUTPUT
otp_lc_data_o.test_unlock_token[127:0] Yes Yes T1,T2,T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.test_tokens_valid[3:0] Yes Yes T7,T5,T6 Yes T7,T4,T5 OUTPUT
otp_lc_data_o.secrets_valid[3:0] Yes Yes T5,T6,T36 Yes T5,T6,T36 OUTPUT
otp_lc_data_o.count[0] No No No OUTPUT
otp_lc_data_o.count[8:1] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.count[9] No No No OUTPUT
otp_lc_data_o.count[14:10] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.count[16:15] No No No OUTPUT
otp_lc_data_o.count[31:17] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.count[32] No No No OUTPUT
otp_lc_data_o.count[46:33] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.count[47] No No No OUTPUT
otp_lc_data_o.count[61:48] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.count[64:62] No No No OUTPUT
otp_lc_data_o.count[76:65] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.count[77] No No No OUTPUT
otp_lc_data_o.count[78] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.count[79] No No No OUTPUT
otp_lc_data_o.count[84:80] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.count[86:85] No No No OUTPUT
otp_lc_data_o.count[88:87] Yes Yes T1,T2,T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.count[89] No No No OUTPUT
otp_lc_data_o.count[101:90] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.count[102] No No No OUTPUT
otp_lc_data_o.count[105:103] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.count[106] No No No OUTPUT
otp_lc_data_o.count[115:107] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.count[116] No No No OUTPUT
otp_lc_data_o.count[118:117] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.count[119] No No No OUTPUT
otp_lc_data_o.count[121:120] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.count[122] No No No OUTPUT
otp_lc_data_o.count[124:123] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.count[125] No No No OUTPUT
otp_lc_data_o.count[134:126] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.count[135] No No No OUTPUT
otp_lc_data_o.count[155:136] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.count[156] No No No OUTPUT
otp_lc_data_o.count[164:157] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.count[166:165] No No No OUTPUT
otp_lc_data_o.count[174:167] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.count[176:175] No No No OUTPUT
otp_lc_data_o.count[185:177] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.count[187:186] No No No OUTPUT
otp_lc_data_o.count[191:188] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.count[192] No No No OUTPUT
otp_lc_data_o.count[193] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.count[194] No No No OUTPUT
otp_lc_data_o.count[202:195] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.count[203] No No No OUTPUT
otp_lc_data_o.count[207:204] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.count[208] No No No OUTPUT
otp_lc_data_o.count[218:209] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.count[219] No No No OUTPUT
otp_lc_data_o.count[225:220] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.count[226] No No No OUTPUT
otp_lc_data_o.count[237:227] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.count[238] No No No OUTPUT
otp_lc_data_o.count[251:239] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.count[252] No No No OUTPUT
otp_lc_data_o.count[272:253] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.count[273] No No No OUTPUT
otp_lc_data_o.count[274] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.count[275] No No No OUTPUT
otp_lc_data_o.count[302:276] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.count[304:303] No No No OUTPUT
otp_lc_data_o.count[309:305] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.count[310] No No No OUTPUT
otp_lc_data_o.count[312:311] Yes Yes T1,T2,T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.count[313] No No No OUTPUT
otp_lc_data_o.count[316:314] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.count[317] No No No OUTPUT
otp_lc_data_o.count[324:318] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.count[325] No No No OUTPUT
otp_lc_data_o.count[327:326] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.count[328] No No No OUTPUT
otp_lc_data_o.count[336:329] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.count[337] No No No OUTPUT
otp_lc_data_o.count[338] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.count[339] No No No OUTPUT
otp_lc_data_o.count[343:340] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.count[344] No No No OUTPUT
otp_lc_data_o.count[364:345] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.count[366:365] No No No OUTPUT
otp_lc_data_o.count[375:367] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.count[376] No No No OUTPUT
otp_lc_data_o.count[383:377] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.state[5:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.state[6] No No No OUTPUT
otp_lc_data_o.state[12:7] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.state[13] No No No OUTPUT
otp_lc_data_o.state[14] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.state[16:15] No No No OUTPUT
otp_lc_data_o.state[17] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.state[19:18] No No No OUTPUT
otp_lc_data_o.state[34:20] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.state[36:35] No No No OUTPUT
otp_lc_data_o.state[42:37] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.state[43] No No No OUTPUT
otp_lc_data_o.state[50:44] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.state[52:51] No No No OUTPUT
otp_lc_data_o.state[59:53] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.state[60] No No No OUTPUT
otp_lc_data_o.state[61] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.state[62] No No No OUTPUT
otp_lc_data_o.state[68:63] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.state[69] No No No OUTPUT
otp_lc_data_o.state[75:70] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.state[76] No No No OUTPUT
otp_lc_data_o.state[79:77] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.state[80] No No No OUTPUT
otp_lc_data_o.state[84:81] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.state[85] No No No OUTPUT
otp_lc_data_o.state[95:86] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.state[96] No No No OUTPUT
otp_lc_data_o.state[98:97] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.state[99] No No No OUTPUT
otp_lc_data_o.state[103:100] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.state[104] No No No OUTPUT
otp_lc_data_o.state[105] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.state[107:106] No No No OUTPUT
otp_lc_data_o.state[113:108] Yes Yes T1,T2,T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.state[114] No No No OUTPUT
otp_lc_data_o.state[121:115] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.state[122] No No No OUTPUT
otp_lc_data_o.state[123] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.state[124] No No No OUTPUT
otp_lc_data_o.state[136:125] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.state[137] No No No OUTPUT
otp_lc_data_o.state[145:138] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.state[147:146] No No No OUTPUT
otp_lc_data_o.state[151:148] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.state[152] No No No OUTPUT
otp_lc_data_o.state[157:153] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.state[158] No No No OUTPUT
otp_lc_data_o.state[160:159] Yes Yes T1,T2,T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.state[161] No No No OUTPUT
otp_lc_data_o.state[163:162] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.state[164] No No No OUTPUT
otp_lc_data_o.state[165] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.state[166] No No No OUTPUT
otp_lc_data_o.state[180:167] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.state[181] No No No OUTPUT
otp_lc_data_o.state[186:182] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.state[187] No No No OUTPUT
otp_lc_data_o.state[206:188] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.state[207] No No No OUTPUT
otp_lc_data_o.state[210:208] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.state[211] No No No OUTPUT
otp_lc_data_o.state[226:212] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.state[227] No No No OUTPUT
otp_lc_data_o.state[230:228] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.state[231] No No No OUTPUT
otp_lc_data_o.state[234:232] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.state[236:235] No No No OUTPUT
otp_lc_data_o.state[246:237] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.state[247] No No No OUTPUT
otp_lc_data_o.state[263:248] Yes Yes *T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.state[264] No No No OUTPUT
otp_lc_data_o.state[273:265] Yes Yes *T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.state[274] No No No OUTPUT
otp_lc_data_o.state[278:275] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.state[279] No No No OUTPUT
otp_lc_data_o.state[285:280] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.state[286] No No No OUTPUT
otp_lc_data_o.state[301:287] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.state[302] No No No OUTPUT
otp_lc_data_o.state[311:303] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.state[312] No No No OUTPUT
otp_lc_data_o.state[319:313] Yes Yes T1,T2,T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.error Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.valid Yes Yes T1,T3,T7 Yes T1,T2,T3 OUTPUT
otp_keymgr_key_o.owner_seed_valid No No No OUTPUT
otp_keymgr_key_o.owner_seed[255:0] No No No OUTPUT
otp_keymgr_key_o.creator_seed_valid No No No OUTPUT
otp_keymgr_key_o.creator_seed[255:0] No No No OUTPUT
otp_keymgr_key_o.creator_root_key_share1_valid Yes Yes T5,T6,T36 Yes T5,T6,T36 OUTPUT
otp_keymgr_key_o.creator_root_key_share1[255:0] Yes Yes T5,T12,T103 Yes T5,T103,T242 OUTPUT
otp_keymgr_key_o.creator_root_key_share0_valid Yes Yes T5,T6,T36 Yes T5,T6,T36 OUTPUT
otp_keymgr_key_o.creator_root_key_share0[255:0] Yes Yes T6,T103,T237 Yes T6,T103,T237 OUTPUT
flash_otp_key_i.addr_req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
flash_otp_key_i.data_req Yes Yes T4,T10,T5 Yes T4,T10,T5 INPUT
flash_otp_key_o.seed_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
flash_otp_key_o.rand_key[127:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
flash_otp_key_o.key[127:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
flash_otp_key_o.addr_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
flash_otp_key_o.data_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
sram_otp_key_i[0].req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sram_otp_key_i[1].req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sram_otp_key_i[2].req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sram_otp_key_i[3].req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sram_otp_key_o[0].seed_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
sram_otp_key_o[0].nonce[127:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
sram_otp_key_o[0].key[127:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
sram_otp_key_o[0].ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
sram_otp_key_o[1].seed_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
sram_otp_key_o[1].nonce[127:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
sram_otp_key_o[1].key[127:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
sram_otp_key_o[1].ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
sram_otp_key_o[2].seed_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
sram_otp_key_o[2].nonce[127:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
sram_otp_key_o[2].key[127:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
sram_otp_key_o[2].ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
sram_otp_key_o[3].seed_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
sram_otp_key_o[3].nonce[127:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
sram_otp_key_o[3].key[127:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
sram_otp_key_o[3].ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otbn_otp_key_i.req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
otbn_otp_key_o.seed_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otbn_otp_key_o.nonce[63:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otbn_otp_key_o.key[127:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otbn_otp_key_o.ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_broadcast_o.hw_cfg0_data.device_id[255:0] Yes Yes T1,T2,T3 Yes T1,T3,T7 OUTPUT
otp_broadcast_o.hw_cfg0_data.manuf_state[255:0] Yes Yes T1,T2,T3 Yes T1,T3,T7 OUTPUT
otp_broadcast_o.hw_cfg0_data.hw_cfg0_digest[63:0] Yes Yes T5,T6,T12 Yes T5,T6,T12 OUTPUT
otp_broadcast_o.hw_cfg1_data.en_sram_ifetch[7:0] Yes Yes T1,T2,T3 Yes T1,T3,T7 OUTPUT
otp_broadcast_o.hw_cfg1_data.en_csrng_sw_app_read[7:0] Yes Yes T1,T2,T3 Yes T1,T3,T7 OUTPUT
otp_broadcast_o.hw_cfg1_data.dis_rv_dm_late_debug[7:0] Yes Yes T1,T2,T3 Yes T1,T3,T7 OUTPUT
otp_broadcast_o.hw_cfg1_data.unallocated[39:0] Yes Yes T6,T55,T56 Yes T6,T55,T56 OUTPUT
otp_broadcast_o.hw_cfg1_data.hw_cfg1_digest[63:0] Yes Yes T1,T2,T3 Yes T1,T3,T7 OUTPUT
otp_broadcast_o.valid[3:0] Yes Yes T1,T3,T7 Yes T1,T2,T3 OUTPUT
otp_ext_voltage_h_io No No No INOUT
scan_en_i Yes Yes T4,T5,T6 Yes T3,T4,T5 INPUT
scan_rst_ni Yes Yes T4,T5,T6 Yes T1,T7,T4 INPUT
scanmode_i[3:0] Yes Yes T4,T10,T5 Yes T3,T4,T11 INPUT
cio_test_o[7:0] No No No OUTPUT
cio_test_en_o[7:0] Yes Yes T5,T6,T8 Yes T2,T5,T6 OUTPUT

*Tests covering at least one bit in the range

Branch Coverage for Module : otp_ctrl
Line No.TotalCoveredPercent
Branches 29 27 93.10
TERNARY 378 2 1 50.00
TERNARY 1435 2 2 100.00
TERNARY 1437 2 2 100.00
TERNARY 1439 2 2 100.00
IF 283 3 2 66.67
IF 304 2 2 100.00
IF 330 2 2 100.00
IF 337 2 2 100.00
IF 403 2 2 100.00
IF 444 2 2 100.00
IF 465 2 2 100.00
IF 468 2 2 100.00
IF 495 2 2 100.00
IF 987 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 378 ((reg2hw.direct_access_regwen.qe && (!reg2hw.direct_access_regwen.q))) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 1435 ((part_digest[Secret0Idx] != '0)) ?

Branches:
-1-StatusTests
1 Covered T7,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 1437 ((part_digest[Secret2Idx] != '0)) ?

Branches:
-1-StatusTests
1 Covered T5,T6,T36
0 Covered T1,T2,T3


LineNo. Expression -1-: 1439 ((part_digest[Secret2Idx] != '0)) ?

Branches:
-1-StatusTests
1 Covered T5,T6,T36
0 Covered T1,T2,T3


LineNo. Expression -1-: 283 if (tlul_req) -2-: 284 if ((tlul_part_sel_oh != '0))

Branches:
-1--2-StatusTests
1 1 Covered T1,T3,T7
1 0 Not Covered
0 - Covered T1,T2,T3


LineNo. Expression -1-: 304 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 330 if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_creator_seed_sw_rw_en))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 337 if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_owner_seed_sw_rw_en))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 403 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 444 if (otp_ctrl_part_pkg::PartInfo[k].integrity)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 465 if ((fatal_macro_error_q || fatal_check_error_q))

Branches:
-1-StatusTests
1 Covered T1,T3,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 468 if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_escalate_en[k]))

Branches:
-1-StatusTests
1 Covered T1,T3,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 495 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 987 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : otp_ctrl
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 71 71 100.00 69 97.18
Cover properties 0 0 0
Cover sequences 0 0 0
Total 71 71 100.00 69 97.18




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertTxKnown_A 473145275 472271170 0 0
CoreTlOutKnown_A 473145275 472271170 0 0
CreatorRootKeyShare0Size_A 1150 1150 0 0
CreatorRootKeyShare1Size_A 1150 1150 0 0
ErrorCodeWidth_A 1150 1150 0 0
FlashAddrKeySeedSize_A 1150 1150 0 0
FlashDataKeySeedSize_A 1150 1150 0 0
FlashOtpKeyRspKnown_A 473145275 472271170 0 0
FpvSecCmCntCnstyCheck_A 473145275 50 0 0
FpvSecCmCntDaiCheck_A 473145275 50 0 0
FpvSecCmCntIntegCheck_A 473145275 50 0 0
FpvSecCmCntKdiEntropyCheck_A 473145275 50 0 0
FpvSecCmCntKdiSeedCheck_A 473145275 50 0 0
FpvSecCmCntLciCheck_A 473145275 50 0 0
FpvSecCmCntScrmblCheck_A 473145275 50 0 0
FpvSecCmCtrlDaiFsmCheck_A 473145275 50 0 0
FpvSecCmCtrlKdiFsmCheck_A 473145275 50 0 0
FpvSecCmCtrlLciFsmCheck_A 473145275 50 0 0
FpvSecCmCtrlLfsrTimerFsmCheck_A 473145275 50 0 0
FpvSecCmCtrlScrambleFsmCheck_A 473145275 50 0 0
FpvSecCmDoubleLfsrCheck_A 473145275 50 0 0
FpvSecCmRegWeOnehotCheck_A 473145275 50 0 0
FpvSecCmTlLcGateFsm_A 473145275 50 0 0
IntrOtpErrorKnown_A 473145275 472271170 0 0
IntrOtpOperationDoneKnown_A 473145275 472271170 0 0
LcOtpProgramRspKnown_A 473145275 472271170 0 0
LcSeedHwRdEnStable0_A 473145275 2323 0 0
LcSeedHwRdEnStable1_A 473145275 2323 0 0
LcSeedHwRdEnStable2_A 473145275 0 0 0
LcSeedHwRdEnStable3_A 473145275 0 0 0
LcStateSize_A 1150 1150 0 0
LcTransitionCntSize_A 1150 1150 0 0
OtpAstPwrSeqKnown_A 473145275 472271170 0 0
OtpBroadcastKnown_A 473145275 472271170 0 0
OtpErrorCode0_A 1150 1150 0 0
OtpErrorCode1_A 1150 1150 0 0
OtpErrorCode2_A 1150 1150 0 0
OtpErrorCode3_A 1150 1150 0 0
OtpErrorCode4_A 1150 1150 0 0
OtpIfWidth_A 1150 1150 0 0
OtpKeymgrKeyKnown_A 473145275 472271170 0 0
OtpLcDataKnown_A 473145275 472271170 0 0
OtpOtgnKeyKnown_A 473145275 472271170 0 0
OtpRespFifoUnderflow_A 473145275 1518652 0 0
OtpSramKeyKnown_A 473145275 472271170 0 0
PartSelMustBeOnehot_A 473145275 472271170 0 0
PrimTlOutKnown_A 473145275 472271170 0 0
PwrOtpInitRspKnown_A 473145275 472271170 0 0
RmaTokenSize_A 1150 1150 0 0
SramDataKeySeedSize_A 1150 1150 0 0
TestExitTokenSize_A 1150 1150 0 0
TestUnlockTokenSize_A 1150 1150 0 0
gen_partitions[0].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A 473145275 50 0 0
gen_partitions[10].gen_lifecycle.FpvSecCmCntPartLcCheck_A 473145275 50 0 0
gen_partitions[10].gen_lifecycle.FpvSecCmCtrlPartLcFsmCheck_A 473145275 50 0 0
gen_partitions[1].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A 473145275 50 0 0
gen_partitions[2].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A 473145275 50 0 0
gen_partitions[3].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A 473145275 50 0 0
gen_partitions[4].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A 473145275 50 0 0
gen_partitions[5].gen_buffered.FpvSecCmCntPartBufCheck_A 473145275 50 0 0
gen_partitions[5].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A 473145275 50 0 0
gen_partitions[6].gen_buffered.FpvSecCmCntPartBufCheck_A 473145275 50 0 0
gen_partitions[6].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A 473145275 50 0 0
gen_partitions[7].gen_buffered.FpvSecCmCntPartBufCheck_A 473145275 50 0 0
gen_partitions[7].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A 473145275 50 0 0
gen_partitions[8].gen_buffered.FpvSecCmCntPartBufCheck_A 473145275 50 0 0
gen_partitions[8].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A 473145275 50 0 0
gen_partitions[9].gen_buffered.FpvSecCmCntPartBufCheck_A 473145275 50 0 0
gen_partitions[9].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A 473145275 50 0 0
gen_reg_we_assert_generic.FpvSecCmPrimFsmCheck_A 473145275 50 0 0
gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A 473145275 50 0 0


AlertTxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 472271170 0 0
T1 10539 10268 0 0
T2 8797 8711 0 0
T3 15153 14867 0 0
T4 46685 45790 0 0
T5 276043 271746 0 0
T6 417024 411962 0 0
T7 9956 9720 0 0
T10 108168 107950 0 0
T11 12051 11890 0 0
T12 99707 98887 0 0

CoreTlOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 472271170 0 0
T1 10539 10268 0 0
T2 8797 8711 0 0
T3 15153 14867 0 0
T4 46685 45790 0 0
T5 276043 271746 0 0
T6 417024 411962 0 0
T7 9956 9720 0 0
T10 108168 107950 0 0
T11 12051 11890 0 0
T12 99707 98887 0 0

CreatorRootKeyShare0Size_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1150 1150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

CreatorRootKeyShare1Size_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1150 1150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

ErrorCodeWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1150 1150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

FlashAddrKeySeedSize_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1150 1150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

FlashDataKeySeedSize_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1150 1150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

FlashOtpKeyRspKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 472271170 0 0
T1 10539 10268 0 0
T2 8797 8711 0 0
T3 15153 14867 0 0
T4 46685 45790 0 0
T5 276043 271746 0 0
T6 417024 411962 0 0
T7 9956 9720 0 0
T10 108168 107950 0 0
T11 12051 11890 0 0
T12 99707 98887 0 0

FpvSecCmCntCnstyCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

FpvSecCmCntDaiCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

FpvSecCmCntIntegCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

FpvSecCmCntKdiEntropyCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

FpvSecCmCntKdiSeedCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

FpvSecCmCntLciCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

FpvSecCmCntScrmblCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

FpvSecCmCtrlDaiFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

FpvSecCmCtrlKdiFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

FpvSecCmCtrlLciFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

FpvSecCmCtrlLfsrTimerFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

FpvSecCmCtrlScrambleFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

FpvSecCmDoubleLfsrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

FpvSecCmTlLcGateFsm_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

IntrOtpErrorKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 472271170 0 0
T1 10539 10268 0 0
T2 8797 8711 0 0
T3 15153 14867 0 0
T4 46685 45790 0 0
T5 276043 271746 0 0
T6 417024 411962 0 0
T7 9956 9720 0 0
T10 108168 107950 0 0
T11 12051 11890 0 0
T12 99707 98887 0 0

IntrOtpOperationDoneKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 472271170 0 0
T1 10539 10268 0 0
T2 8797 8711 0 0
T3 15153 14867 0 0
T4 46685 45790 0 0
T5 276043 271746 0 0
T6 417024 411962 0 0
T7 9956 9720 0 0
T10 108168 107950 0 0
T11 12051 11890 0 0
T12 99707 98887 0 0

LcOtpProgramRspKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 472271170 0 0
T1 10539 10268 0 0
T2 8797 8711 0 0
T3 15153 14867 0 0
T4 46685 45790 0 0
T5 276043 271746 0 0
T6 417024 411962 0 0
T7 9956 9720 0 0
T10 108168 107950 0 0
T11 12051 11890 0 0
T12 99707 98887 0 0

LcSeedHwRdEnStable0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 2323 0 0
T5 276043 19 0 0
T6 417024 18 0 0
T8 104294 0 0 0
T12 99707 0 0 0
T36 62070 7 0 0
T101 0 12 0 0
T102 0 2 0 0
T108 101822 0 0 0
T109 14593 0 0 0
T110 20566 0 0 0
T111 36286 0 0 0
T112 63940 0 0 0
T115 0 1 0 0
T117 0 2 0 0
T118 0 1 0 0
T119 0 2 0 0
T121 0 1 0 0

LcSeedHwRdEnStable1_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 2323 0 0
T5 276043 19 0 0
T6 417024 18 0 0
T8 104294 0 0 0
T12 99707 0 0 0
T36 62070 7 0 0
T101 0 12 0 0
T102 0 2 0 0
T108 101822 0 0 0
T109 14593 0 0 0
T110 20566 0 0 0
T111 36286 0 0 0
T112 63940 0 0 0
T115 0 1 0 0
T117 0 2 0 0
T118 0 1 0 0
T119 0 2 0 0
T121 0 1 0 0

LcSeedHwRdEnStable2_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 0 0 0

LcSeedHwRdEnStable3_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 0 0 0

LcStateSize_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1150 1150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

LcTransitionCntSize_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1150 1150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

OtpAstPwrSeqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 472271170 0 0
T1 10539 10268 0 0
T2 8797 8711 0 0
T3 15153 14867 0 0
T4 46685 45790 0 0
T5 276043 271746 0 0
T6 417024 411962 0 0
T7 9956 9720 0 0
T10 108168 107950 0 0
T11 12051 11890 0 0
T12 99707 98887 0 0

OtpBroadcastKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 472271170 0 0
T1 10539 10268 0 0
T2 8797 8711 0 0
T3 15153 14867 0 0
T4 46685 45790 0 0
T5 276043 271746 0 0
T6 417024 411962 0 0
T7 9956 9720 0 0
T10 108168 107950 0 0
T11 12051 11890 0 0
T12 99707 98887 0 0

OtpErrorCode0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1150 1150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

OtpErrorCode1_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1150 1150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

OtpErrorCode2_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1150 1150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

OtpErrorCode3_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1150 1150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

OtpErrorCode4_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1150 1150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

OtpIfWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1150 1150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

OtpKeymgrKeyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 472271170 0 0
T1 10539 10268 0 0
T2 8797 8711 0 0
T3 15153 14867 0 0
T4 46685 45790 0 0
T5 276043 271746 0 0
T6 417024 411962 0 0
T7 9956 9720 0 0
T10 108168 107950 0 0
T11 12051 11890 0 0
T12 99707 98887 0 0

OtpLcDataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 472271170 0 0
T1 10539 10268 0 0
T2 8797 8711 0 0
T3 15153 14867 0 0
T4 46685 45790 0 0
T5 276043 271746 0 0
T6 417024 411962 0 0
T7 9956 9720 0 0
T10 108168 107950 0 0
T11 12051 11890 0 0
T12 99707 98887 0 0

OtpOtgnKeyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 472271170 0 0
T1 10539 10268 0 0
T2 8797 8711 0 0
T3 15153 14867 0 0
T4 46685 45790 0 0
T5 276043 271746 0 0
T6 417024 411962 0 0
T7 9956 9720 0 0
T10 108168 107950 0 0
T11 12051 11890 0 0
T12 99707 98887 0 0

OtpRespFifoUnderflow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 1518652 0 0
T1 10539 159 0 0
T2 8797 55 0 0
T3 15153 173 0 0
T4 46685 1054 0 0
T5 276043 7518 0 0
T6 417024 10526 0 0
T7 9956 191 0 0
T10 108168 182 0 0
T11 12051 163 0 0
T12 99707 1062 0 0

OtpSramKeyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 472271170 0 0
T1 10539 10268 0 0
T2 8797 8711 0 0
T3 15153 14867 0 0
T4 46685 45790 0 0
T5 276043 271746 0 0
T6 417024 411962 0 0
T7 9956 9720 0 0
T10 108168 107950 0 0
T11 12051 11890 0 0
T12 99707 98887 0 0

PartSelMustBeOnehot_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 472271170 0 0
T1 10539 10268 0 0
T2 8797 8711 0 0
T3 15153 14867 0 0
T4 46685 45790 0 0
T5 276043 271746 0 0
T6 417024 411962 0 0
T7 9956 9720 0 0
T10 108168 107950 0 0
T11 12051 11890 0 0
T12 99707 98887 0 0

PrimTlOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 472271170 0 0
T1 10539 10268 0 0
T2 8797 8711 0 0
T3 15153 14867 0 0
T4 46685 45790 0 0
T5 276043 271746 0 0
T6 417024 411962 0 0
T7 9956 9720 0 0
T10 108168 107950 0 0
T11 12051 11890 0 0
T12 99707 98887 0 0

PwrOtpInitRspKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 472271170 0 0
T1 10539 10268 0 0
T2 8797 8711 0 0
T3 15153 14867 0 0
T4 46685 45790 0 0
T5 276043 271746 0 0
T6 417024 411962 0 0
T7 9956 9720 0 0
T10 108168 107950 0 0
T11 12051 11890 0 0
T12 99707 98887 0 0

RmaTokenSize_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1150 1150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

SramDataKeySeedSize_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1150 1150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

TestExitTokenSize_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1150 1150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

TestUnlockTokenSize_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1150 1150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

gen_partitions[0].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

gen_partitions[10].gen_lifecycle.FpvSecCmCntPartLcCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

gen_partitions[10].gen_lifecycle.FpvSecCmCtrlPartLcFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

gen_partitions[1].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

gen_partitions[2].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

gen_partitions[3].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

gen_partitions[4].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

gen_partitions[5].gen_buffered.FpvSecCmCntPartBufCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

gen_partitions[5].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

gen_partitions[6].gen_buffered.FpvSecCmCntPartBufCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

gen_partitions[6].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

gen_partitions[7].gen_buffered.FpvSecCmCntPartBufCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

gen_partitions[7].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

gen_partitions[8].gen_buffered.FpvSecCmCntPartBufCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

gen_partitions[8].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

gen_partitions[9].gen_buffered.FpvSecCmCntPartBufCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

gen_partitions[9].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

gen_reg_we_assert_generic.FpvSecCmPrimFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

Line Coverage for Instance : tb.dut
Line No.TotalCoveredPercent
TOTAL15415097.40
CONT_ASSIGN24711100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN24911100.00
ALWAYS2801313100.00
ALWAYS30433100.00
ALWAYS3201010100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN38211100.00
CONT_ASSIGN38611100.00
CONT_ASSIGN39011100.00
CONT_ASSIGN39111100.00
CONT_ASSIGN39911100.00
CONT_ASSIGN40011100.00
ALWAYS40355100.00
ALWAYS4301919100.00
CONT_ASSIGN48411100.00
CONT_ASSIGN49211100.00
ALWAYS49599100.00
ALWAYS5171010100.00
CONT_ASSIGN58111100.00
CONT_ASSIGN58911100.00
CONT_ASSIGN63611100.00
CONT_ASSIGN63811100.00
CONT_ASSIGN76111100.00
CONT_ASSIGN76211100.00
CONT_ASSIGN76311100.00
CONT_ASSIGN79311100.00
CONT_ASSIGN79511100.00
ALWAYS87222100.00
ALWAYS93022100.00
ALWAYS95744100.00
CONT_ASSIGN98411100.00
ALWAYS98733100.00
CONT_ASSIGN103911100.00
CONT_ASSIGN104111100.00
CONT_ASSIGN1075100.00
CONT_ASSIGN1126100.00
CONT_ASSIGN118111100.00
CONT_ASSIGN118111100.00
CONT_ASSIGN118111100.00
CONT_ASSIGN118111100.00
CONT_ASSIGN118111100.00
CONT_ASSIGN123611100.00
CONT_ASSIGN1236100.00
CONT_ASSIGN123611100.00
CONT_ASSIGN123611100.00
CONT_ASSIGN123611100.00
CONT_ASSIGN129611100.00
CONT_ASSIGN1308100.00
CONT_ASSIGN133211100.00
ALWAYS134422100.00
CONT_ASSIGN135811100.00
ALWAYS138699100.00
CONT_ASSIGN141711100.00
CONT_ASSIGN141811100.00
CONT_ASSIGN142011100.00
CONT_ASSIGN142211100.00
CONT_ASSIGN142611100.00
CONT_ASSIGN142811100.00
CONT_ASSIGN143011100.00
CONT_ASSIGN143511100.00
CONT_ASSIGN143711100.00
CONT_ASSIGN143911100.00
CONT_ASSIGN147111100.00
CONT_ASSIGN147311100.00
CONT_ASSIGN147711100.00
CONT_ASSIGN148111100.00
CONT_ASSIGN148511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
247 1 1
249 10 10
280 1 1
281 1 1
282 1 1
283 1 1
284 1 1
285 1 1
288 excluded
Exclude Annotation: VC_COV_UNR
MISSING_ELSE
293 1 1
294 1 1
295 1 1
296 1 1
297 1 1
298 1 1
299 1 1
304 1 1
305 1 1
307 1 1
320 1 1
325 1 1
326 1 1
330 1 1
331 1 1
332 1 1
333 1 1
MISSING_ELSE
MISSING_ELSE
337 1 1
338 1 1
339 1 1
340 excluded
Exclude Annotation: VC_COV_UNR
MISSING_ELSE
MISSING_ELSE
378 1 1
382 1 1
386 1 1
390 1 1
391 1 1
399 1 1
400 1 1
403 1 1
404 1 1
406 1 1
408 1 1
409 1 1
430 1 1
431 1 1
432 1 1
434 1 1
436 1 1
439 1 1
441 1 1
444 1 1
445 1 1
MISSING_ELSE
449 1 1
451 1 1
455 1 1
458 1 1
460 1 1
465 1 1
466 1 1
MISSING_ELSE
468 1 1
469 1 1
MISSING_ELSE
474 1 1
484 1 1
492 1 1
495 1 1
496 1 1
497 1 1
498 1 1
499 1 1
501 1 1
502 1 1
503 1 1
504 1 1
517 1 1
519 1 1
521 1 1
523 1 1
525 1 1
534 1 1
536 1 1
537 1 1
538 1 1
539 1 1
581 1 1
589 1 1
636 1 1
638 1 1
761 1 1
762 1 1
763 1 1
793 1 1
795 1 1
872 1 1
873 1 1
930 1 1
931 1 1
957 1 1
958 1 1
959 1 1
960 1 1
984 1 1
987 1 1
988 1 1
990 1 1
1039 1 1
1041 1 1
1075 0 1
1126 0 1
1181 5 5
1236 4 5
1296 1 1
1308 0 1
1332 1 1
1344 1 1
1345 1 1
1358 1 1
1386 1 1
1387 1 1
1388 1 1
1389 1 1
1391 1 1
1392 1 1
1393 1 1
1394 1 1
1395 1 1
1417 1 1
1418 1 1
1420 1 1
1422 1 1
1426 1 1
1428 1 1
1430 1 1
1435 1 1
1437 1 1
1439 1 1
1471 1 1
1473 1 1
1477 1 1
1481 1 1
1485 1 1


Cond Coverage for Instance : tb.dut
TotalCoveredPercent
Conditions10410096.15
Logical10410096.15
Non-Logical00
Event00

 LINE       249
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b00001000000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[1].PartEnd))
             -------------------1------------------   --------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T7
11CoveredT1,T3,T7

 LINE       249
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b00111101000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[2].PartEnd))
             -------------------1------------------   --------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T7
11CoveredT1,T7,T4

 LINE       249
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b10001111000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[3].PartEnd))
             -------------------1------------------   --------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T7
11CoveredT1,T3,T7

 LINE       249
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11001010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[4].PartEnd))
             -------------------1------------------   --------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT8,T9,T13
11CoveredT1,T3,T7

 LINE       249
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11001111000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[5].PartEnd))
             -------------------1------------------   --------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT8,T9,T13
11CoveredT8,T9,T13

 LINE       249
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011000000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[6].PartEnd))
             -------------------1------------------   --------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT8,T9,T13
11CoveredT8,T9,T13

 LINE       249
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[7].PartEnd))
             -------------------1------------------   --------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT8,T9,T13
11CoveredT8,T9,T13

 LINE       249
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011111000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[8].PartEnd))
             -------------------1------------------   --------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT8,T9,T13
11CoveredT8,T9,T13

 LINE       249
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11101010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[9].PartEnd))
             -------------------1------------------   --------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT8,T9,T13
11CoveredT8,T9,T13

 LINE       249
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11110101000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[10].PartEnd))
             -------------------1------------------   ---------------------------2--------------------------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded vcs_gen_start:k=10:vcs_gen_end:VC_COV_UNR
11CoveredT8,T9,T13

 LINE       284
 EXPRESSION (tlul_part_sel_oh != '0)
            ------------1-----------
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1CoveredT1,T3,T7

 LINE       293
 EXPRESSION (((|part_tlul_gnt)) | tlul_oob_err_q)
             ---------1--------   -------2------
-1--2-StatusTestsExclude Annotation
00CoveredT1,T2,T3
01Excluded VC_COV_UNR
10CoveredT1,T3,T7

 LINE       294
 EXPRESSION (((|part_tlul_rvalid)) | tlul_oob_err_q)
             ----------1----------   -------2------
-1--2-StatusTestsExclude Annotation
00CoveredT1,T2,T3
01Excluded VC_COV_UNR
10CoveredT1,T3,T7

 LINE       378
 EXPRESSION ((reg2hw.direct_access_regwen.qe && ((!reg2hw.direct_access_regwen.q))) ? 1'b0 : direct_access_regwen_q)
             -----------------------------------1----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       378
 SUB-EXPRESSION (reg2hw.direct_access_regwen.qe && ((!reg2hw.direct_access_regwen.q)))
                 ---------------1--------------    -----------------2----------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       382
 EXPRESSION (reg2hw.direct_access_cmd.digest.qe | reg2hw.direct_access_cmd.wr.qe | reg2hw.direct_access_cmd.rd.qe)
             -----------------1----------------   ---------------2--------------   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
000CoveredT1,T2,T3
001Excluded VC_COV_UNR
010Excluded VC_COV_UNR
100Excluded VC_COV_UNR

 LINE       399
 EXPRESSION (lci_prog_idle & dai_prog_idle)
             ------1------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T7
11CoveredT1,T2,T3

 LINE       432
 EXPRESSION (fatal_bus_integ_error_q | ((|intg_error)))
             -----------1-----------   -------2-------
-1--2-StatusTestsExclude Annotation
00CoveredT1,T2,T3
01CoveredT22,T23,T24
10Excluded VC_COV_UNR

 LINE       441
 EXPRESSION (part_error[k] == MacroError)
            --------------1--------------
-1-StatusTestsExclude Annotation
0CoveredT1,T2,T3
1Excluded VC_COV_UNR

 LINE       445
 EXPRESSION (part_error[k] == MacroEccUncorrError)
            -------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T11

 LINE       465
 EXPRESSION (fatal_macro_error_q || fatal_check_error_q)
             ---------1---------    ---------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT7,T10,T5
10CoveredT1,T3,T11

 LINE       474
 EXPRESSION (chk_timeout | lfsr_fsm_err | scrmbl_fsm_err | ((|part_fsm_err)))
             -----1-----   ------2-----   -------3------   --------4--------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001CoveredT1,T3,T7
0010CoveredT22,T23,T24
0100CoveredT22,T23,T24
1000CoveredT5,T8,T36

 LINE       523
 EXPRESSION (direct_access_regwen_q & dai_idle)
             -----------1----------   ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       589
 SUB-EXPRESSION (reg2hw.alert_test.recov_prim_otp_alert.q & reg2hw.alert_test.recov_prim_otp_alert.qe)
                 --------------------1-------------------   --------------------2--------------------
-1--2-StatusTests
01CoveredT2,T208,T179
10CoveredT1,T2,T3
11CoveredT2,T208,T179

 LINE       589
 SUB-EXPRESSION (reg2hw.alert_test.fatal_prim_otp_alert.q & reg2hw.alert_test.fatal_prim_otp_alert.qe)
                 --------------------1-------------------   --------------------2--------------------
-1--2-StatusTests
01CoveredT2,T208,T179
10CoveredT1,T2,T3
11CoveredT2,T208,T179

 LINE       589
 SUB-EXPRESSION (reg2hw.alert_test.fatal_bus_integ_error.q & reg2hw.alert_test.fatal_bus_integ_error.qe)
                 --------------------1--------------------   ---------------------2--------------------
-1--2-StatusTests
01CoveredT2,T208,T179
10CoveredT1,T2,T3
11CoveredT2,T208,T179

 LINE       589
 SUB-EXPRESSION (reg2hw.alert_test.fatal_check_error.q & reg2hw.alert_test.fatal_check_error.qe)
                 ------------------1------------------   -------------------2------------------
-1--2-StatusTests
01CoveredT2,T208,T179
10CoveredT1,T2,T3
11CoveredT2,T208,T179

 LINE       589
 SUB-EXPRESSION (reg2hw.alert_test.fatal_macro_error.q & reg2hw.alert_test.fatal_macro_error.qe)
                 ------------------1------------------   -------------------2------------------
-1--2-StatusTests
01CoveredT2,T208,T179
10CoveredT1,T2,T3
11CoveredT2,T208,T179

 LINE       636
 EXPRESSION (reg2hw.check_trigger.integrity.q & reg2hw.check_trigger.integrity.qe)
             ----------------1---------------   ----------------2----------------
-1--2-StatusTests
01CoveredT4,T10,T5
10CoveredT1,T2,T3
11CoveredT4,T10,T5

 LINE       638
 EXPRESSION (reg2hw.check_trigger.consistency.q & reg2hw.check_trigger.consistency.qe)
             -----------------1----------------   -----------------2-----------------
-1--2-StatusTests
01CoveredT4,T10,T5
10CoveredT1,T2,T3
11CoveredT4,T10,T5

 LINE       761
 EXPRESSION (otp_prim_ready & otp_rsp_fifo_ready)
             -------1------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       762
 EXPRESSION (otp_arb_valid & otp_rsp_fifo_ready)
             ------1------   ---------2--------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11CoveredT1,T2,T3

 LINE       763
 EXPRESSION (otp_prim_ready & otp_prim_valid)
             -------1------   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       873
 EXPRESSION (otp_rvalid & otp_fifo_valid)
             -----1----   -------2------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11CoveredT1,T2,T3

 LINE       1417
 EXPRESSION (part_digest[Secret1Idx] != '0)
            ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       1435
 EXPRESSION ((part_digest[Secret0Idx] != '0) ? On : Off)
             ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T4,T5

 LINE       1435
 SUB-EXPRESSION (part_digest[Secret0Idx] != '0)
                ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T4,T5

 LINE       1437
 EXPRESSION ((part_digest[Secret2Idx] != '0) ? On : Off)
             ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T36

 LINE       1437
 SUB-EXPRESSION (part_digest[Secret2Idx] != '0)
                ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T36

 LINE       1439
 EXPRESSION ((part_digest[Secret2Idx] != '0) ? On : Off)
             ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T36

 LINE       1439
 SUB-EXPRESSION (part_digest[Secret2Idx] != '0)
                ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T36

Toggle Coverage for Instance : tb.dut
TotalCoveredPercent
Totals 149 142 95.30
Total Bits 9984 9696 97.12
Total Bits 0->1 4992 4848 97.12
Total Bits 1->0 4992 4848 97.12

Ports 149 142 95.30
Port Bits 9984 9696 97.12
Port Bits 0->1 4992 4848 97.12
Port Bits 1->0 4992 4848 97.12

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T3,T7 Yes T1,T2,T3 INPUT
clk_edn_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_edn_ni Yes Yes T1,T3,T7 Yes T1,T2,T3 INPUT
edn_o.edn_req Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_i.edn_bus[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
edn_i.edn_fips Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
edn_i.edn_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
core_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_user.instr_type[3:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
core_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
core_tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_address[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
core_tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
core_tl_o.d_error Yes Yes T4,T10,T5 Yes T4,T10,T5 OUTPUT
core_tl_o.d_user.data_intg[6:0] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
core_tl_o.d_user.rsp_intg[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
core_tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
core_tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T3,T7 OUTPUT
core_tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
core_tl_o.d_source[7:0] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
core_tl_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
core_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
core_tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
core_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
core_tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
prim_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
prim_tl_i.a_user.data_intg[6:0] Yes Yes T3,T4,T10 Yes T3,T4,T10 INPUT
prim_tl_i.a_user.cmd_intg[6:0] Yes Yes T3,T7,T4 Yes T3,T7,T4 INPUT
prim_tl_i.a_user.instr_type[3:0] Yes Yes T3,T7,T11 Yes T3,T7,T11 INPUT
prim_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
prim_tl_i.a_data[31:0] Yes Yes T3,T7,T4 Yes T7,T4,T10 INPUT
prim_tl_i.a_mask[3:0] Yes Yes T3,T7,T11 Yes T3,T7,T11 INPUT
prim_tl_i.a_address[31:0] Yes Yes T3,T11,T5 Yes T3,T7,T5 INPUT
prim_tl_i.a_source[7:0] Yes Yes T3,T7,T4 Yes T7,T4,T10 INPUT
prim_tl_i.a_size[1:0] Yes Yes T3,T7,T11 Yes T3,T7,T5 INPUT
prim_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
prim_tl_i.a_opcode[2:0] Yes Yes T3,T7,T4 Yes T3,T4,T10 INPUT
prim_tl_i.a_valid Yes Yes T4,T10,T5 Yes T4,T10,T5 INPUT
prim_tl_o.a_ready Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
prim_tl_o.d_error Yes Yes T2,T5,T6 Yes T5,T6,T8 OUTPUT
prim_tl_o.d_user.data_intg[6:0] Yes Yes T6,T15,T13 Yes T6,T15,T13 OUTPUT
prim_tl_o.d_user.rsp_intg[5:0] Yes Yes *T4,*T10,*T5 Yes T4,T10,T5 OUTPUT
prim_tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
prim_tl_o.d_data[31:0] Yes Yes T2,T5,T6 Yes T5,T6,T8 OUTPUT
prim_tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
prim_tl_o.d_source[7:0] Yes Yes T4,T10,T5 Yes T4,T10,T5 OUTPUT
prim_tl_o.d_size[1:0] Yes Yes T8,T9,T13 Yes T8,T9,T13 OUTPUT
prim_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
prim_tl_o.d_opcode[0] Yes Yes *T2,*T4,*T10 Yes T4,T10,T5 OUTPUT
prim_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
prim_tl_o.d_valid Yes Yes T4,T10,T5 Yes T4,T10,T5 OUTPUT
intr_otp_operation_done_o Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
intr_otp_error_o Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[2].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[2].ack_p Yes Yes T2,T208,T22 Yes T2,T208,T22 INPUT
alert_rx_i[2].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[2].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[3].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[3].ack_p Yes Yes T2,T208,T22 Yes T2,T208,T22 INPUT
alert_rx_i[3].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[3].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[4].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[4].ack_p Yes Yes T2,T208,T179 Yes T2,T208,T179 INPUT
alert_rx_i[4].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[4].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[2].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[2].alert_p Yes Yes T2,T208,T22 Yes T2,T208,T22 OUTPUT
alert_tx_o[3].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[3].alert_p Yes Yes T2,T208,T22 Yes T2,T208,T22 OUTPUT
alert_tx_o[4].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[4].alert_p Yes Yes T2,T208,T179 Yes T2,T208,T179 OUTPUT
obs_ctrl_i.obmen[3:0] No No No INPUT
obs_ctrl_i.obmsl[3:0] No No No INPUT
obs_ctrl_i.obgsl[3:0] No No No INPUT
otp_obs_o[7:0] Unreachable Unreachable Unreachable OUTPUT
otp_ast_pwr_seq_o.pwr_seq[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
otp_ast_pwr_seq_h_i.pwr_seq_h[1:0] Yes Yes T1,T4,T10 Yes T3,T4,T5 INPUT
pwr_otp_i.otp_init Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
pwr_otp_o.otp_idle Yes Yes T1,T3,T7 Yes T1,T2,T3 OUTPUT
pwr_otp_o.otp_done Yes Yes T1,T3,T7 Yes T1,T2,T3 OUTPUT
lc_otp_vendor_test_i.ctrl[31:0] No No No INPUT
lc_otp_vendor_test_o.status[31:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
lc_otp_program_i.count[383:0] Yes Yes T6,T8,T110 Yes T6,T16,T241 INPUT
lc_otp_program_i.state[319:0] Yes Yes T6,T8,T9 Yes T6,T9,T16 INPUT
lc_otp_program_i.req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
lc_otp_program_o.ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
lc_otp_program_o.err Yes Yes T110,T9,T113 Yes T110,T9,T113 OUTPUT
lc_creator_seed_sw_rw_en_i[3:0] Yes Yes T4,T10,T5 Yes T4,T10,T5 INPUT
lc_owner_seed_sw_rw_en_i[3:0] Yes Yes T4,T10,T5 Yes T4,T5,T6 INPUT
lc_seed_hw_rd_en_i[3:0] Yes Yes T4,T5,T6 Yes T3,T4,T11 INPUT
lc_dft_en_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T4 INPUT
lc_escalate_en_i[3:0] Yes Yes T10,T6,T109 Yes T10,T6,T109 INPUT
lc_check_byp_en_i[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
otp_lc_data_o.rma_token[127:0] Yes Yes T1,T3,T7 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.rma_token_valid[3:0] Yes Yes T5,T6,T36 Yes T5,T6,T36 OUTPUT
otp_lc_data_o.test_exit_token[127:0] Yes Yes T5,T6,T119 Yes T5,T6,T119 OUTPUT
otp_lc_data_o.test_unlock_token[127:0] Yes Yes T1,T2,T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.test_tokens_valid[3:0] Yes Yes T7,T5,T6 Yes T7,T4,T5 OUTPUT
otp_lc_data_o.secrets_valid[3:0] Yes Yes T5,T6,T36 Yes T5,T6,T36 OUTPUT
otp_lc_data_o.count[0] No No No OUTPUT
otp_lc_data_o.count[8:1] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.count[9] No No No OUTPUT
otp_lc_data_o.count[14:10] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.count[16:15] No No No OUTPUT
otp_lc_data_o.count[31:17] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.count[32] No No No OUTPUT
otp_lc_data_o.count[46:33] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.count[47] No No No OUTPUT
otp_lc_data_o.count[61:48] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.count[64:62] No No No OUTPUT
otp_lc_data_o.count[76:65] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.count[77] No No No OUTPUT
otp_lc_data_o.count[78] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.count[79] No No No OUTPUT
otp_lc_data_o.count[84:80] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.count[86:85] No No No OUTPUT
otp_lc_data_o.count[88:87] Yes Yes T1,T2,T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.count[89] No No No OUTPUT
otp_lc_data_o.count[101:90] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.count[102] No No No OUTPUT
otp_lc_data_o.count[105:103] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.count[106] No No No OUTPUT
otp_lc_data_o.count[115:107] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.count[116] No No No OUTPUT
otp_lc_data_o.count[118:117] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.count[119] No No No OUTPUT
otp_lc_data_o.count[121:120] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.count[122] No No No OUTPUT
otp_lc_data_o.count[124:123] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.count[125] No No No OUTPUT
otp_lc_data_o.count[134:126] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.count[135] No No No OUTPUT
otp_lc_data_o.count[155:136] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.count[156] No No No OUTPUT
otp_lc_data_o.count[164:157] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.count[166:165] No No No OUTPUT
otp_lc_data_o.count[174:167] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.count[176:175] No No No OUTPUT
otp_lc_data_o.count[185:177] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.count[187:186] No No No OUTPUT
otp_lc_data_o.count[191:188] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.count[192] No No No OUTPUT
otp_lc_data_o.count[193] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.count[194] No No No OUTPUT
otp_lc_data_o.count[202:195] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.count[203] No No No OUTPUT
otp_lc_data_o.count[207:204] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.count[208] No No No OUTPUT
otp_lc_data_o.count[218:209] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.count[219] No No No OUTPUT
otp_lc_data_o.count[225:220] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.count[226] No No No OUTPUT
otp_lc_data_o.count[237:227] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.count[238] No No No OUTPUT
otp_lc_data_o.count[251:239] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.count[252] No No No OUTPUT
otp_lc_data_o.count[272:253] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.count[273] No No No OUTPUT
otp_lc_data_o.count[274] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.count[275] No No No OUTPUT
otp_lc_data_o.count[302:276] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.count[304:303] No No No OUTPUT
otp_lc_data_o.count[309:305] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.count[310] No No No OUTPUT
otp_lc_data_o.count[312:311] Yes Yes T1,T2,T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.count[313] No No No OUTPUT
otp_lc_data_o.count[316:314] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.count[317] No No No OUTPUT
otp_lc_data_o.count[324:318] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.count[325] No No No OUTPUT
otp_lc_data_o.count[327:326] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.count[328] No No No OUTPUT
otp_lc_data_o.count[336:329] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.count[337] No No No OUTPUT
otp_lc_data_o.count[338] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.count[339] No No No OUTPUT
otp_lc_data_o.count[343:340] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.count[344] No No No OUTPUT
otp_lc_data_o.count[364:345] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.count[366:365] No No No OUTPUT
otp_lc_data_o.count[375:367] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.count[376] No No No OUTPUT
otp_lc_data_o.count[383:377] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.state[5:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.state[6] No No No OUTPUT
otp_lc_data_o.state[12:7] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.state[13] No No No OUTPUT
otp_lc_data_o.state[14] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.state[16:15] No No No OUTPUT
otp_lc_data_o.state[17] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.state[19:18] No No No OUTPUT
otp_lc_data_o.state[34:20] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.state[36:35] No No No OUTPUT
otp_lc_data_o.state[42:37] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.state[43] No No No OUTPUT
otp_lc_data_o.state[50:44] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.state[52:51] No No No OUTPUT
otp_lc_data_o.state[59:53] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.state[60] No No No OUTPUT
otp_lc_data_o.state[61] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.state[62] No No No OUTPUT
otp_lc_data_o.state[68:63] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.state[69] No No No OUTPUT
otp_lc_data_o.state[75:70] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.state[76] No No No OUTPUT
otp_lc_data_o.state[79:77] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.state[80] No No No OUTPUT
otp_lc_data_o.state[84:81] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.state[85] No No No OUTPUT
otp_lc_data_o.state[95:86] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.state[96] No No No OUTPUT
otp_lc_data_o.state[98:97] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.state[99] No No No OUTPUT
otp_lc_data_o.state[103:100] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.state[104] No No No OUTPUT
otp_lc_data_o.state[105] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.state[107:106] No No No OUTPUT
otp_lc_data_o.state[113:108] Yes Yes T1,T2,T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.state[114] No No No OUTPUT
otp_lc_data_o.state[121:115] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.state[122] No No No OUTPUT
otp_lc_data_o.state[123] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.state[124] No No No OUTPUT
otp_lc_data_o.state[136:125] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.state[137] No No No OUTPUT
otp_lc_data_o.state[145:138] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.state[147:146] No No No OUTPUT
otp_lc_data_o.state[151:148] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.state[152] No No No OUTPUT
otp_lc_data_o.state[157:153] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.state[158] No No No OUTPUT
otp_lc_data_o.state[160:159] Yes Yes T1,T2,T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.state[161] No No No OUTPUT
otp_lc_data_o.state[163:162] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.state[164] No No No OUTPUT
otp_lc_data_o.state[165] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.state[166] No No No OUTPUT
otp_lc_data_o.state[180:167] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.state[181] No No No OUTPUT
otp_lc_data_o.state[186:182] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.state[187] No No No OUTPUT
otp_lc_data_o.state[206:188] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.state[207] No No No OUTPUT
otp_lc_data_o.state[210:208] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.state[211] No No No OUTPUT
otp_lc_data_o.state[226:212] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.state[227] No No No OUTPUT
otp_lc_data_o.state[230:228] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.state[231] No No No OUTPUT
otp_lc_data_o.state[234:232] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.state[236:235] No No No OUTPUT
otp_lc_data_o.state[246:237] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.state[247] No No No OUTPUT
otp_lc_data_o.state[263:248] Yes Yes *T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.state[264] No No No OUTPUT
otp_lc_data_o.state[273:265] Yes Yes *T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.state[274] No No No OUTPUT
otp_lc_data_o.state[278:275] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_lc_data_o.state[279] No No No OUTPUT
otp_lc_data_o.state[285:280] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.state[286] No No No OUTPUT
otp_lc_data_o.state[301:287] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.state[302] No No No OUTPUT
otp_lc_data_o.state[311:303] Yes Yes *T1,*T2,*T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.state[312] No No No OUTPUT
otp_lc_data_o.state[319:313] Yes Yes T1,T2,T3 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.error Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
otp_lc_data_o.valid Yes Yes T1,T3,T7 Yes T1,T2,T3 OUTPUT
otp_keymgr_key_o.owner_seed_valid Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
otp_keymgr_key_o.owner_seed[255:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
otp_keymgr_key_o.creator_seed_valid Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
otp_keymgr_key_o.creator_seed[255:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
otp_keymgr_key_o.creator_root_key_share1_valid Yes Yes T5,T6,T36 Yes T5,T6,T36 OUTPUT
otp_keymgr_key_o.creator_root_key_share1[255:0] Yes Yes T5,T12,T103 Yes T5,T103,T242 OUTPUT
otp_keymgr_key_o.creator_root_key_share0_valid Yes Yes T5,T6,T36 Yes T5,T6,T36 OUTPUT
otp_keymgr_key_o.creator_root_key_share0[255:0] Yes Yes T6,T103,T237 Yes T6,T103,T237 OUTPUT
flash_otp_key_i.addr_req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
flash_otp_key_i.data_req Yes Yes T4,T10,T5 Yes T4,T10,T5 INPUT
flash_otp_key_o.seed_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
flash_otp_key_o.rand_key[127:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
flash_otp_key_o.key[127:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
flash_otp_key_o.addr_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
flash_otp_key_o.data_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
sram_otp_key_i[0].req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sram_otp_key_i[1].req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sram_otp_key_i[2].req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sram_otp_key_i[3].req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sram_otp_key_o[0].seed_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
sram_otp_key_o[0].nonce[127:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
sram_otp_key_o[0].key[127:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
sram_otp_key_o[0].ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
sram_otp_key_o[1].seed_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
sram_otp_key_o[1].nonce[127:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
sram_otp_key_o[1].key[127:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
sram_otp_key_o[1].ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
sram_otp_key_o[2].seed_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
sram_otp_key_o[2].nonce[127:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
sram_otp_key_o[2].key[127:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
sram_otp_key_o[2].ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
sram_otp_key_o[3].seed_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
sram_otp_key_o[3].nonce[127:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
sram_otp_key_o[3].key[127:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
sram_otp_key_o[3].ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otbn_otp_key_i.req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
otbn_otp_key_o.seed_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otbn_otp_key_o.nonce[63:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otbn_otp_key_o.key[127:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otbn_otp_key_o.ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_broadcast_o.hw_cfg0_data.device_id[255:0] Yes Yes T1,T2,T3 Yes T1,T3,T7 OUTPUT
otp_broadcast_o.hw_cfg0_data.manuf_state[255:0] Yes Yes T1,T2,T3 Yes T1,T3,T7 OUTPUT
otp_broadcast_o.hw_cfg0_data.hw_cfg0_digest[63:0] Yes Yes T5,T6,T12 Yes T5,T6,T12 OUTPUT
otp_broadcast_o.hw_cfg1_data.en_sram_ifetch[7:0] Yes Yes T1,T2,T3 Yes T1,T3,T7 OUTPUT
otp_broadcast_o.hw_cfg1_data.en_csrng_sw_app_read[7:0] Yes Yes T1,T2,T3 Yes T1,T3,T7 OUTPUT
otp_broadcast_o.hw_cfg1_data.dis_rv_dm_late_debug[7:0] Yes Yes T1,T2,T3 Yes T1,T3,T7 OUTPUT
otp_broadcast_o.hw_cfg1_data.unallocated[39:0] Yes Yes T6,T55,T56 Yes T6,T55,T56 OUTPUT
otp_broadcast_o.hw_cfg1_data.hw_cfg1_digest[63:0] Yes Yes T1,T2,T3 Yes T1,T3,T7 OUTPUT
otp_broadcast_o.valid[3:0] Yes Yes T1,T3,T7 Yes T1,T2,T3 OUTPUT
otp_ext_voltage_h_io No No No INOUT
scan_en_i Yes Yes T4,T5,T6 Yes T3,T4,T5 INPUT
scan_rst_ni Yes Yes T4,T5,T6 Yes T1,T7,T4 INPUT
scanmode_i[3:0] Yes Yes T4,T10,T5 Yes T3,T4,T11 INPUT
cio_test_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
cio_test_en_o[7:0] Yes Yes T5,T6,T8 Yes T2,T5,T6 OUTPUT

*Tests covering at least one bit in the range

Branch Coverage for Instance : tb.dut
Line No.TotalCoveredPercent
Branches 28 27 96.43
TERNARY 378 2 1 50.00
TERNARY 1435 2 2 100.00
TERNARY 1437 2 2 100.00
TERNARY 1439 2 2 100.00
IF 283 2 2 100.00
IF 304 2 2 100.00
IF 330 2 2 100.00
IF 337 2 2 100.00
IF 403 2 2 100.00
IF 444 2 2 100.00
IF 465 2 2 100.00
IF 468 2 2 100.00
IF 495 2 2 100.00
IF 987 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 378 ((reg2hw.direct_access_regwen.qe && (!reg2hw.direct_access_regwen.q))) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 1435 ((part_digest[Secret0Idx] != '0)) ?

Branches:
-1-StatusTests
1 Covered T7,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 1437 ((part_digest[Secret2Idx] != '0)) ?

Branches:
-1-StatusTests
1 Covered T5,T6,T36
0 Covered T1,T2,T3


LineNo. Expression -1-: 1439 ((part_digest[Secret2Idx] != '0)) ?

Branches:
-1-StatusTests
1 Covered T5,T6,T36
0 Covered T1,T2,T3


LineNo. Expression -1-: 283 if (tlul_req) -2-: 284 if ((tlul_part_sel_oh != '0))

Branches:
-1--2-StatusTestsExclude Annotation
1 1 Covered T1,T3,T7
1 0 Excluded VC_COV_UNR
0 - Covered T1,T2,T3


LineNo. Expression -1-: 304 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 330 if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_creator_seed_sw_rw_en))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 337 if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_owner_seed_sw_rw_en))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 403 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 444 if (otp_ctrl_part_pkg::PartInfo[k].integrity)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 465 if ((fatal_macro_error_q || fatal_check_error_q))

Branches:
-1-StatusTests
1 Covered T1,T3,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 468 if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_escalate_en[k]))

Branches:
-1-StatusTests
1 Covered T1,T3,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 495 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 987 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 71 71 100.00 69 97.18
Cover properties 0 0 0
Cover sequences 0 0 0
Total 71 71 100.00 69 97.18




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertTxKnown_A 473145275 472271170 0 0
CoreTlOutKnown_A 473145275 472271170 0 0
CreatorRootKeyShare0Size_A 1150 1150 0 0
CreatorRootKeyShare1Size_A 1150 1150 0 0
ErrorCodeWidth_A 1150 1150 0 0
FlashAddrKeySeedSize_A 1150 1150 0 0
FlashDataKeySeedSize_A 1150 1150 0 0
FlashOtpKeyRspKnown_A 473145275 472271170 0 0
FpvSecCmCntCnstyCheck_A 473145275 50 0 0
FpvSecCmCntDaiCheck_A 473145275 50 0 0
FpvSecCmCntIntegCheck_A 473145275 50 0 0
FpvSecCmCntKdiEntropyCheck_A 473145275 50 0 0
FpvSecCmCntKdiSeedCheck_A 473145275 50 0 0
FpvSecCmCntLciCheck_A 473145275 50 0 0
FpvSecCmCntScrmblCheck_A 473145275 50 0 0
FpvSecCmCtrlDaiFsmCheck_A 473145275 50 0 0
FpvSecCmCtrlKdiFsmCheck_A 473145275 50 0 0
FpvSecCmCtrlLciFsmCheck_A 473145275 50 0 0
FpvSecCmCtrlLfsrTimerFsmCheck_A 473145275 50 0 0
FpvSecCmCtrlScrambleFsmCheck_A 473145275 50 0 0
FpvSecCmDoubleLfsrCheck_A 473145275 50 0 0
FpvSecCmRegWeOnehotCheck_A 473145275 50 0 0
FpvSecCmTlLcGateFsm_A 473145275 50 0 0
IntrOtpErrorKnown_A 473145275 472271170 0 0
IntrOtpOperationDoneKnown_A 473145275 472271170 0 0
LcOtpProgramRspKnown_A 473145275 472271170 0 0
LcSeedHwRdEnStable0_A 473145275 2323 0 0
LcSeedHwRdEnStable1_A 473145275 2323 0 0
LcSeedHwRdEnStable2_A 473145275 0 0 0
LcSeedHwRdEnStable3_A 473145275 0 0 0
LcStateSize_A 1150 1150 0 0
LcTransitionCntSize_A 1150 1150 0 0
OtpAstPwrSeqKnown_A 473145275 472271170 0 0
OtpBroadcastKnown_A 473145275 472271170 0 0
OtpErrorCode0_A 1150 1150 0 0
OtpErrorCode1_A 1150 1150 0 0
OtpErrorCode2_A 1150 1150 0 0
OtpErrorCode3_A 1150 1150 0 0
OtpErrorCode4_A 1150 1150 0 0
OtpIfWidth_A 1150 1150 0 0
OtpKeymgrKeyKnown_A 473145275 472271170 0 0
OtpLcDataKnown_A 473145275 472271170 0 0
OtpOtgnKeyKnown_A 473145275 472271170 0 0
OtpRespFifoUnderflow_A 473145275 1518652 0 0
OtpSramKeyKnown_A 473145275 472271170 0 0
PartSelMustBeOnehot_A 473145275 472271170 0 0
PrimTlOutKnown_A 473145275 472271170 0 0
PwrOtpInitRspKnown_A 473145275 472271170 0 0
RmaTokenSize_A 1150 1150 0 0
SramDataKeySeedSize_A 1150 1150 0 0
TestExitTokenSize_A 1150 1150 0 0
TestUnlockTokenSize_A 1150 1150 0 0
gen_partitions[0].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A 473145275 50 0 0
gen_partitions[10].gen_lifecycle.FpvSecCmCntPartLcCheck_A 473145275 50 0 0
gen_partitions[10].gen_lifecycle.FpvSecCmCtrlPartLcFsmCheck_A 473145275 50 0 0
gen_partitions[1].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A 473145275 50 0 0
gen_partitions[2].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A 473145275 50 0 0
gen_partitions[3].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A 473145275 50 0 0
gen_partitions[4].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A 473145275 50 0 0
gen_partitions[5].gen_buffered.FpvSecCmCntPartBufCheck_A 473145275 50 0 0
gen_partitions[5].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A 473145275 50 0 0
gen_partitions[6].gen_buffered.FpvSecCmCntPartBufCheck_A 473145275 50 0 0
gen_partitions[6].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A 473145275 50 0 0
gen_partitions[7].gen_buffered.FpvSecCmCntPartBufCheck_A 473145275 50 0 0
gen_partitions[7].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A 473145275 50 0 0
gen_partitions[8].gen_buffered.FpvSecCmCntPartBufCheck_A 473145275 50 0 0
gen_partitions[8].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A 473145275 50 0 0
gen_partitions[9].gen_buffered.FpvSecCmCntPartBufCheck_A 473145275 50 0 0
gen_partitions[9].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A 473145275 50 0 0
gen_reg_we_assert_generic.FpvSecCmPrimFsmCheck_A 473145275 50 0 0
gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A 473145275 50 0 0


AlertTxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 472271170 0 0
T1 10539 10268 0 0
T2 8797 8711 0 0
T3 15153 14867 0 0
T4 46685 45790 0 0
T5 276043 271746 0 0
T6 417024 411962 0 0
T7 9956 9720 0 0
T10 108168 107950 0 0
T11 12051 11890 0 0
T12 99707 98887 0 0

CoreTlOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 472271170 0 0
T1 10539 10268 0 0
T2 8797 8711 0 0
T3 15153 14867 0 0
T4 46685 45790 0 0
T5 276043 271746 0 0
T6 417024 411962 0 0
T7 9956 9720 0 0
T10 108168 107950 0 0
T11 12051 11890 0 0
T12 99707 98887 0 0

CreatorRootKeyShare0Size_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1150 1150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

CreatorRootKeyShare1Size_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1150 1150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

ErrorCodeWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1150 1150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

FlashAddrKeySeedSize_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1150 1150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

FlashDataKeySeedSize_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1150 1150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

FlashOtpKeyRspKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 472271170 0 0
T1 10539 10268 0 0
T2 8797 8711 0 0
T3 15153 14867 0 0
T4 46685 45790 0 0
T5 276043 271746 0 0
T6 417024 411962 0 0
T7 9956 9720 0 0
T10 108168 107950 0 0
T11 12051 11890 0 0
T12 99707 98887 0 0

FpvSecCmCntCnstyCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

FpvSecCmCntDaiCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

FpvSecCmCntIntegCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

FpvSecCmCntKdiEntropyCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

FpvSecCmCntKdiSeedCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

FpvSecCmCntLciCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

FpvSecCmCntScrmblCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

FpvSecCmCtrlDaiFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

FpvSecCmCtrlKdiFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

FpvSecCmCtrlLciFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

FpvSecCmCtrlLfsrTimerFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

FpvSecCmCtrlScrambleFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

FpvSecCmDoubleLfsrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

FpvSecCmTlLcGateFsm_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

IntrOtpErrorKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 472271170 0 0
T1 10539 10268 0 0
T2 8797 8711 0 0
T3 15153 14867 0 0
T4 46685 45790 0 0
T5 276043 271746 0 0
T6 417024 411962 0 0
T7 9956 9720 0 0
T10 108168 107950 0 0
T11 12051 11890 0 0
T12 99707 98887 0 0

IntrOtpOperationDoneKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 472271170 0 0
T1 10539 10268 0 0
T2 8797 8711 0 0
T3 15153 14867 0 0
T4 46685 45790 0 0
T5 276043 271746 0 0
T6 417024 411962 0 0
T7 9956 9720 0 0
T10 108168 107950 0 0
T11 12051 11890 0 0
T12 99707 98887 0 0

LcOtpProgramRspKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 472271170 0 0
T1 10539 10268 0 0
T2 8797 8711 0 0
T3 15153 14867 0 0
T4 46685 45790 0 0
T5 276043 271746 0 0
T6 417024 411962 0 0
T7 9956 9720 0 0
T10 108168 107950 0 0
T11 12051 11890 0 0
T12 99707 98887 0 0

LcSeedHwRdEnStable0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 2323 0 0
T5 276043 19 0 0
T6 417024 18 0 0
T8 104294 0 0 0
T12 99707 0 0 0
T36 62070 7 0 0
T101 0 12 0 0
T102 0 2 0 0
T108 101822 0 0 0
T109 14593 0 0 0
T110 20566 0 0 0
T111 36286 0 0 0
T112 63940 0 0 0
T115 0 1 0 0
T117 0 2 0 0
T118 0 1 0 0
T119 0 2 0 0
T121 0 1 0 0

LcSeedHwRdEnStable1_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 2323 0 0
T5 276043 19 0 0
T6 417024 18 0 0
T8 104294 0 0 0
T12 99707 0 0 0
T36 62070 7 0 0
T101 0 12 0 0
T102 0 2 0 0
T108 101822 0 0 0
T109 14593 0 0 0
T110 20566 0 0 0
T111 36286 0 0 0
T112 63940 0 0 0
T115 0 1 0 0
T117 0 2 0 0
T118 0 1 0 0
T119 0 2 0 0
T121 0 1 0 0

LcSeedHwRdEnStable2_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 0 0 0

LcSeedHwRdEnStable3_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 0 0 0

LcStateSize_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1150 1150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

LcTransitionCntSize_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1150 1150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

OtpAstPwrSeqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 472271170 0 0
T1 10539 10268 0 0
T2 8797 8711 0 0
T3 15153 14867 0 0
T4 46685 45790 0 0
T5 276043 271746 0 0
T6 417024 411962 0 0
T7 9956 9720 0 0
T10 108168 107950 0 0
T11 12051 11890 0 0
T12 99707 98887 0 0

OtpBroadcastKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 472271170 0 0
T1 10539 10268 0 0
T2 8797 8711 0 0
T3 15153 14867 0 0
T4 46685 45790 0 0
T5 276043 271746 0 0
T6 417024 411962 0 0
T7 9956 9720 0 0
T10 108168 107950 0 0
T11 12051 11890 0 0
T12 99707 98887 0 0

OtpErrorCode0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1150 1150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

OtpErrorCode1_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1150 1150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

OtpErrorCode2_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1150 1150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

OtpErrorCode3_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1150 1150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

OtpErrorCode4_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1150 1150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

OtpIfWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1150 1150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

OtpKeymgrKeyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 472271170 0 0
T1 10539 10268 0 0
T2 8797 8711 0 0
T3 15153 14867 0 0
T4 46685 45790 0 0
T5 276043 271746 0 0
T6 417024 411962 0 0
T7 9956 9720 0 0
T10 108168 107950 0 0
T11 12051 11890 0 0
T12 99707 98887 0 0

OtpLcDataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 472271170 0 0
T1 10539 10268 0 0
T2 8797 8711 0 0
T3 15153 14867 0 0
T4 46685 45790 0 0
T5 276043 271746 0 0
T6 417024 411962 0 0
T7 9956 9720 0 0
T10 108168 107950 0 0
T11 12051 11890 0 0
T12 99707 98887 0 0

OtpOtgnKeyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 472271170 0 0
T1 10539 10268 0 0
T2 8797 8711 0 0
T3 15153 14867 0 0
T4 46685 45790 0 0
T5 276043 271746 0 0
T6 417024 411962 0 0
T7 9956 9720 0 0
T10 108168 107950 0 0
T11 12051 11890 0 0
T12 99707 98887 0 0

OtpRespFifoUnderflow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 1518652 0 0
T1 10539 159 0 0
T2 8797 55 0 0
T3 15153 173 0 0
T4 46685 1054 0 0
T5 276043 7518 0 0
T6 417024 10526 0 0
T7 9956 191 0 0
T10 108168 182 0 0
T11 12051 163 0 0
T12 99707 1062 0 0

OtpSramKeyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 472271170 0 0
T1 10539 10268 0 0
T2 8797 8711 0 0
T3 15153 14867 0 0
T4 46685 45790 0 0
T5 276043 271746 0 0
T6 417024 411962 0 0
T7 9956 9720 0 0
T10 108168 107950 0 0
T11 12051 11890 0 0
T12 99707 98887 0 0

PartSelMustBeOnehot_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 472271170 0 0
T1 10539 10268 0 0
T2 8797 8711 0 0
T3 15153 14867 0 0
T4 46685 45790 0 0
T5 276043 271746 0 0
T6 417024 411962 0 0
T7 9956 9720 0 0
T10 108168 107950 0 0
T11 12051 11890 0 0
T12 99707 98887 0 0

PrimTlOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 472271170 0 0
T1 10539 10268 0 0
T2 8797 8711 0 0
T3 15153 14867 0 0
T4 46685 45790 0 0
T5 276043 271746 0 0
T6 417024 411962 0 0
T7 9956 9720 0 0
T10 108168 107950 0 0
T11 12051 11890 0 0
T12 99707 98887 0 0

PwrOtpInitRspKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 472271170 0 0
T1 10539 10268 0 0
T2 8797 8711 0 0
T3 15153 14867 0 0
T4 46685 45790 0 0
T5 276043 271746 0 0
T6 417024 411962 0 0
T7 9956 9720 0 0
T10 108168 107950 0 0
T11 12051 11890 0 0
T12 99707 98887 0 0

RmaTokenSize_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1150 1150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

SramDataKeySeedSize_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1150 1150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

TestExitTokenSize_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1150 1150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

TestUnlockTokenSize_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1150 1150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

gen_partitions[0].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

gen_partitions[10].gen_lifecycle.FpvSecCmCntPartLcCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

gen_partitions[10].gen_lifecycle.FpvSecCmCtrlPartLcFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

gen_partitions[1].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

gen_partitions[2].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

gen_partitions[3].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

gen_partitions[4].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

gen_partitions[5].gen_buffered.FpvSecCmCntPartBufCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

gen_partitions[5].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

gen_partitions[6].gen_buffered.FpvSecCmCntPartBufCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

gen_partitions[6].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

gen_partitions[7].gen_buffered.FpvSecCmCntPartBufCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

gen_partitions[7].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

gen_partitions[8].gen_buffered.FpvSecCmCntPartBufCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

gen_partitions[8].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

gen_partitions[9].gen_buffered.FpvSecCmCntPartBufCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

gen_partitions[9].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

gen_reg_we_assert_generic.FpvSecCmPrimFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 473145275 50 0 0
T22 101681 10 0 0
T23 0 10 0 0
T24 0 10 0 0
T47 15042 0 0 0
T74 8855 0 0 0
T104 91498 0 0 0
T105 95116 0 0 0
T106 68231 0 0 0
T107 318619 0 0 0
T165 108455 0 0 0
T179 6590 0 0 0
T180 38310 0 0 0
T243 0 10 0 0
T244 0 10 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%