Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.84	97.40	96.15	97.04		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	465478317	7776869	0	0
check_regwen_rd_A	465478317	3330	0	0
check_timeout_rd_A	465478317	2932	0	0
check_trigger_regwen_rd_A	465478317	3689	0	0
consistency_check_period_rd_A	465478317	3682	0	0
creator_sw_cfg_read_lock_rd_A	465478317	2939	0	0
direct_access_address_rd_A	465478317	1885	0	0
direct_access_wdata_0_rd_A	465478317	1087	0	0
direct_access_wdata_1_rd_A	465478317	1416	0	0
integrity_check_period_rd_A	465478317	3526	0	0
intr_enable_rd_A	465478317	4461	0	0
owner_sw_cfg_read_lock_rd_A	465478317	2771	0	0
rot_creator_auth_codesign_read_lock_rd_A	465478317	2923	0	0
rot_creator_auth_state_read_lock_rd_A	465478317	2827	0	0
vendor_test_read_lock_rd_A	465478317	2997	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465478317	7776869	0	0
T6	439034	75947	0	0
T7	905990	234731	0	0
T13	208173	42549	0	0
T14	697889	0	0	0
T15	4928	0	0	0
T16	0	31944	0	0
T17	0	46115	0	0
T18	0	121481	0	0
T34	44348	0	0	0
T65	0	110496	0	0
T67	11858	0	0	0
T100	60348	0	0	0
T111	14958	0	0	0
T124	0	161750	0	0
T173	6533	0	0	0
T218	0	119703	0	0
T253	0	36421	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465478317	3330	0	0
T13	208173	6	0	0
T14	697889	0	0	0
T16	151318	0	0	0
T65	462082	0	0	0
T69	217431	0	0	0
T76	28218	0	0	0
T100	60348	0	0	0
T145	9581	0	0	0
T154	0	89	0	0
T158	8527	0	0	0
T228	47490	0	0	0
T253	0	65	0	0
T254	0	134	0	0
T319	0	36	0	0
T321	0	102	0	0
T322	0	46	0	0
T323	0	23	0	0
T324	0	42	0	0
T325	0	145	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465478317	2932	0	0
T13	208173	65	0	0
T14	697889	0	0	0
T16	151318	0	0	0
T65	462082	0	0	0
T69	217431	0	0	0
T76	28218	0	0	0
T100	60348	0	0	0
T145	9581	0	0	0
T154	0	115	0	0
T158	8527	0	0	0
T228	47490	0	0	0
T253	0	59	0	0
T254	0	119	0	0
T319	0	66	0	0
T321	0	143	0	0
T322	0	30	0	0
T323	0	30	0	0
T324	0	83	0	0
T325	0	172	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465478317	3689	0	0
T13	208173	58	0	0
T14	697889	0	0	0
T16	151318	0	0	0
T65	462082	0	0	0
T69	217431	0	0	0
T76	28218	0	0	0
T100	60348	0	0	0
T145	9581	0	0	0
T154	0	75	0	0
T158	8527	0	0	0
T228	47490	0	0	0
T253	0	67	0	0
T254	0	125	0	0
T319	0	81	0	0
T321	0	82	0	0
T322	0	42	0	0
T323	0	12	0	0
T324	0	99	0	0
T325	0	198	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465478317	3682	0	0
T13	208173	63	0	0
T14	697889	0	0	0
T16	151318	0	0	0
T65	462082	0	0	0
T69	217431	0	0	0
T76	28218	0	0	0
T100	60348	0	0	0
T145	9581	0	0	0
T154	0	78	0	0
T158	8527	0	0	0
T228	47490	0	0	0
T253	0	71	0	0
T254	0	107	0	0
T319	0	59	0	0
T321	0	101	0	0
T322	0	36	0	0
T323	0	12	0	0
T324	0	98	0	0
T325	0	178	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465478317	2939	0	0
T13	208173	29	0	0
T14	697889	0	0	0
T16	151318	0	0	0
T65	462082	0	0	0
T69	217431	0	0	0
T76	28218	0	0	0
T100	60348	0	0	0
T145	9581	0	0	0
T154	0	109	0	0
T158	8527	0	0	0
T228	47490	0	0	0
T253	0	54	0	0
T254	0	117	0	0
T319	0	54	0	0
T321	0	123	0	0
T322	0	41	0	0
T323	0	15	0	0
T324	0	101	0	0
T325	0	174	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465478317	1885	0	0
T13	208173	37	0	0
T14	697889	0	0	0
T16	151318	0	0	0
T65	462082	0	0	0
T69	217431	0	0	0
T76	28218	0	0	0
T100	60348	0	0	0
T145	9581	0	0	0
T154	0	97	0	0
T158	8527	0	0	0
T228	47490	0	0	0
T253	0	54	0	0
T254	0	130	0	0
T319	0	68	0	0
T321	0	83	0	0
T322	0	31	0	0
T323	0	22	0	0
T324	0	107	0	0
T325	0	160	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465478317	1087	0	0
T13	208173	28	0	0
T14	697889	0	0	0
T16	151318	0	0	0
T65	462082	0	0	0
T69	217431	0	0	0
T76	28218	0	0	0
T100	60348	0	0	0
T145	9581	0	0	0
T154	0	54	0	0
T158	8527	0	0	0
T228	47490	0	0	0
T253	0	46	0	0
T254	0	72	0	0
T319	0	24	0	0
T321	0	71	0	0
T322	0	11	0	0
T323	0	1	0	0
T324	0	36	0	0
T325	0	93	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465478317	1416	0	0
T13	208173	32	0	0
T14	697889	0	0	0
T16	151318	0	0	0
T65	462082	0	0	0
T69	217431	0	0	0
T76	28218	0	0	0
T100	60348	0	0	0
T145	9581	0	0	0
T154	0	67	0	0
T158	8527	0	0	0
T228	47490	0	0	0
T253	0	39	0	0
T254	0	55	0	0
T319	0	54	0	0
T321	0	102	0	0
T322	0	19	0	0
T323	0	28	0	0
T324	0	47	0	0
T325	0	146	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465478317	3526	0	0
T13	208173	37	0	0
T14	697889	0	0	0
T16	151318	0	0	0
T65	462082	0	0	0
T69	217431	0	0	0
T76	28218	0	0	0
T100	60348	0	0	0
T145	9581	0	0	0
T154	0	81	0	0
T158	8527	0	0	0
T228	47490	0	0	0
T253	0	24	0	0
T254	0	91	0	0
T319	0	49	0	0
T321	0	117	0	0
T322	0	11	0	0
T323	0	19	0	0
T324	0	97	0	0
T325	0	149	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465478317	4461	0	0
T13	208173	61	0	0
T14	697889	0	0	0
T16	151318	0	0	0
T65	462082	0	0	0
T69	217431	0	0	0
T76	28218	0	0	0
T100	60348	0	0	0
T104	0	76	0	0
T145	9581	0	0	0
T154	0	86	0	0
T158	8527	0	0	0
T228	47490	0	0	0
T253	0	55	0	0
T254	0	187	0	0
T321	0	97	0	0
T322	0	36	0	0
T323	0	25	0	0
T324	0	71	0	0
T325	0	215	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465478317	2771	0	0
T13	208173	29	0	0
T14	697889	0	0	0
T16	151318	0	0	0
T65	462082	0	0	0
T69	217431	0	0	0
T76	28218	0	0	0
T100	60348	0	0	0
T145	9581	0	0	0
T154	0	80	0	0
T158	8527	0	0	0
T228	47490	0	0	0
T253	0	47	0	0
T254	0	101	0	0
T319	0	50	0	0
T321	0	111	0	0
T322	0	33	0	0
T323	0	18	0	0
T324	0	60	0	0
T325	0	140	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465478317	2923	0	0
T13	208173	34	0	0
T14	697889	0	0	0
T16	151318	0	0	0
T65	462082	0	0	0
T69	217431	0	0	0
T76	28218	0	0	0
T100	60348	0	0	0
T145	9581	0	0	0
T154	0	105	0	0
T158	8527	0	0	0
T228	47490	0	0	0
T253	0	69	0	0
T254	0	90	0	0
T319	0	71	0	0
T321	0	95	0	0
T322	0	25	0	0
T323	0	12	0	0
T324	0	99	0	0
T325	0	202	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465478317	2827	0	0
T13	208173	47	0	0
T14	697889	0	0	0
T16	151318	0	0	0
T65	462082	0	0	0
T69	217431	0	0	0
T76	28218	0	0	0
T100	60348	0	0	0
T145	9581	0	0	0
T154	0	67	0	0
T158	8527	0	0	0
T228	47490	0	0	0
T253	0	77	0	0
T254	0	104	0	0
T319	0	64	0	0
T321	0	103	0	0
T322	0	38	0	0
T323	0	13	0	0
T324	0	59	0	0
T325	0	82	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465478317	2997	0	0
T13	208173	36	0	0
T14	697889	0	0	0
T16	151318	0	0	0
T65	462082	0	0	0
T69	217431	0	0	0
T76	28218	0	0	0
T100	60348	0	0	0
T145	9581	0	0	0
T154	0	86	0	0
T158	8527	0	0	0
T228	47490	0	0	0
T253	0	43	0	0
T254	0	119	0	0
T319	0	29	0	0
T321	0	107	0	0
T322	0	42	0	0
T323	0	14	0	0
T324	0	83	0	0
T325	0	209	0	0