Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.23	100.00	100.00		90.00	100.00	96.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.56	100.00	100.00	100.00	90.00	98.15	97.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.84	97.40	96.15	97.04		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.84	97.40	96.15	97.04		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.84	97.40	96.15	97.04		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		86	86	100.00
CONT_ASSIGN	138	1	1	100.00
ALWAYS	153	3	3	100.00
ALWAYS	164	61	61	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
153	1	1
154	1	1
156	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			==> MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
224		excluded
			Exclude Annotation: VC_COV_UNR
225		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
276		excluded
			Exclude Annotation: VC_COV_UNR
277		excluded
			Exclude Annotation: VC_COV_UNR
279		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
339	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	29	29	100.00
Logical	29	29	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T3,T4
1	Excluded		VC_COV_UNR

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T8,T5,T9
1	Covered	T21,T22,T23

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T77,T136,T137
1	Covered	T77,T136,T137

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T8,T5,T9
1	Covered	T8,T5,T9

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T8

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T8

---

FSM Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	11	84.62
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T8,T5,T9
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T3,T4
ReadWaitSt	252	Covered	T1,T3,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T8,T5,T9
IdleSt->ReadSt	236	Covered	T1,T3,T4
InitSt->ErrorSt	315	Covered	T178,T179
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T180,T181,T182
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T1,T3,T8
ReadSt->ReadWaitSt	252	Covered	T1,T3,T4
ReadWaitSt->ErrorSt	276	Not Covered
ReadWaitSt->IdleSt	270	Covered	T1,T3,T4
ResetSt->ErrorSt	315	Covered	T76,T77,T78
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests	Exclude Annotation
AccessError	256	Covered	T1,T3,T8
CheckFailError	317	Covered	T77,T136,T137
FsmStateError	289	Covered	T8,T5,T9
MacroEccCorrError	221	Excluded		VC_COV_UNR
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded
AccessError->FsmStateError	325	Covered	T8,T5,T6
AccessError->MacroEccCorrError	221	Excluded
AccessError->NoError	235	Covered	T1,T3,T5
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded
CheckFailError->NoError	235	Covered	T77,T136,T137
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded
FsmStateError->NoError	235	Covered	T8,T5,T9
MacroEccCorrError->AccessError	256	Excluded
MacroEccCorrError->CheckFailError	317	Excluded
MacroEccCorrError->FsmStateError	325	Excluded
MacroEccCorrError->NoError	235	Excluded
NoError->AccessError	256	Covered	T1,T3,T8
NoError->CheckFailError	317	Covered	T77,T136,T137
NoError->FsmStateError	289	Covered	T9,T10,T6
NoError->MacroEccCorrError	221	Excluded

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	18	18	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00
IF	153	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests	Exclude Annotation
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T3,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T1,T4,T111
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T3,T8
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T3,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T8,T5,T9
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T8,T5,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T8,T5,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T8,T5,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T77,T136,T137
1	0	Covered	T77,T136,T137
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T8,T5,T9
1	0	Covered	T8,T5,T9
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	if ((otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}))

Branches:

-1-	Status	Tests
1	Covered	T5,T9,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	462139186	461300521	0	0
DigestKnown_A	462139186	461300521	0	0
DigestOffsetMustBeRepresentable_A	1149	1149	0	0
EccErrorState_A	462139186	11030	0	0
ErrorKnown_A	462139186	461300521	0	0
FsmStateKnown_A	462139186	461300521	0	0
InitDoneKnown_A	462139186	461300521	0	0
InitReadLocksPartition_A	462139186	83691322	0	0
InitWriteLocksPartition_A	462139186	83691322	0	0
OffsetMustBeBlockAligned_A	1149	1149	0	0
OtpAddrKnown_A	462139186	461300521	0	0
OtpCmdKnown_A	462139186	461300521	0	0
OtpErrorState_A	462139186	0	0	0
OtpReqKnown_A	462139186	461300521	0	0
OtpSizeKnown_A	462139186	461300521	0	0
OtpWdataKnown_A	462139186	461300521	0	0
ReadLockPropagation_A	462139186	205890439	0	0
SizeMustBeBlockAligned_A	1149	1149	0	0
TlulGntKnown_A	462139186	461300521	0	0
TlulRdataKnown_A	462139186	461300521	0	0
TlulReadOnReadLock_A	462139186	7664	0	0
TlulRerrorKnown_A	462139186	461300521	0	0
TlulRvalidKnown_A	462139186	461300521	0	0
WriteLockPropagation_A	462139186	2445979	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	462139186	25789588	0	0
u_state_regs_A	462139186	461300521	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	11030	0	0
T77	10799	2758	0	0
T78	600616	0	0	0
T108	57069	0	0	0
T109	60713	0	0	0
T125	88329	0	0	0
T136	0	3609	0	0
T137	0	2205	0	0
T139	32178	0	0	0
T141	0	2458	0	0
T148	9490	0	0	0
T149	10179	0	0	0
T150	38123	0	0	0
T151	50446	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	83691322	0	0
T1	47671	675	0	0
T2	17694	5757	0	0
T3	53055	791	0	0
T4	44993	555	0	0
T5	18174	6570	0	0
T8	40211	29032	0	0
T9	19474	7415	0	0
T10	16051	4442	0	0
T11	15094	186	0	0
T12	60034	571	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	83691322	0	0
T1	47671	675	0	0
T2	17694	5757	0	0
T3	53055	791	0	0
T4	44993	555	0	0
T5	18174	6570	0	0
T8	40211	29032	0	0
T9	19474	7415	0	0
T10	16051	4442	0	0
T11	15094	186	0	0
T12	60034	571	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	205890439	0	0
T1	47671	2519	0	0
T2	17694	0	0	0
T3	53055	4313	0	0
T4	44993	0	0	0
T5	18174	10527	0	0
T6	0	256998	0	0
T7	0	499856	0	0
T8	40211	31758	0	0
T9	19474	0	0	0
T10	16051	0	0	0
T11	15094	6247	0	0
T12	60034	15501	0	0
T34	0	8675	0	0
T111	0	1673	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	7664	0	0
T1	47671	7	0	0
T2	17694	0	0	0
T3	53055	2	0	0
T4	44993	0	0	0
T5	18174	4	0	0
T6	0	73	0	0
T7	0	54	0	0
T8	40211	10	0	0
T9	19474	0	0	0
T10	16051	0	0	0
T11	15094	1	0	0
T12	60034	8	0	0
T34	0	4	0	0
T111	0	1	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	2445979	0	0
T3	53055	2665	0	0
T4	44993	0	0	0
T5	18174	0	0	0
T6	439034	0	0	0
T8	40211	0	0	0
T9	19474	0	0	0
T10	16051	0	0	0
T11	15094	0	0	0
T12	60034	0	0	0
T14	0	35848	0	0
T15	4928	0	0	0
T34	0	1866	0	0
T69	0	15091	0	0
T100	0	1210	0	0
T101	0	4353	0	0
T102	0	6051	0	0
T103	0	1023	0	0
T105	0	9563	0	0
T106	0	10992	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	25789588	0	0
T1	47671	39757	0	0
T2	17694	0	0	0
T3	53055	37436	0	0
T4	44993	0	0	0
T5	18174	0	0	0
T8	40211	2934	0	0
T9	19474	0	0	0
T10	16051	0	0	0
T11	15094	0	0	0
T12	60034	52944	0	0
T14	0	417895	0	0
T34	0	36296	0	0
T69	0	198045	0	0
T100	0	43069	0	0
T111	0	8023	0	0
T158	0	3114	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T138,T46

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T69,T139,T140

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T8,T5,T9
1	Covered	T21,T22,T23

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T77,T134,T141
1	Covered	T77,T134,T141

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T8,T5,T9
1	Covered	T8,T5,T10

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T8

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T8

---

FSM Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T8,T5,T9
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T3,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T8,T5,T10
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T180,T181,T182
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T9,T67,T145
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T1,T2,T3
ReadSt->ReadWaitSt	252	Covered	T1,T3,T4
ReadWaitSt->ErrorSt	276	Covered	T140,T167,T183
ReadWaitSt->IdleSt	270	Covered	T1,T3,T4
ResetSt->ErrorSt	315	Covered	T76,T77,T78
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T1,T2,T3
CheckFailError	317	Covered	T77,T134,T141
FsmStateError	289	Covered	T8,T5,T10
MacroEccCorrError	221	Covered	T10,T69,T138
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T8,T5,T6
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T1,T2,T3
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T77,T134,T141
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T8,T5,T10
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T10,T138,T46
MacroEccCorrError->NoError	235	Covered	T69,T140,T41
NoError->AccessError	256	Covered	T1,T2,T3
NoError->CheckFailError	317	Covered	T77,T134,T141
NoError->FsmStateError	289	Covered	T6,T7,T13
NoError->MacroEccCorrError	221	Covered	T10,T69,T138

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T10,T138,T46
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T9,T67,T145
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T3,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T1,T4,T7
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T69,T139,T140
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T3,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T140,T167,T183
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T8,T5,T9
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T8,T5,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T8,T5,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T8,T5,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T77,T134,T141
1	0	Covered	T77,T134,T141
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T8,T5,T10
1	0	Covered	T8,T5,T9
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	462139186	461300521	0	0
DigestKnown_A	462139186	461300521	0	0
DigestOffsetMustBeRepresentable_A	1149	1149	0	0
EccErrorState_A	462139186	12120	0	0
ErrorKnown_A	462139186	461300521	0	0
FsmStateKnown_A	462139186	461300521	0	0
InitDoneKnown_A	462139186	461300521	0	0
InitReadLocksPartition_A	462139186	83869730	0	0
InitWriteLocksPartition_A	462139186	83869730	0	0
OffsetMustBeBlockAligned_A	1149	1149	0	0
OtpAddrKnown_A	462139186	461300521	0	0
OtpCmdKnown_A	462139186	461300521	0	0
OtpErrorState_A	462139186	66	0	0
OtpReqKnown_A	462139186	461300521	0	0
OtpSizeKnown_A	462139186	461300521	0	0
OtpWdataKnown_A	462139186	461300521	0	0
ReadLockPropagation_A	462139186	192008045	0	0
SizeMustBeBlockAligned_A	1149	1149	0	0
TlulGntKnown_A	462139186	461300521	0	0
TlulRdataKnown_A	462139186	461300521	0	0
TlulReadOnReadLock_A	462139186	8008	0	0
TlulRerrorKnown_A	462139186	461300521	0	0
TlulRvalidKnown_A	462139186	461300521	0	0
WriteLockPropagation_A	462139186	2035352	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	462139186	25091890	0	0
u_state_regs_A	462139186	461300521	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	12120	0	0
T77	10799	2758	0	0
T78	600616	0	0	0
T108	57069	0	0	0
T109	60713	0	0	0
T125	88329	0	0	0
T134	0	4035	0	0
T135	0	2869	0	0
T139	32178	0	0	0
T141	0	2458	0	0
T148	9490	0	0	0
T149	10179	0	0	0
T150	38123	0	0	0
T151	50446	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	83869730	0	0
T1	47671	896	0	0
T2	17694	5791	0	0
T3	53055	1029	0	0
T4	44993	776	0	0
T5	18174	6621	0	0
T8	40211	29083	0	0
T9	19474	7456	0	0
T10	16051	4476	0	0
T11	15094	220	0	0
T12	60034	724	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	83869730	0	0
T1	47671	896	0	0
T2	17694	5791	0	0
T3	53055	1029	0	0
T4	44993	776	0	0
T5	18174	6621	0	0
T8	40211	29083	0	0
T9	19474	7456	0	0
T10	16051	4476	0	0
T11	15094	220	0	0
T12	60034	724	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	66	0	0
T6	439034	0	0	0
T7	905990	0	0	0
T9	19474	1	0	0
T10	16051	0	0	0
T11	15094	0	0	0
T12	60034	0	0	0
T15	4928	0	0	0
T67	11858	1	0	0
T111	14958	0	0	0
T140	0	1	0	0
T145	0	1	0	0
T161	0	1	0	0
T165	0	1	0	0
T166	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T169	0	1	0	0
T173	6533	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	192008045	0	0
T1	47671	2669	0	0
T2	17694	2393	0	0
T3	53055	5022	0	0
T4	44993	160	0	0
T5	18174	9184	0	0
T6	0	255107	0	0
T7	0	500104	0	0
T8	40211	31747	0	0
T9	19474	0	0	0
T10	16051	0	0	0
T11	15094	7911	0	0
T12	60034	16840	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	8008	0	0
T1	47671	4	0	0
T2	17694	1	0	0
T3	53055	3	0	0
T4	44993	0	0	0
T5	18174	5	0	0
T6	0	65	0	0
T7	0	54	0	0
T8	40211	9	0	0
T9	19474	0	0	0
T10	16051	0	0	0
T11	15094	0	0	0
T12	60034	6	0	0
T34	0	7	0	0
T111	0	1	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	2035352	0	0
T3	53055	5539	0	0
T4	44993	0	0	0
T5	18174	0	0	0
T6	439034	0	0	0
T8	40211	0	0	0
T9	19474	0	0	0
T10	16051	0	0	0
T11	15094	0	0	0
T12	60034	10166	0	0
T14	0	22880	0	0
T15	4928	0	0	0
T40	0	4437	0	0
T69	0	15091	0	0
T100	0	2960	0	0
T101	0	4318	0	0
T102	0	23571	0	0
T103	0	6305	0	0
T105	0	24430	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	25091890	0	0
T1	47671	39570	0	0
T2	17694	0	0	0
T3	53055	44483	0	0
T4	44993	0	0	0
T5	18174	0	0	0
T8	40211	2917	0	0
T9	19474	3676	0	0
T10	16051	0	0	0
T11	15094	0	0	0
T12	60034	52808	0	0
T14	0	406990	0	0
T34	0	36143	0	0
T67	0	3743	0	0
T100	0	50249	0	0
T111	0	7955	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T68,T113,T46

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T69,T40,T73

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T8,T5,T9
1	Covered	T21,T22,T23

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T77,T134,T137
1	Covered	T77,T134,T137

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T8,T5,T9
1	Covered	T8,T5,T9

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00111101000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T12,T34

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T12,T34

---

FSM Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T8,T5,T9
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T2,T3
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T8,T5,T10
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T180,T181,T182
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T9,T67,T145
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T1,T3,T12
ReadSt->ReadWaitSt	252	Covered	T1,T2,T3
ReadWaitSt->ErrorSt	276	Covered	T140,T133,T184
ReadWaitSt->IdleSt	270	Covered	T1,T2,T3
ResetSt->ErrorSt	315	Covered	T76,T77,T78
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T1,T3,T12
CheckFailError	317	Covered	T77,T134,T137
FsmStateError	289	Covered	T8,T5,T9
MacroEccCorrError	221	Covered	T69,T68,T113
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T6,T7,T14
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T1,T3,T12
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T77,T134,T137
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T8,T5,T9
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T68,T113,T46
MacroEccCorrError->NoError	235	Covered	T69,T40,T73
NoError->AccessError	256	Covered	T1,T3,T12
NoError->CheckFailError	317	Covered	T77,T134,T137
NoError->FsmStateError	289	Covered	T8,T5,T9
NoError->MacroEccCorrError	221	Covered	T69,T68,T113

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T12,T34
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T68,T113,T46
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T158,T138,T162
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T1,T7,T16
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T3,T12
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T69,T40,T73
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T140,T133,T184
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T8,T5,T9
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T8,T5,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T8,T5,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T8,T5,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T77,T134,T137
1	0	Covered	T77,T134,T137
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T8,T5,T9
1	0	Covered	T8,T5,T9
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	462139186	461300521	0	0
DigestKnown_A	462139186	461300521	0	0
DigestOffsetMustBeRepresentable_A	1149	1149	0	0
EccErrorState_A	462139186	17798	0	0
ErrorKnown_A	462139186	461300521	0	0
FsmStateKnown_A	462139186	461300521	0	0
InitDoneKnown_A	462139186	461300521	0	0
InitReadLocksPartition_A	462139186	84047012	0	0
InitWriteLocksPartition_A	462139186	84047012	0	0
OffsetMustBeBlockAligned_A	1149	1149	0	0
OtpAddrKnown_A	462139186	461300521	0	0
OtpCmdKnown_A	462139186	461300521	0	0
OtpErrorState_A	462139186	48	0	0
OtpReqKnown_A	462139186	461300521	0	0
OtpSizeKnown_A	462139186	461300521	0	0
OtpWdataKnown_A	462139186	461300521	0	0
ReadLockPropagation_A	462139186	196696652	0	0
SizeMustBeBlockAligned_A	1149	1149	0	0
TlulGntKnown_A	462139186	461300521	0	0
TlulRdataKnown_A	462139186	461300521	0	0
TlulReadOnReadLock_A	462139186	8303	0	0
TlulRerrorKnown_A	462139186	461300521	0	0
TlulRvalidKnown_A	462139186	461300521	0	0
WriteLockPropagation_A	462139186	1501425	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	462139186	16704961	0	0
u_state_regs_A	462139186	461300521	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	17798	0	0
T77	10799	2758	0	0
T78	600616	0	0	0
T108	57069	0	0	0
T109	60713	0	0	0
T125	88329	0	0	0
T134	0	4035	0	0
T135	0	2869	0	0
T137	0	2205	0	0
T139	32178	0	0	0
T141	0	2458	0	0
T147	0	3473	0	0
T148	9490	0	0	0
T149	10179	0	0	0
T150	38123	0	0	0
T151	50446	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	84047012	0	0
T1	47671	1117	0	0
T2	17694	5825	0	0
T3	53055	1267	0	0
T4	44993	997	0	0
T5	18174	6672	0	0
T8	40211	29134	0	0
T9	19474	7490	0	0
T10	16051	4510	0	0
T11	15094	254	0	0
T12	60034	877	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	84047012	0	0
T1	47671	1117	0	0
T2	17694	5825	0	0
T3	53055	1267	0	0
T4	44993	997	0	0
T5	18174	6672	0	0
T8	40211	29134	0	0
T9	19474	7490	0	0
T10	16051	4510	0	0
T11	15094	254	0	0
T12	60034	877	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	48	0	0
T65	462082	0	0	0
T68	10114	0	0	0
T69	217431	0	0	0
T76	28218	0	0	0
T101	100463	0	0	0
T110	24419	0	0	0
T112	14810	0	0	0
T133	0	1	0	0
T138	0	1	0	0
T140	0	1	0	0
T158	8527	1	0	0
T162	0	1	0	0
T163	0	1	0	0
T164	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T172	0	1	0	0
T174	78281	0	0	0
T175	12543	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	196696652	0	0
T1	47671	3987	0	0
T2	17694	3431	0	0
T3	53055	6148	0	0
T4	44993	1197	0	0
T5	18174	10525	0	0
T6	0	261224	0	0
T7	0	498358	0	0
T8	40211	0	0	0
T9	19474	0	0	0
T10	16051	0	0	0
T11	15094	0	0	0
T12	60034	13486	0	0
T34	0	7950	0	0
T111	0	714	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	8303	0	0
T1	47671	4	0	0
T2	17694	0	0	0
T3	53055	2	0	0
T4	44993	0	0	0
T5	18174	4	0	0
T6	0	90	0	0
T7	0	41	0	0
T8	40211	5	0	0
T9	19474	0	0	0
T10	16051	0	0	0
T11	15094	0	0	0
T12	60034	13	0	0
T13	0	1	0	0
T14	0	95	0	0
T34	0	9	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	1501425	0	0
T6	439034	0	0	0
T7	905990	0	0	0
T12	60034	6959	0	0
T13	208173	0	0	0
T14	697889	6333	0	0
T15	4928	0	0	0
T34	44348	1630	0	0
T67	11858	0	0	0
T69	0	15317	0	0
T100	0	2856	0	0
T103	0	2639	0	0
T105	0	15631	0	0
T107	0	3488	0	0
T108	0	2088	0	0
T111	14958	0	0	0
T129	0	5909	0	0
T173	6533	0	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	16704961	0	0
T5	18174	0	0	0
T6	439034	0	0	0
T7	905990	0	0	0
T8	40211	2900	0	0
T9	19474	0	0	0
T10	16051	0	0	0
T11	15094	0	0	0
T12	60034	52672	0	0
T14	0	319595	0	0
T15	4928	0	0	0
T34	0	35990	0	0
T67	11858	0	0	0
T69	0	197705	0	0
T76	0	2445	0	0
T100	0	50079	0	0
T102	0	56325	0	0
T103	0	49609	0	0
T158	0	3092	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0