Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.84	97.40	96.15	97.04		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.84	97.40	96.15	97.04		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T24,T132

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T69,T40,T133

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T8,T5,T9
1	Covered	T21,T22,T23

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T134,T135
1	Covered	T134,T135

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T8,T5,T9
1	Covered	T8,T5,T9

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b10001111000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

---

FSM Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T8,T5,T9
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T3,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T8,T5,T10
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T9,T67,T145
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T158,T138,T159
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T1,T2,T3
ReadSt->ReadWaitSt	252	Covered	T1,T3,T4
ReadWaitSt->ErrorSt	276	Covered	T146,T167,T183
ReadWaitSt->IdleSt	270	Covered	T1,T3,T4
ResetSt->ErrorSt	315	Covered	T76,T77,T78
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T1,T2,T3
CheckFailError	317	Covered	T134,T135
FsmStateError	289	Covered	T8,T5,T9
MacroEccCorrError	221	Covered	T10,T69,T40
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T5,T6,T14
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T1,T2,T3
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T134,T135
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T8,T5,T9
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T10,T24,T133
MacroEccCorrError->NoError	235	Covered	T69,T40,T41
NoError->AccessError	256	Covered	T1,T2,T3
NoError->CheckFailError	317	Covered	T134,T135
NoError->FsmStateError	289	Covered	T8,T9,T6
NoError->MacroEccCorrError	221	Covered	T10,T69,T40

---

Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T10,T24,T132
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T159,T160,T148
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T3,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T1,T7,T111
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T69,T40,T133
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T3,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T146,T167,T183
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T8,T5,T9
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T8,T5,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T8,T5,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T8,T5,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T134,T135
1	0	Covered	T134,T135
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T8,T5,T9
1	0	Covered	T8,T5,T9
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	462139186	461300521	0	0
DigestKnown_A	462139186	461300521	0	0
DigestOffsetMustBeRepresentable_A	1149	1149	0	0
EccErrorState_A	462139186	6904	0	0
ErrorKnown_A	462139186	461300521	0	0
FsmStateKnown_A	462139186	461300521	0	0
InitDoneKnown_A	462139186	461300521	0	0
InitReadLocksPartition_A	462139186	84223288	0	0
InitWriteLocksPartition_A	462139186	84223288	0	0
OffsetMustBeBlockAligned_A	1149	1149	0	0
OtpAddrKnown_A	462139186	461300521	0	0
OtpCmdKnown_A	462139186	461300521	0	0
OtpErrorState_A	462139186	55	0	0
OtpReqKnown_A	462139186	461300521	0	0
OtpSizeKnown_A	462139186	461300521	0	0
OtpWdataKnown_A	462139186	461300521	0	0
ReadLockPropagation_A	462139186	185664303	0	0
SizeMustBeBlockAligned_A	1149	1149	0	0
TlulGntKnown_A	462139186	461300521	0	0
TlulRdataKnown_A	462139186	461300521	0	0
TlulReadOnReadLock_A	462139186	8174	0	0
TlulRerrorKnown_A	462139186	461300521	0	0
TlulRvalidKnown_A	462139186	461300521	0	0
WriteLockPropagation_A	462139186	2088863	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	462139186	24264583	0	0
u_state_regs_A	462139186	461300521	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	6904	0	0
T21	931891	0	0	0
T87	41749	0	0	0
T115	52914	0	0	0
T134	13170	4035	0	0
T135	0	2869	0	0
T152	12127	0	0	0
T153	21752	0	0	0
T154	410362	0	0	0
T155	13095	0	0	0
T156	11230	0	0	0
T157	9007	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	84223288	0	0
T1	47671	1316	0	0
T2	17694	5859	0	0
T3	53055	1505	0	0
T4	44993	1218	0	0
T5	18174	6723	0	0
T8	40211	29185	0	0
T9	19474	7524	0	0
T10	16051	4544	0	0
T11	15094	288	0	0
T12	60034	1030	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	84223288	0	0
T1	47671	1316	0	0
T2	17694	5859	0	0
T3	53055	1505	0	0
T4	44993	1218	0	0
T5	18174	6723	0	0
T8	40211	29185	0	0
T9	19474	7524	0	0
T10	16051	4544	0	0
T11	15094	288	0	0
T12	60034	1030	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	55	0	0
T40	60180	0	0	0
T77	10799	0	0	0
T105	156983	0	0	0
T106	98130	0	0	0
T107	42008	0	0	0
T108	57069	0	0	0
T146	0	1	0	0
T148	0	1	0	0
T159	11860	1	0	0
T160	10951	1	0	0
T167	0	1	0	0
T183	0	1	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0
T189	18719	0	0	0
T190	10316	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	185664303	0	0
T1	47671	4748	0	0
T2	17694	3423	0	0
T3	53055	4180	0	0
T4	44993	1193	0	0
T5	18174	10510	0	0
T6	0	259471	0	0
T7	0	499386	0	0
T8	40211	31744	0	0
T9	19474	0	0	0
T10	16051	0	0	0
T11	15094	7909	0	0
T12	60034	13866	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	8174	0	0
T1	47671	6	0	0
T2	17694	2	0	0
T3	53055	2	0	0
T4	44993	1	0	0
T5	18174	7	0	0
T6	0	87	0	0
T7	0	47	0	0
T8	40211	8	0	0
T9	19474	0	0	0
T10	16051	0	0	0
T11	15094	2	0	0
T12	60034	7	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	2088863	0	0
T4	44993	3749	0	0
T5	18174	0	0	0
T6	439034	0	0	0
T8	40211	0	0	0
T9	19474	0	0	0
T10	16051	0	0	0
T11	15094	0	0	0
T12	60034	0	0	0
T14	0	15173	0	0
T15	4928	0	0	0
T34	0	2057	0	0
T67	11858	0	0	0
T100	0	4170	0	0
T101	0	4318	0	0
T102	0	6051	0	0
T103	0	3630	0	0
T105	0	9629	0	0
T106	0	8359	0	0
T107	0	4104	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	24264583	0	0
T1	47671	39218	0	0
T2	17694	0	0	0
T3	53055	44041	0	0
T4	44993	34394	0	0
T5	18174	0	0	0
T8	40211	2883	0	0
T9	19474	0	0	0
T10	16051	0	0	0
T11	15094	0	0	0
T12	60034	52536	0	0
T14	0	354385	0	0
T34	0	35837	0	0
T69	0	197535	0	0
T100	0	49909	0	0
T111	0	7819	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T142,T71,T84

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T69,T40,T139

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T8,T5,T9
1	Covered	T21,T22,T23

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T143,T134,T144
1	Covered	T143,T134,T144

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T8,T5,T9
1	Covered	T8,T5,T9

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T3,T5

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b11001010000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T3,T8

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

---

FSM Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T8,T5,T9
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T3,T5
ReadWaitSt	252	Covered	T1,T3,T5
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T8,T5,T10
IdleSt->ReadSt	236	Covered	T1,T3,T5
InitSt->ErrorSt	315	Covered	T9,T67,T145
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T113,T159,T160
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T1,T3,T5
ReadSt->ReadWaitSt	252	Covered	T1,T3,T5
ReadWaitSt->ErrorSt	276	Covered	T191,T184,T192
ReadWaitSt->IdleSt	270	Covered	T1,T3,T5
ResetSt->ErrorSt	315	Covered	T76,T77,T78
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T1,T3,T5
CheckFailError	317	Covered	T143,T134,T144
FsmStateError	289	Covered	T8,T5,T9
MacroEccCorrError	221	Covered	T69,T40,T139
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T5,T6,T14
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T1,T3,T5
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T143,T134,T144
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T8,T5,T9
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T139,T140,T142
MacroEccCorrError->NoError	235	Covered	T69,T40,T73
NoError->AccessError	256	Covered	T1,T3,T5
NoError->CheckFailError	317	Covered	T143,T134,T144
NoError->FsmStateError	289	Covered	T8,T9,T10
NoError->MacroEccCorrError	221	Covered	T69,T40,T139

---

Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T5

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T5

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T142,T71,T84
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T113,T193,T194
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T3,T5
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T3,T5
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T1,T111,T16
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T3,T5
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T69,T40,T139
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T3,T5
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T191,T184,T192
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T3,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T8,T5,T9
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T8,T5,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T8,T5,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T8,T5,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T143,T134,T144
1	0	Covered	T143,T134,T144
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T8,T5,T9
1	0	Covered	T8,T5,T9
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T8
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	462139186	461300521	0	0
DigestKnown_A	462139186	461300521	0	0
DigestOffsetMustBeRepresentable_A	1149	1149	0	0
EccErrorState_A	462139186	18977	0	0
ErrorKnown_A	462139186	461300521	0	0
FsmStateKnown_A	462139186	461300521	0	0
InitDoneKnown_A	462139186	461300521	0	0
InitReadLocksPartition_A	462139186	84398733	0	0
InitWriteLocksPartition_A	462139186	84398733	0	0
OffsetMustBeBlockAligned_A	1149	1149	0	0
OtpAddrKnown_A	462139186	461300521	0	0
OtpCmdKnown_A	462139186	461300521	0	0
OtpErrorState_A	462139186	35	0	0
OtpReqKnown_A	462139186	461300521	0	0
OtpSizeKnown_A	462139186	461300521	0	0
OtpWdataKnown_A	462139186	461300521	0	0
ReadLockPropagation_A	462139186	198474217	0	0
SizeMustBeBlockAligned_A	1149	1149	0	0
TlulGntKnown_A	462139186	461300521	0	0
TlulRdataKnown_A	462139186	461300521	0	0
TlulReadOnReadLock_A	462139186	7642	0	0
TlulRerrorKnown_A	462139186	461300521	0	0
TlulRvalidKnown_A	462139186	461300521	0	0
WriteLockPropagation_A	462139186	918394	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	462139186	9985145	0	0
u_state_regs_A	462139186	461300521	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	18977	0	0
T47	14137	0	0	0
T134	0	4035	0	0
T137	0	2205	0	0
T141	0	2458	0	0
T143	11895	3539	0	0
T144	0	3267	0	0
T147	0	3473	0	0
T195	36031	0	0	0
T196	138482	0	0	0
T197	23997	0	0	0
T198	4047	0	0	0
T199	14527	0	0	0
T200	26121	0	0	0
T201	4941	0	0	0
T202	22446	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	84398733	0	0
T1	47671	1503	0	0
T2	17694	5893	0	0
T3	53055	1743	0	0
T4	44993	1439	0	0
T5	18174	6774	0	0
T8	40211	29236	0	0
T9	19474	7558	0	0
T10	16051	4578	0	0
T11	15094	322	0	0
T12	60034	1183	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	84398733	0	0
T1	47671	1503	0	0
T2	17694	5893	0	0
T3	53055	1743	0	0
T4	44993	1439	0	0
T5	18174	6774	0	0
T8	40211	29236	0	0
T9	19474	7558	0	0
T10	16051	4578	0	0
T11	15094	322	0	0
T12	60034	1183	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	35	0	0
T40	60180	0	0	0
T46	16641	0	0	0
T104	261403	0	0	0
T105	156983	0	0	0
T106	98130	0	0	0
T113	9853	1	0	0
T138	12876	0	0	0
T152	0	1	0	0
T159	11860	0	0	0
T189	18719	0	0	0
T190	10316	0	0	0
T191	0	1	0	0
T193	0	1	0	0
T194	0	1	0	0
T203	0	1	0	0
T204	0	1	0	0
T205	0	1	0	0
T206	0	1	0	0
T207	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	198474217	0	0
T1	47671	4636	0	0
T2	17694	0	0	0
T3	53055	2339	0	0
T4	44993	384	0	0
T5	18174	9180	0	0
T6	0	256736	0	0
T7	0	503239	0	0
T8	40211	0	0	0
T9	19474	0	0	0
T10	16051	0	0	0
T11	15094	6234	0	0
T12	60034	8764	0	0
T13	0	685183	0	0
T34	0	10350	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	7642	0	0
T1	47671	8	0	0
T2	17694	0	0	0
T3	53055	1	0	0
T4	44993	0	0	0
T5	18174	8	0	0
T6	0	79	0	0
T7	0	64	0	0
T8	40211	3	0	0
T9	19474	0	0	0
T10	16051	0	0	0
T11	15094	1	0	0
T12	60034	9	0	0
T13	0	1	0	0
T34	0	8	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	918394	0	0
T3	53055	1075	0	0
T4	44993	0	0	0
T5	18174	0	0	0
T6	439034	0	0	0
T8	40211	0	0	0
T9	19474	0	0	0
T10	16051	0	0	0
T11	15094	0	0	0
T12	60034	0	0	0
T14	0	12867	0	0
T15	4928	0	0	0
T70	0	6953	0	0
T78	0	1542	0	0
T101	0	4516	0	0
T104	0	34212	0	0
T176	0	3746	0	0
T177	0	11172	0	0
T208	0	1951	0	0
T209	0	2475	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	9985145	0	0
T1	47671	39065	0	0
T2	17694	0	0	0
T3	53055	43820	0	0
T4	44993	34207	0	0
T5	18174	0	0	0
T8	40211	0	0	0
T9	19474	0	0	0
T10	16051	0	0	0
T11	15094	0	0	0
T12	60034	0	0	0
T14	0	102114	0	0
T40	0	48524	0	0
T78	0	92679	0	0
T101	0	85461	0	0
T104	0	63355	0	0
T111	0	7751	0	0
T113	0	3463	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462139186	461300521	0	0
T1	47671	46680	0	0
T2	17694	16335	0	0
T3	53055	51982	0	0
T4	44993	44194	0	0
T5	18174	17966	0	0
T8	40211	39972	0	0
T9	19474	19222	0	0
T10	16051	15802	0	0
T11	15094	14328	0	0
T12	60034	58988	0	0