Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.12	96.70	93.94		83.33	95.45	96.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.27	97.83	93.94	98.55	83.33	94.74	97.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.58	96.10	96.15	97.04		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	94.64	100.00		98.55		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.58	96.10	96.15	97.04		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	88	96.70
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	65	95.59
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	0	1
316	0	1
317	0	1
			==> MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	31	93.94
Logical	33	31	93.94
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T137,T70,T71

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T138,T139,T47

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T11
1	Covered	T28,T29,T30

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T11
1	Covered	T1,T3,T11

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T6
1	1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b10001111000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T19

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T19

---

FSM Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T3,T11
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T2,T3
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T3,T11,T8
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T107,T147,T181
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T1,T95,T144
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T6,T7,T19
ReadSt->ReadWaitSt	252	Covered	T1,T2,T3
ReadWaitSt->ErrorSt	276	Covered	T143,T183,T182
ReadWaitSt->IdleSt	270	Covered	T1,T2,T3
ResetSt->ErrorSt	315	Covered	T68,T14,T69
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	4	80.00	(Not included in score)
Transitions	11	8	72.73
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T6,T7,T19
CheckFailError	317	Not Covered
FsmStateError	289	Covered	T1,T3,T11
MacroEccCorrError	221	Covered	T138,T137,T70
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T9,T20,T15
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T6,T7,T19
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Not Covered
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T3,T11
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T138,T137,T70
MacroEccCorrError->NoError	235	Covered	T47,T63,T54
NoError->AccessError	256	Covered	T6,T7,T19
NoError->CheckFailError	317	Not Covered
NoError->FsmStateError	289	Covered	T1,T3,T11
NoError->MacroEccCorrError	221	Covered	T138,T137,T70

---

Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	42	95.45
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	1	33.33
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T137,T70,T71
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T95,T142,T81
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T7,T20,T21
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T6,T7,T19
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T138,T139,T47
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T143,T183,T182
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T28,T29,T30
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T3,T11
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T3,T8,T68
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T3,T8,T68
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T3,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T28,T29,T30

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T3,T11
1	0	Covered	T1,T3,T11
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	468048268	467164347	0	0
DigestKnown_A	468048268	467164347	0	0
DigestOffsetMustBeRepresentable_A	1149	1149	0	0
EccErrorState_A	468048268	0	0	0
ErrorKnown_A	468048268	467164347	0	0
FsmStateKnown_A	468048268	467164347	0	0
InitDoneKnown_A	468048268	467164347	0	0
InitReadLocksPartition_A	468048268	105649467	0	0
InitWriteLocksPartition_A	468048268	105649467	0	0
OffsetMustBeBlockAligned_A	1149	1149	0	0
OtpAddrKnown_A	468048268	467164347	0	0
OtpCmdKnown_A	468048268	467164347	0	0
OtpErrorState_A	468048268	45	0	0
OtpReqKnown_A	468048268	467164347	0	0
OtpSizeKnown_A	468048268	467164347	0	0
OtpWdataKnown_A	468048268	467164347	0	0
ReadLockPropagation_A	468048268	204763269	0	0
SizeMustBeBlockAligned_A	1149	1149	0	0
TlulGntKnown_A	468048268	467164347	0	0
TlulRdataKnown_A	468048268	467164347	0	0
TlulReadOnReadLock_A	468048268	8144	0	0
TlulRerrorKnown_A	468048268	467164347	0	0
TlulRvalidKnown_A	468048268	467164347	0	0
WriteLockPropagation_A	468048268	2419732	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	468048268	27625353	0	0
u_state_regs_A	468048268	467164347	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468048268	467164347	0	0
T1	10618	10374	0	0
T2	22997	22412	0	0
T3	484294	484281	0	0
T5	10189	9967	0	0
T6	99520	98704	0	0
T7	78249	76783	0	0
T8	77372	77163	0	0
T10	4528	4451	0	0
T11	16448	16247	0	0
T12	22226	21935	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468048268	467164347	0	0
T1	10618	10374	0	0
T2	22997	22412	0	0
T3	484294	484281	0	0
T5	10189	9967	0	0
T6	99520	98704	0	0
T7	78249	76783	0	0
T8	77372	77163	0	0
T10	4528	4451	0	0
T11	16448	16247	0	0
T12	22226	21935	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468048268	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468048268	467164347	0	0
T1	10618	10374	0	0
T2	22997	22412	0	0
T3	484294	484281	0	0
T5	10189	9967	0	0
T6	99520	98704	0	0
T7	78249	76783	0	0
T8	77372	77163	0	0
T10	4528	4451	0	0
T11	16448	16247	0	0
T12	22226	21935	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468048268	467164347	0	0
T1	10618	10374	0	0
T2	22997	22412	0	0
T3	484294	484281	0	0
T5	10189	9967	0	0
T6	99520	98704	0	0
T7	78249	76783	0	0
T8	77372	77163	0	0
T10	4528	4451	0	0
T11	16448	16247	0	0
T12	22226	21935	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468048268	467164347	0	0
T1	10618	10374	0	0
T2	22997	22412	0	0
T3	484294	484281	0	0
T5	10189	9967	0	0
T6	99520	98704	0	0
T7	78249	76783	0	0
T8	77372	77163	0	0
T10	4528	4451	0	0
T11	16448	16247	0	0
T12	22226	21935	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468048268	105649467	0	0
T1	10618	4670	0	0
T2	22997	610	0	0
T3	484294	725820	0	0
T5	10189	364	0	0
T6	99520	1290	0	0
T7	78249	5486	0	0
T8	77372	57181	0	0
T10	4528	88	0	0
T11	16448	3730	0	0
T12	22226	9253	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468048268	105649467	0	0
T1	10618	4670	0	0
T2	22997	610	0	0
T3	484294	725820	0	0
T5	10189	364	0	0
T6	99520	1290	0	0
T7	78249	5486	0	0
T8	77372	57181	0	0
T10	4528	88	0	0
T11	16448	3730	0	0
T12	22226	9253	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468048268	467164347	0	0
T1	10618	10374	0	0
T2	22997	22412	0	0
T3	484294	484281	0	0
T5	10189	9967	0	0
T6	99520	98704	0	0
T7	78249	76783	0	0
T8	77372	77163	0	0
T10	4528	4451	0	0
T11	16448	16247	0	0
T12	22226	21935	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468048268	467164347	0	0
T1	10618	10374	0	0
T2	22997	22412	0	0
T3	484294	484281	0	0
T5	10189	9967	0	0
T6	99520	98704	0	0
T7	78249	76783	0	0
T8	77372	77163	0	0
T10	4528	4451	0	0
T11	16448	16247	0	0
T12	22226	21935	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468048268	45	0	0
T20	264232	0	0	0
T50	12395	0	0	0
T65	12014	0	0	0
T81	0	1	0	0
T95	9949	1	0	0
T99	26648	0	0	0
T100	16997	0	0	0
T103	13101	0	0	0
T107	9328	0	0	0
T142	0	1	0	0
T143	0	1	0	0
T144	10310	0	0	0
T176	54564	0	0	0
T182	0	1	0	0
T183	0	1	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468048268	467164347	0	0
T1	10618	10374	0	0
T2	22997	22412	0	0
T3	484294	484281	0	0
T5	10189	9967	0	0
T6	99520	98704	0	0
T7	78249	76783	0	0
T8	77372	77163	0	0
T10	4528	4451	0	0
T11	16448	16247	0	0
T12	22226	21935	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468048268	467164347	0	0
T1	10618	10374	0	0
T2	22997	22412	0	0
T3	484294	484281	0	0
T5	10189	9967	0	0
T6	99520	98704	0	0
T7	78249	76783	0	0
T8	77372	77163	0	0
T10	4528	4451	0	0
T11	16448	16247	0	0
T12	22226	21935	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468048268	467164347	0	0
T1	10618	10374	0	0
T2	22997	22412	0	0
T3	484294	484281	0	0
T5	10189	9967	0	0
T6	99520	98704	0	0
T7	78249	76783	0	0
T8	77372	77163	0	0
T10	4528	4451	0	0
T11	16448	16247	0	0
T12	22226	21935	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468048268	204763269	0	0
T6	99520	17223	0	0
T7	78249	8399	0	0
T9	136888	838438	0	0
T19	86488	12673	0	0
T20	0	97710	0	0
T38	19098	0	0	0
T41	29036	1515	0	0
T64	15569	0	0	0
T68	26251	0	0	0
T93	24473	16064	0	0
T94	6145	0	0	0
T100	0	6042	0	0
T103	0	5451	0	0
T176	0	43971	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468048268	467164347	0	0
T1	10618	10374	0	0
T2	22997	22412	0	0
T3	484294	484281	0	0
T5	10189	9967	0	0
T6	99520	98704	0	0
T7	78249	76783	0	0
T8	77372	77163	0	0
T10	4528	4451	0	0
T11	16448	16247	0	0
T12	22226	21935	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468048268	467164347	0	0
T1	10618	10374	0	0
T2	22997	22412	0	0
T3	484294	484281	0	0
T5	10189	9967	0	0
T6	99520	98704	0	0
T7	78249	76783	0	0
T8	77372	77163	0	0
T10	4528	4451	0	0
T11	16448	16247	0	0
T12	22226	21935	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468048268	8144	0	0
T3	484294	23	0	0
T5	10189	0	0	0
T6	99520	1	0	0
T7	78249	13	0	0
T8	77372	14	0	0
T9	0	27	0	0
T10	4528	0	0	0
T11	16448	0	0	0
T12	22226	0	0	0
T19	86488	6	0	0
T41	0	3	0	0
T68	26251	2	0	0
T93	0	5	0	0
T176	0	6	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468048268	467164347	0	0
T1	10618	10374	0	0
T2	22997	22412	0	0
T3	484294	484281	0	0
T5	10189	9967	0	0
T6	99520	98704	0	0
T7	78249	76783	0	0
T8	77372	77163	0	0
T10	4528	4451	0	0
T11	16448	16247	0	0
T12	22226	21935	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468048268	467164347	0	0
T1	10618	10374	0	0
T2	22997	22412	0	0
T3	484294	484281	0	0
T5	10189	9967	0	0
T6	99520	98704	0	0
T7	78249	76783	0	0
T8	77372	77163	0	0
T10	4528	4451	0	0
T11	16448	16247	0	0
T12	22226	21935	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468048268	2419732	0	0
T6	99520	13614	0	0
T7	78249	1098	0	0
T9	136888	0	0	0
T14	0	19190	0	0
T19	86488	23213	0	0
T20	0	10784	0	0
T21	0	422	0	0
T38	19098	0	0	0
T41	29036	0	0	0
T64	15569	0	0	0
T68	26251	0	0	0
T88	0	7830	0	0
T89	0	275	0	0
T90	0	3933	0	0
T93	24473	0	0	0
T94	6145	0	0	0
T136	0	8353	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468048268	27625353	0	0
T6	99520	71965	0	0
T7	78249	60636	0	0
T9	136888	0	0	0
T19	86488	71623	0	0
T20	0	150298	0	0
T21	0	25343	0	0
T38	19098	0	0	0
T41	29036	18904	0	0
T64	15569	0	0	0
T68	26251	3196	0	0
T93	24473	2662	0	0
T94	6145	0	0	0
T95	0	3794	0	0
T176	0	4228	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468048268	467164347	0	0
T1	10618	10374	0	0
T2	22997	22412	0	0
T3	484294	484281	0	0
T5	10189	9967	0	0
T6	99520	98704	0	0
T7	78249	76783	0	0
T8	77372	77163	0	0
T10	4528	4451	0	0
T11	16448	16247	0	0
T12	22226	21935	0	0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T39,T115,T126

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T47,T141,T42

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T11
1	Covered	T28,T29,T30

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T145,T146
1	Covered	T145,T146

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T11
1	Covered	T1,T3,T11

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T6
1	1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b11001010000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T19

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T19

---

FSM Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T3,T11
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T2,T3
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T3,T11,T8
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T1,T107,T144
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T95,T137,T142
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T3,T6,T7
ReadSt->ReadWaitSt	252	Covered	T1,T2,T3
ReadWaitSt->ErrorSt	276	Covered	T148,T141,T189
ReadWaitSt->IdleSt	270	Covered	T1,T2,T3
ResetSt->ErrorSt	315	Covered	T68,T14,T69
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T3,T6,T7
CheckFailError	317	Covered	T145,T146
FsmStateError	289	Covered	T1,T3,T11
MacroEccCorrError	221	Covered	T39,T47,T141
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T3,T9,T15
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T6,T7,T19
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T145,T146
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T3,T11
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T39,T141,T115
MacroEccCorrError->NoError	235	Covered	T47,T42,T48
NoError->AccessError	256	Covered	T3,T6,T7
NoError->CheckFailError	317	Covered	T145,T146
NoError->FsmStateError	289	Covered	T1,T11,T8
NoError->MacroEccCorrError	221	Covered	T39,T47,T141

---

Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T39,T115,T126
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T137,T190,T191
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T7,T41,T20
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T3,T6,T7
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T47,T141,T42
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T148,T141,T189
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T28,T29,T30
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T3,T11
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T3,T8,T68
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T3,T8,T68
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T3,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T28,T29,T30

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T145,T146
1	0	Covered	T145,T146
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T3,T11
1	0	Covered	T1,T3,T11
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	468048268	467164347	0	0
DigestKnown_A	468048268	467164347	0	0
DigestOffsetMustBeRepresentable_A	1149	1149	0	0
EccErrorState_A	468048268	4644	0	0
ErrorKnown_A	468048268	467164347	0	0
FsmStateKnown_A	468048268	467164347	0	0
InitDoneKnown_A	468048268	467164347	0	0
InitReadLocksPartition_A	468048268	105832145	0	0
InitWriteLocksPartition_A	468048268	105832145	0	0
OffsetMustBeBlockAligned_A	1149	1149	0	0
OtpAddrKnown_A	468048268	467164347	0	0
OtpCmdKnown_A	468048268	467164347	0	0
OtpErrorState_A	468048268	36	0	0
OtpReqKnown_A	468048268	467164347	0	0
OtpSizeKnown_A	468048268	467164347	0	0
OtpWdataKnown_A	468048268	467164347	0	0
ReadLockPropagation_A	468048268	206783538	0	0
SizeMustBeBlockAligned_A	1149	1149	0	0
TlulGntKnown_A	468048268	467164347	0	0
TlulRdataKnown_A	468048268	467164347	0	0
TlulReadOnReadLock_A	468048268	7806	0	0
TlulRerrorKnown_A	468048268	467164347	0	0
TlulRvalidKnown_A	468048268	467164347	0	0
WriteLockPropagation_A	468048268	866831	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	468048268	10220631	0	0
u_state_regs_A	468048268	467164347	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468048268	467164347	0	0
T1	10618	10374	0	0
T2	22997	22412	0	0
T3	484294	484281	0	0
T5	10189	9967	0	0
T6	99520	98704	0	0
T7	78249	76783	0	0
T8	77372	77163	0	0
T10	4528	4451	0	0
T11	16448	16247	0	0
T12	22226	21935	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468048268	467164347	0	0
T1	10618	10374	0	0
T2	22997	22412	0	0
T3	484294	484281	0	0
T5	10189	9967	0	0
T6	99520	98704	0	0
T7	78249	76783	0	0
T8	77372	77163	0	0
T10	4528	4451	0	0
T11	16448	16247	0	0
T12	22226	21935	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468048268	4644	0	0
T145	13381	2478	0	0
T146	0	2166	0	0
T157	11169	0	0	0
T158	873109	0	0	0
T159	23848	0	0	0
T160	456813	0	0	0
T161	260569	0	0	0
T162	191728	0	0	0
T163	36938	0	0	0
T164	737643	0	0	0
T165	923349	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468048268	467164347	0	0
T1	10618	10374	0	0
T2	22997	22412	0	0
T3	484294	484281	0	0
T5	10189	9967	0	0
T6	99520	98704	0	0
T7	78249	76783	0	0
T8	77372	77163	0	0
T10	4528	4451	0	0
T11	16448	16247	0	0
T12	22226	21935	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468048268	467164347	0	0
T1	10618	10374	0	0
T2	22997	22412	0	0
T3	484294	484281	0	0
T5	10189	9967	0	0
T6	99520	98704	0	0
T7	78249	76783	0	0
T8	77372	77163	0	0
T10	4528	4451	0	0
T11	16448	16247	0	0
T12	22226	21935	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468048268	467164347	0	0
T1	10618	10374	0	0
T2	22997	22412	0	0
T3	484294	484281	0	0
T5	10189	9967	0	0
T6	99520	98704	0	0
T7	78249	76783	0	0
T8	77372	77163	0	0
T10	4528	4451	0	0
T11	16448	16247	0	0
T12	22226	21935	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468048268	105832145	0	0
T1	10618	4687	0	0
T2	22997	712	0	0
T3	484294	725939	0	0
T5	10189	415	0	0
T6	99520	1494	0	0
T7	78249	5775	0	0
T8	77372	57215	0	0
T10	4528	105	0	0
T11	16448	3764	0	0
T12	22226	9304	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468048268	105832145	0	0
T1	10618	4687	0	0
T2	22997	712	0	0
T3	484294	725939	0	0
T5	10189	415	0	0
T6	99520	1494	0	0
T7	78249	5775	0	0
T8	77372	57215	0	0
T10	4528	105	0	0
T11	16448	3764	0	0
T12	22226	9304	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468048268	467164347	0	0
T1	10618	10374	0	0
T2	22997	22412	0	0
T3	484294	484281	0	0
T5	10189	9967	0	0
T6	99520	98704	0	0
T7	78249	76783	0	0
T8	77372	77163	0	0
T10	4528	4451	0	0
T11	16448	16247	0	0
T12	22226	21935	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468048268	467164347	0	0
T1	10618	10374	0	0
T2	22997	22412	0	0
T3	484294	484281	0	0
T5	10189	9967	0	0
T6	99520	98704	0	0
T7	78249	76783	0	0
T8	77372	77163	0	0
T10	4528	4451	0	0
T11	16448	16247	0	0
T12	22226	21935	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468048268	36	0	0
T25	10532	0	0	0
T45	17425	0	0	0
T70	10608	0	0	0
T89	77187	0	0	0
T137	9245	1	0	0
T141	0	1	0	0
T147	13074	0	0	0
T148	0	1	0	0
T166	11201	0	0	0
T179	25271	0	0	0
T180	89083	0	0	0
T182	0	1	0	0
T189	0	1	0	0
T190	0	1	0	0
T191	0	1	0	0
T192	0	1	0	0
T193	0	1	0	0
T194	0	1	0	0
T195	31688	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468048268	467164347	0	0
T1	10618	10374	0	0
T2	22997	22412	0	0
T3	484294	484281	0	0
T5	10189	9967	0	0
T6	99520	98704	0	0
T7	78249	76783	0	0
T8	77372	77163	0	0
T10	4528	4451	0	0
T11	16448	16247	0	0
T12	22226	21935	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468048268	467164347	0	0
T1	10618	10374	0	0
T2	22997	22412	0	0
T3	484294	484281	0	0
T5	10189	9967	0	0
T6	99520	98704	0	0
T7	78249	76783	0	0
T8	77372	77163	0	0
T10	4528	4451	0	0
T11	16448	16247	0	0
T12	22226	21935	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468048268	467164347	0	0
T1	10618	10374	0	0
T2	22997	22412	0	0
T3	484294	484281	0	0
T5	10189	9967	0	0
T6	99520	98704	0	0
T7	78249	76783	0	0
T8	77372	77163	0	0
T10	4528	4451	0	0
T11	16448	16247	0	0
T12	22226	21935	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468048268	206783538	0	0
T3	484294	736556	0	0
T5	10189	0	0	0
T6	99520	17107	0	0
T7	78249	8072	0	0
T8	77372	59497	0	0
T9	0	840137	0	0
T10	4528	0	0	0
T11	16448	0	0	0
T12	22226	0	0	0
T19	86488	13383	0	0
T41	0	1323	0	0
T68	26251	0	0	0
T93	0	16057	0	0
T100	0	6035	0	0
T103	0	5448	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468048268	467164347	0	0
T1	10618	10374	0	0
T2	22997	22412	0	0
T3	484294	484281	0	0
T5	10189	9967	0	0
T6	99520	98704	0	0
T7	78249	76783	0	0
T8	77372	77163	0	0
T10	4528	4451	0	0
T11	16448	16247	0	0
T12	22226	21935	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468048268	467164347	0	0
T1	10618	10374	0	0
T2	22997	22412	0	0
T3	484294	484281	0	0
T5	10189	9967	0	0
T6	99520	98704	0	0
T7	78249	76783	0	0
T8	77372	77163	0	0
T10	4528	4451	0	0
T11	16448	16247	0	0
T12	22226	21935	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468048268	7806	0	0
T3	484294	20	0	0
T5	10189	0	0	0
T6	99520	5	0	0
T7	78249	12	0	0
T8	77372	9	0	0
T9	0	27	0	0
T10	4528	0	0	0
T11	16448	0	0	0
T12	22226	0	0	0
T19	86488	3	0	0
T68	26251	2	0	0
T93	0	1	0	0
T103	0	2	0	0
T176	0	15	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468048268	467164347	0	0
T1	10618	10374	0	0
T2	22997	22412	0	0
T3	484294	484281	0	0
T5	10189	9967	0	0
T6	99520	98704	0	0
T7	78249	76783	0	0
T8	77372	77163	0	0
T10	4528	4451	0	0
T11	16448	16247	0	0
T12	22226	21935	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468048268	467164347	0	0
T1	10618	10374	0	0
T2	22997	22412	0	0
T3	484294	484281	0	0
T5	10189	9967	0	0
T6	99520	98704	0	0
T7	78249	76783	0	0
T8	77372	77163	0	0
T10	4528	4451	0	0
T11	16448	16247	0	0
T12	22226	21935	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468048268	866831	0	0
T6	99520	13670	0	0
T7	78249	5717	0	0
T9	136888	0	0	0
T14	0	3826	0	0
T19	86488	12141	0	0
T20	0	30789	0	0
T38	19098	0	0	0
T41	29036	0	0	0
T47	0	2477	0	0
T63	0	934	0	0
T64	15569	0	0	0
T68	26251	0	0	0
T93	24473	0	0	0
T94	6145	0	0	0
T97	0	14634	0	0
T125	0	8439	0	0
T136	0	3071	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468048268	10220631	0	0
T6	99520	85017	0	0
T7	78249	60381	0	0
T9	136888	0	0	0
T14	0	84276	0	0
T19	86488	71504	0	0
T20	0	145162	0	0
T38	19098	0	0	0
T41	29036	18802	0	0
T64	15569	0	0	0
T68	26251	3162	0	0
T93	24473	0	0	0
T94	6145	0	0	0
T137	0	3406	0	0
T176	0	4194	0	0
T181	0	4884	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468048268	467164347	0	0
T1	10618	10374	0	0
T2	22997	22412	0	0
T3	484294	484281	0	0
T5	10189	9967	0	0
T6	99520	98704	0	0
T7	78249	76783	0	0
T8	77372	77163	0	0
T10	4528	4451	0	0
T11	16448	16247	0	0
T12	22226	21935	0	0