Unified Coverage Report :: Module :: otp_ctrl_part_unbuf

Module : otp_ctrl_part_unbuf

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.82	98.49	96.36		64.71	94.57	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf	97.23	100.00	100.00		90.00	100.00	96.15
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf	97.75	100.00	97.06		91.67	100.00	100.00
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf	98.33	100.00	100.00		91.67	100.00	100.00
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf	98.33	100.00	100.00		91.67	100.00	100.00
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf	98.33	100.00	100.00		91.67	100.00	100.00

Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=65616,DigestOffset=56,StateWidth=10 )
Line Coverage for Module self-instances :

SCORE	LINE
97.23	100.00

tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		93	86	92.47
CONT_ASSIGN	138	1	1	100.00
ALWAYS	153	3	3	100.00
ALWAYS	164	68	61	89.71
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
153	1	1
154	1	1
156	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			==> MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	0	1
			MISSING_ELSE
224	0	1
225	0	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	0	1
			MISSING_ELSE
276	0	1
277	0	1
279	0	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
339	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=134643796,DigestOffset=472,StateWidth=10 )
Line Coverage for Module self-instances :

SCORE	LINE
98.33	100.00

tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=1007312980,DigestOffset=1136,StateWidth=10 )
Line Coverage for Module self-instances :

SCORE	LINE
97.75	100.00

tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=-1,DigestOffset=1608,StateWidth=10 )
Line Coverage for Module self-instances :

SCORE	LINE
98.33	100.00

tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=-1,DigestOffset=1648,StateWidth=10 )
Line Coverage for Module self-instances :

SCORE	LINE
98.33	100.00

tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=1007312980,DigestOffset=1136,StateWidth=10 )
Cond Coverage for Module self-instances :

SCORE	COND
97.75	97.06

tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	34	33	97.06
Logical	34	33	97.06
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T64,T43,T139

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T11,T140,T141

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T9,T21,T22

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T142,T143,T144
1	Covered	T142,T143,T144

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T3,T5,T6

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T1,T2,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00111100000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T6

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T6

---

Cond Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=-1,DigestOffset=1608,StateWidth=10 )
Cond Coverage for Module self-instances :

SCORE	COND
98.33	100.00

tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	34	33	97.06
Logical	34	33	97.06
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T64,T43,T113

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T145,T67,T146

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T9,T21,T22

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T70,T71,T142
1	Covered	T70,T71,T142

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T5

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T1,T2,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b10001111000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T147

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T147

---

Cond Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=65616,DigestOffset=56,StateWidth=10 )
Cond Coverage for Module self-instances :

SCORE	COND
97.23	100.00

tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	31	29	93.55
Logical	31	29	93.55
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Not Covered

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T9,T21,T22

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T148,T142,T149
1	Covered	T148,T142,T149

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T5

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T1,T2,T5

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T6

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T6

---

Cond Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=134643796,DigestOffset=472,StateWidth=10 )
Cond Coverage for Module self-instances :

SCORE	COND
98.33	100.00

tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	34	33	97.06
Logical	34	33	97.06
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T150,T151,T152

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T32,T145,T67

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T9,T21,T22

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T70,T71,T153
1	Covered	T70,T71,T153

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T5

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T2,T4,T5

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T61

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T61

---

Cond Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=-1,DigestOffset=1648,StateWidth=10 )
Cond Coverage for Module self-instances :

SCORE	COND
98.33	100.00

tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	34	33	97.06
Logical	34	33	97.06
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T63,T74,T23

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T11,T104,T44

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T9,T21,T22

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T148,T153,T149
1	Covered	T148,T153,T149

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T5

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T1,T2,T5

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b11001010000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T154

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T154

---

FSM Coverage for Module : otp_ctrl_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T3,T5
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T4
ReadWaitSt	252	Covered	T1,T2,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
IdleSt->ErrorSt	315	Covered	T2,T3,T5
IdleSt->ReadSt	236	Covered	T1,T2,T4
InitSt->ErrorSt	315	Covered	T61,T62,T154
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T2,T61,T62
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T5,T6,T7
ReadSt->ReadWaitSt	252	Covered	T1,T2,T4
ReadWaitSt->ErrorSt	276	Covered	T104,T155,T156
ReadWaitSt->IdleSt	270	Covered	T1,T2,T4
ResetSt->ErrorSt	315	Covered	T7,T70,T71
ResetSt->IdleSt	196	Not Covered
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	20	10	50.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T5,T6,T7
CheckFailError	317	Covered	T70,T71,T148
FsmStateError	289	Covered	T2,T3,T5
MacroEccCorrError	221	Covered	T11,T64,T140
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AccessError->CheckFailError	317	Not Covered
AccessError->FsmStateError	325	Covered	T5,T6,T7
AccessError->MacroEccCorrError	221	Not Covered
AccessError->NoError	235	Covered	T5,T6,T7
CheckFailError->AccessError	256	Not Covered
CheckFailError->FsmStateError	325	Not Covered
CheckFailError->MacroEccCorrError	221	Not Covered
CheckFailError->NoError	235	Covered	T70,T71,T148
FsmStateError->AccessError	256	Not Covered
FsmStateError->CheckFailError	317	Not Covered
FsmStateError->MacroEccCorrError	221	Not Covered
FsmStateError->NoError	235	Covered	T2,T3,T5
MacroEccCorrError->AccessError	256	Not Covered
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T63,T64,T140
MacroEccCorrError->NoError	235	Covered	T11,T32,T67
NoError->AccessError	256	Covered	T5,T6,T7
NoError->CheckFailError	317	Covered	T70,T71,T148
NoError->FsmStateError	289	Covered	T2,T3,T5
NoError->MacroEccCorrError	221	Covered	T11,T64,T140

---

Branch Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=65616,DigestOffset=56,StateWidth=10 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
97.23	100.00

tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		46	41	89.13
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	18	78.26
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00
IF	153	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T5
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T96,T106,T130
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T5,T6,T7
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T5
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T9,T21,T22
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T3,T5,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T3,T5,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T5
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T21,T22

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T148,T142,T149
1	0	Covered	T148,T142,T149
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	if ((otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}))

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T6
0	Covered	T1,T2,T3

---

Branch Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=134643796,DigestOffset=472,StateWidth=10 + Info=1007312980,DigestOffset=1136,StateWidth=10 + Info=-1,DigestOffset=1608,StateWidth=10 + Info=-1,DigestOffset=1648,StateWidth=10 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.33	100.00

tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

SCORE	BRANCH
97.75	100.00

tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

SCORE	BRANCH
98.33	100.00

tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

SCORE	BRANCH
98.33	100.00

tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T64,T150,T43
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T2,T61,T62
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T7,T96,T106
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T5,T6,T7
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T11,T140,T32
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T104,T155,T156
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T9,T21,T22
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T3,T5,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T3,T5,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T5
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T21,T22

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T70,T71,T148
1	0	Covered	T70,T71,T148
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : otp_ctrl_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	2147483647	2147483647	0	0
DigestKnown_A	2147483647	2147483647	0	0
DigestOffsetMustBeRepresentable_A	5735	5735	0	0
EccErrorState_A	2147483647	82165	0	0
ErrorKnown_A	2147483647	2147483647	0	0
FsmStateKnown_A	2147483647	2147483647	0	0
InitDoneKnown_A	2147483647	2147483647	0	0
InitReadLocksPartition_A	2147483647	472152910	0	0
InitWriteLocksPartition_A	2147483647	472152910	0	0
OffsetMustBeBlockAligned_A	5735	5735	0	0
OtpAddrKnown_A	2147483647	2147483647	0	0
OtpCmdKnown_A	2147483647	2147483647	0	0
OtpErrorState_A	2147483647	199	0	0
OtpReqKnown_A	2147483647	2147483647	0	0
OtpSizeKnown_A	2147483647	2147483647	0	0
OtpWdataKnown_A	2147483647	2147483647	0	0
ReadLockPropagation_A	2147483647	1065320325	0	0
SizeMustBeBlockAligned_A	5735	5735	0	0
TlulGntKnown_A	2147483647	2147483647	0	0
TlulRdataKnown_A	2147483647	2147483647	0	0
TlulReadOnReadLock_A	2147483647	39479	0	0
TlulRerrorKnown_A	2147483647	2147483647	0	0
TlulRvalidKnown_A	2147483647	2147483647	0	0
WriteLockPropagation_A	2147483647	8490645	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	2147483647	103525445	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	83945	82365	0	0
T2	55605	54335	0	0
T3	303510	302660	0	0
T4	52310	51430	0	0
T5	1475775	1475635	0	0
T6	678305	673780	0	0
T8	130905	127995	0	0
T9	570100	558770	0	0
T10	78175	76845	0	0
T11	821565	816025	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	83945	82365	0	0
T2	55605	54335	0	0
T3	303510	302660	0	0
T4	52310	51430	0	0
T5	1475775	1475635	0	0
T6	678305	673780	0	0
T8	130905	127995	0	0
T9	570100	558770	0	0
T10	78175	76845	0	0
T11	821565	816025	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5735	5735	0	0
T1	5	5	0	0
T2	5	5	0	0
T3	5	5	0	0
T4	5	5	0	0
T5	5	5	0	0
T6	5	5	0	0
T8	5	5	0	0
T9	5	5	0	0
T10	5	5	0	0
T11	5	5	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	82165	0	0
T12	603209	0	0	0
T44	41584	0	0	0
T64	12759	0	0	0
T70	8671	6766	0	0
T71	0	6336	0	0
T74	14901	0	0	0
T96	87698	0	0	0
T106	35785	0	0	0
T130	35264	0	0	0
T142	10459	8226	0	0
T143	0	18770	0	0
T144	0	5546	0	0
T148	9320	5692	0	0
T149	0	6866	0	0
T153	0	6652	0	0
T156	96371	0	0	0
T157	0	6154	0	0
T158	0	11157	0	0
T159	12552	0	0	0
T160	4457	0	0	0
T161	7889	0	0	0
T162	96446	0	0	0
T163	23487	0	0	0
T164	565624	0	0	0
T165	17960	0	0	0
T166	22880	0	0	0
T167	43091	0	0	0
T168	17669	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	83945	82365	0	0
T2	55605	54335	0	0
T3	303510	302660	0	0
T4	52310	51430	0	0
T5	1475775	1475635	0	0
T6	678305	673780	0	0
T8	130905	127995	0	0
T9	570100	558770	0	0
T10	78175	76845	0	0
T11	821565	816025	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	83945	82365	0	0
T2	55605	54335	0	0
T3	303510	302660	0	0
T4	52310	51430	0	0
T5	1475775	1475635	0	0
T6	678305	673780	0	0
T8	130905	127995	0	0
T9	570100	558770	0	0
T10	78175	76845	0	0
T11	821565	816025	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	83945	82365	0	0
T2	55605	54335	0	0
T3	303510	302660	0	0
T4	52310	51430	0	0
T5	1475775	1475635	0	0
T6	678305	673780	0	0
T8	130905	127995	0	0
T9	570100	558770	0	0
T10	78175	76845	0	0
T11	821565	816025	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	472152910	0	0
T1	83945	1165	0	0
T2	55605	21464	0	0
T3	303510	265185	0	0
T4	52310	1355	0	0
T5	1475775	4255380	0	0
T6	678305	864417	0	0
T8	130905	2985	0	0
T9	570100	1423700	0	0
T10	78175	22850	0	0
T11	821565	42050	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	472152910	0	0
T1	83945	1165	0	0
T2	55605	21464	0	0
T3	303510	265185	0	0
T4	52310	1355	0	0
T5	1475775	4255380	0	0
T6	678305	864417	0	0
T8	130905	2985	0	0
T9	570100	1423700	0	0
T10	78175	22850	0	0
T11	821565	42050	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5735	5735	0	0
T1	5	5	0	0
T2	5	5	0	0
T3	5	5	0	0
T4	5	5	0	0
T5	5	5	0	0
T6	5	5	0	0
T8	5	5	0	0
T9	5	5	0	0
T10	5	5	0	0
T11	5	5	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	83945	82365	0	0
T2	55605	54335	0	0
T3	303510	302660	0	0
T4	52310	51430	0	0
T5	1475775	1475635	0	0
T6	678305	673780	0	0
T8	130905	127995	0	0
T9	570100	558770	0	0
T10	78175	76845	0	0
T11	821565	816025	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	83945	82365	0	0
T2	55605	54335	0	0
T3	303510	302660	0	0
T4	52310	51430	0	0
T5	1475775	1475635	0	0
T6	678305	673780	0	0
T8	130905	127995	0	0
T9	570100	558770	0	0
T10	78175	76845	0	0
T11	821565	816025	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	199	0	0
T2	11121	1	0	0
T3	60702	0	0	0
T4	10462	0	0	0
T5	295155	0	0	0
T6	135661	0	0	0
T7	423612	0	0	0
T8	26181	0	0	0
T9	114020	0	0	0
T10	15635	0	0	0
T11	164313	0	0	0
T57	26464	0	0	0
T61	32252	1	0	0
T62	13905	1	0	0
T63	11473	0	0	0
T103	25353	0	0	0
T104	237848	1	0	0
T147	53162	0	0	0
T150	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T154	25877	0	0	0
T155	0	2	0	0
T159	0	1	0	0
T162	0	1	0	0
T169	9845	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0
T174	0	1	0	0
T175	0	1	0	0
T176	0	1	0	0
T177	0	1	0	0
T178	0	1	0	0
T179	0	1	0	0
T180	119442	0	0	0
T181	51738	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	83945	82365	0	0
T2	55605	54335	0	0
T3	303510	302660	0	0
T4	52310	51430	0	0
T5	1475775	1475635	0	0
T6	678305	673780	0	0
T8	130905	127995	0	0
T9	570100	558770	0	0
T10	78175	76845	0	0
T11	821565	816025	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	83945	82365	0	0
T2	55605	54335	0	0
T3	303510	302660	0	0
T4	52310	51430	0	0
T5	1475775	1475635	0	0
T6	678305	673780	0	0
T8	130905	127995	0	0
T9	570100	558770	0	0
T10	78175	76845	0	0
T11	821565	816025	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	83945	82365	0	0
T2	55605	54335	0	0
T3	303510	302660	0	0
T4	52310	51430	0	0
T5	1475775	1475635	0	0
T6	678305	673780	0	0
T8	130905	127995	0	0
T9	570100	558770	0	0
T10	78175	76845	0	0
T11	821565	816025	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1065320325	0	0
T3	121404	106928	0	0
T4	20924	0	0	0
T5	1475775	833574	0	0
T6	678305	1467844	0	0
T7	1270836	687800	0	0
T8	130905	0	0	0
T9	570100	0	0	0
T10	78175	0	0	0
T11	821565	20607	0	0
T31	0	20826	0	0
T61	80630	0	0	0
T62	41715	0	0	0
T96	0	11748	0	0
T103	126765	0	0	0
T105	0	87388	0	0
T106	0	10080	0	0
T108	0	19581	0	0
T147	0	71520	0	0
T154	0	11570	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5735	5735	0	0
T1	5	5	0	0
T2	5	5	0	0
T3	5	5	0	0
T4	5	5	0	0
T5	5	5	0	0
T6	5	5	0	0
T8	5	5	0	0
T9	5	5	0	0
T10	5	5	0	0
T11	5	5	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	83945	82365	0	0
T2	55605	54335	0	0
T3	303510	302660	0	0
T4	52310	51430	0	0
T5	1475775	1475635	0	0
T6	678305	673780	0	0
T8	130905	127995	0	0
T9	570100	558770	0	0
T10	78175	76845	0	0
T11	821565	816025	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	83945	82365	0	0
T2	55605	54335	0	0
T3	303510	302660	0	0
T4	52310	51430	0	0
T5	1475775	1475635	0	0
T6	678305	673780	0	0
T8	130905	127995	0	0
T9	570100	558770	0	0
T10	78175	76845	0	0
T11	821565	816025	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	39479	0	0
T3	303510	74	0	0
T4	52310	0	0	0
T5	1475775	160	0	0
T6	678305	262	0	0
T7	0	202	0	0
T8	130905	0	0	0
T9	570100	254	0	0
T10	78175	0	0	0
T11	821565	2	0	0
T61	80630	0	0	0
T103	126765	0	0	0
T104	0	30	0	0
T108	0	12	0	0
T147	0	18	0	0
T154	0	5	0	0
T180	0	38	0	0
T181	0	68	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	83945	82365	0	0
T2	55605	54335	0	0
T3	303510	302660	0	0
T4	52310	51430	0	0
T5	1475775	1475635	0	0
T6	678305	673780	0	0
T8	130905	127995	0	0
T9	570100	558770	0	0
T10	78175	76845	0	0
T11	821565	816025	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	83945	82365	0	0
T2	55605	54335	0	0
T3	303510	302660	0	0
T4	52310	51430	0	0
T5	1475775	1475635	0	0
T6	678305	673780	0	0
T8	130905	127995	0	0
T9	570100	558770	0	0
T10	78175	76845	0	0
T11	821565	816025	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8490645	0	0
T6	678305	251773	0	0
T7	2118060	29127	0	0
T9	570100	0	0	0
T10	78175	0	0	0
T11	821565	0	0	0
T31	0	46753	0	0
T44	0	4468	0	0
T60	0	49460	0	0
T61	80630	0	0	0
T62	69525	0	0	0
T63	57365	0	0	0
T67	0	7794	0	0
T96	0	5980	0	0
T97	0	8105	0	0
T98	0	36572	0	0
T99	0	4442	0	0
T100	0	109315	0	0
T102	0	63012	0	0
T103	126765	0	0	0
T104	594620	0	0	0
T105	0	9492	0	0
T106	0	5335	0	0
T107	0	43644	0	0
T130	0	6152	0	0
T131	0	12410	0	0
T182	0	16548	0	0
T183	0	34494	0	0
T184	0	30139	0	0
T185	0	5491	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	103525445	0	0
T2	22242	5562	0	0
T3	121404	0	0	0
T4	31386	12654	0	0
T5	885465	0	0	0
T6	678305	2301110	0	0
T7	1270836	390339	0	0
T8	78543	0	0	0
T9	570100	0	0	0
T10	78175	0	0	0
T11	821565	0	0	0
T31	0	347056	0	0
T44	0	69086	0	0
T60	0	38602	0	0
T61	80630	2273	0	0
T62	27810	4014	0	0
T63	22946	3076	0	0
T96	0	141935	0	0
T97	0	50049	0	0
T103	76059	0	0	0
T104	237848	0	0	0
T105	0	104778	0	0
T106	0	54615	0	0
T108	0	9780	0	0
T130	0	24309	0	0
T147	0	10730	0	0
T154	0	10200	0	0
T169	0	2422	0	0
T182	0	25753	0	0
T186	0	3121	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	83945	82365	0	0
T2	55605	54335	0	0
T3	303510	302660	0	0
T4	52310	51430	0	0
T5	1475775	1475635	0	0
T6	678305	673780	0	0
T8	130905	127995	0	0
T9	570100	558770	0	0
T10	78175	76845	0	0
T11	821565	816025	0	0