Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.23	100.00	100.00		90.00	100.00	96.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.56	100.00	100.00	100.00	90.00	98.15	97.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.81	97.40	96.15	96.90		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.81	97.40	96.15	96.90		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.75	100.00	97.06		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.83	100.00	97.06	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.81	97.40	96.15	96.90		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		86	86	100.00
CONT_ASSIGN	138	1	1	100.00
ALWAYS	153	3	3	100.00
ALWAYS	164	61	61	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
153	1	1
154	1	1
156	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			==> MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
224		excluded
			Exclude Annotation: VC_COV_UNR
225		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
276		excluded
			Exclude Annotation: VC_COV_UNR
277		excluded
			Exclude Annotation: VC_COV_UNR
279		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
339	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	29	29	100.00
Logical	29	29	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T5
1	Excluded		VC_COV_UNR

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T9,T21,T22

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T148,T142,T149
1	Covered	T148,T142,T149

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T5

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T1,T2,T5

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T6

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T6

---

FSM Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	11	84.62
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T3,T5
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T5
ReadWaitSt	252	Covered	T1,T2,T5
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T3,T5
IdleSt->ReadSt	236	Covered	T1,T2,T5
InitSt->ErrorSt	315	Covered	T187
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T154,T60,T188
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T5,T6,T7
ReadSt->ReadWaitSt	252	Covered	T1,T2,T5
ReadWaitSt->ErrorSt	276	Not Covered
ReadWaitSt->IdleSt	270	Covered	T1,T2,T5
ResetSt->ErrorSt	315	Covered	T7,T70,T71
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests	Exclude Annotation
AccessError	256	Covered	T5,T6,T7
CheckFailError	317	Covered	T148,T142,T149
FsmStateError	289	Covered	T2,T3,T5
MacroEccCorrError	221	Excluded		VC_COV_UNR
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded
AccessError->FsmStateError	325	Covered	T5,T6,T7
AccessError->MacroEccCorrError	221	Excluded
AccessError->NoError	235	Covered	T5,T6,T7
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded
CheckFailError->NoError	235	Covered	T148,T142,T149
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded
FsmStateError->NoError	235	Covered	T2,T3,T5
MacroEccCorrError->AccessError	256	Excluded
MacroEccCorrError->CheckFailError	317	Excluded
MacroEccCorrError->FsmStateError	325	Excluded
MacroEccCorrError->NoError	235	Excluded
NoError->AccessError	256	Covered	T5,T6,T7
NoError->CheckFailError	317	Covered	T148,T142,T149
NoError->FsmStateError	289	Covered	T2,T3,T6
NoError->MacroEccCorrError	221	Excluded

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	18	18	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00
IF	153	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests	Exclude Annotation
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T5
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T96,T106,T130
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T5,T6,T7
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T5
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T9,T21,T22
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T3,T5,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T3,T5,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T5
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T21,T22

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T148,T142,T149
1	0	Covered	T148,T142,T149
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	if ((otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}))

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	461541576	460690025	0	0
DigestKnown_A	461541576	460690025	0	0
DigestOffsetMustBeRepresentable_A	1147	1147	0	0
EccErrorState_A	461541576	16494	0	0
ErrorKnown_A	461541576	460690025	0	0
FsmStateKnown_A	461541576	460690025	0	0
InitDoneKnown_A	461541576	460690025	0	0
InitReadLocksPartition_A	461541576	94075026	0	0
InitWriteLocksPartition_A	461541576	94075026	0	0
OffsetMustBeBlockAligned_A	1147	1147	0	0
OtpAddrKnown_A	461541576	460690025	0	0
OtpCmdKnown_A	461541576	460690025	0	0
OtpErrorState_A	461541576	0	0	0
OtpReqKnown_A	461541576	460690025	0	0
OtpSizeKnown_A	461541576	460690025	0	0
OtpWdataKnown_A	461541576	460690025	0	0
ReadLockPropagation_A	461541576	220801153	0	0
SizeMustBeBlockAligned_A	1147	1147	0	0
TlulGntKnown_A	461541576	460690025	0	0
TlulRdataKnown_A	461541576	460690025	0	0
TlulReadOnReadLock_A	461541576	7733	0	0
TlulRerrorKnown_A	461541576	460690025	0	0
TlulRvalidKnown_A	461541576	460690025	0	0
WriteLockPropagation_A	461541576	2091249	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	461541576	26100377	0	0
u_state_regs_A	461541576	460690025	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	460690025	0	0
T1	16789	16473	0	0
T2	11121	10867	0	0
T3	60702	60532	0	0
T4	10462	10286	0	0
T5	295155	295127	0	0
T6	135661	134756	0	0
T8	26181	25599	0	0
T9	114020	111754	0	0
T10	15635	15369	0	0
T11	164313	163205	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	460690025	0	0
T1	16789	16473	0	0
T2	11121	10867	0	0
T3	60702	60532	0	0
T4	10462	10286	0	0
T5	295155	295127	0	0
T6	135661	134756	0	0
T8	26181	25599	0	0
T9	114020	111754	0	0
T10	15635	15369	0	0
T11	164313	163205	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147	1147	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	16494	0	0
T74	14901	0	0	0
T142	0	2742	0	0
T143	0	3754	0	0
T148	9320	2846	0	0
T149	0	3433	0	0
T156	96371	0	0	0
T158	0	3719	0	0
T162	96446	0	0	0
T163	23487	0	0	0
T164	565624	0	0	0
T165	17960	0	0	0
T166	22880	0	0	0
T167	43091	0	0	0
T168	17669	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	460690025	0	0
T1	16789	16473	0	0
T2	11121	10867	0	0
T3	60702	60532	0	0
T4	10462	10286	0	0
T5	295155	295127	0	0
T6	135661	134756	0	0
T8	26181	25599	0	0
T9	114020	111754	0	0
T10	15635	15369	0	0
T11	164313	163205	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	460690025	0	0
T1	16789	16473	0	0
T2	11121	10867	0	0
T3	60702	60532	0	0
T4	10462	10286	0	0
T5	295155	295127	0	0
T6	135661	134756	0	0
T8	26181	25599	0	0
T9	114020	111754	0	0
T10	15635	15369	0	0
T11	164313	163205	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	460690025	0	0
T1	16789	16473	0	0
T2	11121	10867	0	0
T3	60702	60532	0	0
T4	10462	10286	0	0
T5	295155	295127	0	0
T6	135661	134756	0	0
T8	26181	25599	0	0
T9	114020	111754	0	0
T10	15635	15369	0	0
T11	164313	163205	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	94075026	0	0
T1	16789	131	0	0
T2	11121	4241	0	0
T3	60702	52969	0	0
T4	10462	169	0	0
T5	295155	850634	0	0
T6	135661	169267	0	0
T8	26181	325	0	0
T9	114020	273146	0	0
T10	15635	4468	0	0
T11	164313	7968	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	94075026	0	0
T1	16789	131	0	0
T2	11121	4241	0	0
T3	60702	52969	0	0
T4	10462	169	0	0
T5	295155	850634	0	0
T6	135661	169267	0	0
T8	26181	325	0	0
T9	114020	273146	0	0
T10	15635	4468	0	0
T11	164313	7968	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147	1147	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	460690025	0	0
T1	16789	16473	0	0
T2	11121	10867	0	0
T3	60702	60532	0	0
T4	10462	10286	0	0
T5	295155	295127	0	0
T6	135661	134756	0	0
T8	26181	25599	0	0
T9	114020	111754	0	0
T10	15635	15369	0	0
T11	164313	163205	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	460690025	0	0
T1	16789	16473	0	0
T2	11121	10867	0	0
T3	60702	60532	0	0
T4	10462	10286	0	0
T5	295155	295127	0	0
T6	135661	134756	0	0
T8	26181	25599	0	0
T9	114020	111754	0	0
T10	15635	15369	0	0
T11	164313	163205	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	460690025	0	0
T1	16789	16473	0	0
T2	11121	10867	0	0
T3	60702	60532	0	0
T4	10462	10286	0	0
T5	295155	295127	0	0
T6	135661	134756	0	0
T8	26181	25599	0	0
T9	114020	111754	0	0
T10	15635	15369	0	0
T11	164313	163205	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	460690025	0	0
T1	16789	16473	0	0
T2	11121	10867	0	0
T3	60702	60532	0	0
T4	10462	10286	0	0
T5	295155	295127	0	0
T6	135661	134756	0	0
T8	26181	25599	0	0
T9	114020	111754	0	0
T10	15635	15369	0	0
T11	164313	163205	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	460690025	0	0
T1	16789	16473	0	0
T2	11121	10867	0	0
T3	60702	60532	0	0
T4	10462	10286	0	0
T5	295155	295127	0	0
T6	135661	134756	0	0
T8	26181	25599	0	0
T9	114020	111754	0	0
T10	15635	15369	0	0
T11	164313	163205	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	220801153	0	0
T3	60702	53473	0	0
T4	10462	0	0	0
T5	295155	182580	0	0
T6	135661	392261	0	0
T7	0	149765	0	0
T8	26181	0	0	0
T9	114020	0	0	0
T10	15635	0	0	0
T11	164313	0	0	0
T31	0	3907	0	0
T61	16126	0	0	0
T96	0	2934	0	0
T103	25353	0	0	0
T105	0	20760	0	0
T106	0	3907	0	0
T147	0	13373	0	0
T154	0	3002	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147	1147	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	460690025	0	0
T1	16789	16473	0	0
T2	11121	10867	0	0
T3	60702	60532	0	0
T4	10462	10286	0	0
T5	295155	295127	0	0
T6	135661	134756	0	0
T8	26181	25599	0	0
T9	114020	111754	0	0
T10	15635	15369	0	0
T11	164313	163205	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	460690025	0	0
T1	16789	16473	0	0
T2	11121	10867	0	0
T3	60702	60532	0	0
T4	10462	10286	0	0
T5	295155	295127	0	0
T6	135661	134756	0	0
T8	26181	25599	0	0
T9	114020	111754	0	0
T10	15635	15369	0	0
T11	164313	163205	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	7733	0	0
T3	60702	18	0	0
T4	10462	0	0	0
T5	295155	35	0	0
T6	135661	62	0	0
T7	0	33	0	0
T8	26181	0	0	0
T9	114020	5	0	0
T10	15635	0	0	0
T11	164313	0	0	0
T61	16126	0	0	0
T103	25353	0	0	0
T104	0	4	0	0
T147	0	4	0	0
T154	0	3	0	0
T180	0	8	0	0
T181	0	10	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	460690025	0	0
T1	16789	16473	0	0
T2	11121	10867	0	0
T3	60702	60532	0	0
T4	10462	10286	0	0
T5	295155	295127	0	0
T6	135661	134756	0	0
T8	26181	25599	0	0
T9	114020	111754	0	0
T10	15635	15369	0	0
T11	164313	163205	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	460690025	0	0
T1	16789	16473	0	0
T2	11121	10867	0	0
T3	60702	60532	0	0
T4	10462	10286	0	0
T5	295155	295127	0	0
T6	135661	134756	0	0
T8	26181	25599	0	0
T9	114020	111754	0	0
T10	15635	15369	0	0
T11	164313	163205	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	2091249	0	0
T6	135661	87389	0	0
T7	423612	10791	0	0
T9	114020	0	0	0
T10	15635	0	0	0
T11	164313	0	0	0
T60	0	25785	0	0
T61	16126	0	0	0
T62	13905	0	0	0
T63	11473	0	0	0
T96	0	5493	0	0
T97	0	1625	0	0
T98	0	3087	0	0
T100	0	24188	0	0
T103	25353	0	0	0
T104	118924	0	0	0
T105	0	9492	0	0
T130	0	3076	0	0
T182	0	4800	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	26100377	0	0
T2	11121	2792	0	0
T3	60702	0	0	0
T4	10462	4252	0	0
T5	295155	0	0	0
T6	135661	585708	0	0
T7	0	104538	0	0
T8	26181	0	0	0
T9	114020	0	0	0
T10	15635	0	0	0
T11	164313	0	0	0
T31	0	87138	0	0
T61	16126	0	0	0
T62	0	4014	0	0
T63	0	3076	0	0
T108	0	2479	0	0
T147	0	2708	0	0
T154	0	2584	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	460690025	0	0
T1	16789	16473	0	0
T2	11121	10867	0	0
T3	60702	60532	0	0
T4	10462	10286	0	0
T5	295155	295127	0	0
T6	135661	134756	0	0
T8	26181	25599	0	0
T9	114020	111754	0	0
T10	15635	15369	0	0
T11	164313	163205	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T150,T151,T152

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T32,T145,T67

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T9,T21,T22

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T70,T71,T153
1	Covered	T70,T71,T153

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T5

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T2,T4,T5

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T2,T3,T4

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T61

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T61

---

FSM Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T3,T5
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T2,T4,T5
ReadWaitSt	252	Covered	T2,T4,T5
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T3,T5
IdleSt->ReadSt	236	Covered	T2,T4,T5
InitSt->ErrorSt	315	Covered	T154,T60,T188
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T61,T62,T169
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T5,T6,T7
ReadSt->ReadWaitSt	252	Covered	T2,T4,T5
ReadWaitSt->ErrorSt	276	Covered	T162,T189,T190
ReadWaitSt->IdleSt	270	Covered	T2,T4,T5
ResetSt->ErrorSt	315	Covered	T7,T70,T71
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T5,T6,T7
CheckFailError	317	Covered	T70,T71,T153
FsmStateError	289	Covered	T2,T3,T5
MacroEccCorrError	221	Covered	T150,T32,T145
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T6,T7,T147
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T5,T6,T7
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T70,T71,T153
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T2,T3,T5
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T150,T145,T151
MacroEccCorrError->NoError	235	Covered	T32,T67,T45
NoError->AccessError	256	Covered	T5,T6,T7
NoError->CheckFailError	317	Covered	T70,T71,T153
NoError->FsmStateError	289	Covered	T2,T3,T5
NoError->MacroEccCorrError	221	Covered	T150,T32,T145

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T61
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T150,T151,T152
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T61,T62,T169
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T4,T5
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T96,T106,T130
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T5,T6,T7
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T32,T145,T67
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T4,T5
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T162,T189,T190
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T4,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T9,T21,T22
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T3,T5,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T3,T5,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T5
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T21,T22

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T70,T71,T153
1	0	Covered	T70,T71,T153
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	461541576	460690025	0	0
DigestKnown_A	461541576	460690025	0	0
DigestOffsetMustBeRepresentable_A	1147	1147	0	0
EccErrorState_A	461541576	20427	0	0
ErrorKnown_A	461541576	460690025	0	0
FsmStateKnown_A	461541576	460690025	0	0
InitDoneKnown_A	461541576	460690025	0	0
InitReadLocksPartition_A	461541576	94253956	0	0
InitWriteLocksPartition_A	461541576	94253956	0	0
OffsetMustBeBlockAligned_A	1147	1147	0	0
OtpAddrKnown_A	461541576	460690025	0	0
OtpCmdKnown_A	461541576	460690025	0	0
OtpErrorState_A	461541576	66	0	0
OtpReqKnown_A	461541576	460690025	0	0
OtpSizeKnown_A	461541576	460690025	0	0
OtpWdataKnown_A	461541576	460690025	0	0
ReadLockPropagation_A	461541576	212149986	0	0
SizeMustBeBlockAligned_A	1147	1147	0	0
TlulGntKnown_A	461541576	460690025	0	0
TlulRdataKnown_A	461541576	460690025	0	0
TlulReadOnReadLock_A	461541576	8007	0	0
TlulRerrorKnown_A	461541576	460690025	0	0
TlulRvalidKnown_A	461541576	460690025	0	0
WriteLockPropagation_A	461541576	2442426	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	461541576	25685844	0	0
u_state_regs_A	461541576	460690025	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	460690025	0	0
T1	16789	16473	0	0
T2	11121	10867	0	0
T3	60702	60532	0	0
T4	10462	10286	0	0
T5	295155	295127	0	0
T6	135661	134756	0	0
T8	26181	25599	0	0
T9	114020	111754	0	0
T10	15635	15369	0	0
T11	164313	163205	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	460690025	0	0
T1	16789	16473	0	0
T2	11121	10867	0	0
T3	60702	60532	0	0
T4	10462	10286	0	0
T5	295155	295127	0	0
T6	135661	134756	0	0
T8	26181	25599	0	0
T9	114020	111754	0	0
T10	15635	15369	0	0
T11	164313	163205	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147	1147	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	20427	0	0
T12	603209	0	0	0
T44	41584	0	0	0
T64	12759	0	0	0
T70	8671	3383	0	0
T71	0	3168	0	0
T96	87698	0	0	0
T106	35785	0	0	0
T130	35264	0	0	0
T143	0	3754	0	0
T153	0	3326	0	0
T157	0	3077	0	0
T158	0	3719	0	0
T159	12552	0	0	0
T160	4457	0	0	0
T161	7889	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	460690025	0	0
T1	16789	16473	0	0
T2	11121	10867	0	0
T3	60702	60532	0	0
T4	10462	10286	0	0
T5	295155	295127	0	0
T6	135661	134756	0	0
T8	26181	25599	0	0
T9	114020	111754	0	0
T10	15635	15369	0	0
T11	164313	163205	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	460690025	0	0
T1	16789	16473	0	0
T2	11121	10867	0	0
T3	60702	60532	0	0
T4	10462	10286	0	0
T5	295155	295127	0	0
T6	135661	134756	0	0
T8	26181	25599	0	0
T9	114020	111754	0	0
T10	15635	15369	0	0
T11	164313	163205	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	460690025	0	0
T1	16789	16473	0	0
T2	11121	10867	0	0
T3	60702	60532	0	0
T4	10462	10286	0	0
T5	295155	295127	0	0
T6	135661	134756	0	0
T8	26181	25599	0	0
T9	114020	111754	0	0
T10	15635	15369	0	0
T11	164313	163205	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	94253956	0	0
T1	16789	182	0	0
T2	11121	4275	0	0
T3	60702	53003	0	0
T4	10462	220	0	0
T5	295155	850855	0	0
T6	135661	171093	0	0
T8	26181	461	0	0
T9	114020	278943	0	0
T10	15635	4519	0	0
T11	164313	8189	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	94253956	0	0
T1	16789	182	0	0
T2	11121	4275	0	0
T3	60702	53003	0	0
T4	10462	220	0	0
T5	295155	850855	0	0
T6	135661	171093	0	0
T8	26181	461	0	0
T9	114020	278943	0	0
T10	15635	4519	0	0
T11	164313	8189	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147	1147	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	460690025	0	0
T1	16789	16473	0	0
T2	11121	10867	0	0
T3	60702	60532	0	0
T4	10462	10286	0	0
T5	295155	295127	0	0
T6	135661	134756	0	0
T8	26181	25599	0	0
T9	114020	111754	0	0
T10	15635	15369	0	0
T11	164313	163205	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	460690025	0	0
T1	16789	16473	0	0
T2	11121	10867	0	0
T3	60702	60532	0	0
T4	10462	10286	0	0
T5	295155	295127	0	0
T6	135661	134756	0	0
T8	26181	25599	0	0
T9	114020	111754	0	0
T10	15635	15369	0	0
T11	164313	163205	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	66	0	0
T7	423612	0	0	0
T57	13232	0	0	0
T61	16126	1	0	0
T62	13905	1	0	0
T63	11473	0	0	0
T103	25353	0	0	0
T104	118924	0	0	0
T147	26581	0	0	0
T159	0	1	0	0
T162	0	1	0	0
T169	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0
T175	0	1	0	0
T178	0	1	0	0
T179	0	1	0	0
T180	59721	0	0	0
T181	25869	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	460690025	0	0
T1	16789	16473	0	0
T2	11121	10867	0	0
T3	60702	60532	0	0
T4	10462	10286	0	0
T5	295155	295127	0	0
T6	135661	134756	0	0
T8	26181	25599	0	0
T9	114020	111754	0	0
T10	15635	15369	0	0
T11	164313	163205	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	460690025	0	0
T1	16789	16473	0	0
T2	11121	10867	0	0
T3	60702	60532	0	0
T4	10462	10286	0	0
T5	295155	295127	0	0
T6	135661	134756	0	0
T8	26181	25599	0	0
T9	114020	111754	0	0
T10	15635	15369	0	0
T11	164313	163205	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	460690025	0	0
T1	16789	16473	0	0
T2	11121	10867	0	0
T3	60702	60532	0	0
T4	10462	10286	0	0
T5	295155	295127	0	0
T6	135661	134756	0	0
T8	26181	25599	0	0
T9	114020	111754	0	0
T10	15635	15369	0	0
T11	164313	163205	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	212149986	0	0
T3	60702	53455	0	0
T4	10462	0	0	0
T5	295155	183589	0	0
T6	135661	231276	0	0
T7	0	145828	0	0
T8	26181	0	0	0
T9	114020	0	0	0
T10	15635	0	0	0
T11	164313	1727	0	0
T31	0	2656	0	0
T61	16126	0	0	0
T103	25353	0	0	0
T105	0	18523	0	0
T108	0	6529	0	0
T147	0	14938	0	0
T154	0	2585	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147	1147	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	460690025	0	0
T1	16789	16473	0	0
T2	11121	10867	0	0
T3	60702	60532	0	0
T4	10462	10286	0	0
T5	295155	295127	0	0
T6	135661	134756	0	0
T8	26181	25599	0	0
T9	114020	111754	0	0
T10	15635	15369	0	0
T11	164313	163205	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	460690025	0	0
T1	16789	16473	0	0
T2	11121	10867	0	0
T3	60702	60532	0	0
T4	10462	10286	0	0
T5	295155	295127	0	0
T6	135661	134756	0	0
T8	26181	25599	0	0
T9	114020	111754	0	0
T10	15635	15369	0	0
T11	164313	163205	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	8007	0	0
T3	60702	14	0	0
T4	10462	0	0	0
T5	295155	28	0	0
T6	135661	47	0	0
T7	0	48	0	0
T8	26181	0	0	0
T9	114020	52	0	0
T10	15635	0	0	0
T11	164313	1	0	0
T61	16126	0	0	0
T103	25353	0	0	0
T104	0	7	0	0
T147	0	4	0	0
T180	0	5	0	0
T181	0	13	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	460690025	0	0
T1	16789	16473	0	0
T2	11121	10867	0	0
T3	60702	60532	0	0
T4	10462	10286	0	0
T5	295155	295127	0	0
T6	135661	134756	0	0
T8	26181	25599	0	0
T9	114020	111754	0	0
T10	15635	15369	0	0
T11	164313	163205	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	460690025	0	0
T1	16789	16473	0	0
T2	11121	10867	0	0
T3	60702	60532	0	0
T4	10462	10286	0	0
T5	295155	295127	0	0
T6	135661	134756	0	0
T8	26181	25599	0	0
T9	114020	111754	0	0
T10	15635	15369	0	0
T11	164313	163205	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	2442426	0	0
T6	135661	24811	0	0
T7	423612	8160	0	0
T9	114020	0	0	0
T10	15635	0	0	0
T11	164313	0	0	0
T31	0	25066	0	0
T60	0	11451	0	0
T61	16126	0	0	0
T62	13905	0	0	0
T63	11473	0	0	0
T97	0	622	0	0
T98	0	18458	0	0
T100	0	41902	0	0
T102	0	13436	0	0
T103	25353	0	0	0
T104	118924	0	0	0
T106	0	3871	0	0
T107	0	43644	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	25685844	0	0
T4	10462	4218	0	0
T5	295155	0	0	0
T6	135661	476302	0	0
T7	423612	106407	0	0
T8	26181	0	0	0
T9	114020	0	0	0
T10	15635	0	0	0
T11	164313	0	0	0
T31	0	86951	0	0
T61	16126	2273	0	0
T103	25353	0	0	0
T105	0	35011	0	0
T108	0	2462	0	0
T147	0	2691	0	0
T154	0	2567	0	0
T169	0	2422	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	460690025	0	0
T1	16789	16473	0	0
T2	11121	10867	0	0
T3	60702	60532	0	0
T4	10462	10286	0	0
T5	295155	295127	0	0
T6	135661	134756	0	0
T8	26181	25599	0	0
T9	114020	111754	0	0
T10	15635	15369	0	0
T11	164313	163205	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	34	33	97.06
Logical	34	33	97.06
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T64,T43,T139

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T11,T140,T141

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T9,T21,T22

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T142,T143,T144
1	Covered	T142,T143,T144

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T3,T5,T6

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T1,T2,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00111100000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T6

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T6

---

FSM Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T3,T5
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T4
ReadWaitSt	252	Covered	T1,T2,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T3,T5,T6
IdleSt->ReadSt	236	Covered	T1,T2,T4
InitSt->ErrorSt	315	Covered	T154,T60,T188
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T2,T61,T62
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T5,T6,T7
ReadSt->ReadWaitSt	252	Covered	T1,T2,T4
ReadWaitSt->ErrorSt	276	Covered	T155,T189,T191
ReadWaitSt->IdleSt	270	Covered	T1,T2,T4
ResetSt->ErrorSt	315	Covered	T7,T70,T71
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T5,T6,T7
CheckFailError	317	Covered	T142,T143,T144
FsmStateError	289	Covered	T3,T5,T6
MacroEccCorrError	221	Covered	T11,T64,T140
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T5,T6,T7
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T5,T6,T7
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T142,T143,T144
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T3,T5,T6
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T64,T140,T43
MacroEccCorrError->NoError	235	Covered	T11,T67,T192
NoError->AccessError	256	Covered	T5,T6,T7
NoError->CheckFailError	317	Covered	T142,T143,T144
NoError->FsmStateError	289	Covered	T3,T5,T6
NoError->MacroEccCorrError	221	Covered	T11,T64,T140

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T64,T43,T139
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T2,T170,T171
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T96,T60,T97
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T5,T6,T7
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T11,T140,T141
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T155,T189,T191
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T9,T21,T22
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T3,T5,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T3,T5,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T5
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T21,T22

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T142,T143,T144
1	0	Covered	T142,T143,T144
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T3,T5,T6
1	0	Covered	T2,T3,T5
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	461541576	460690025	0	0
DigestKnown_A	461541576	460690025	0	0
DigestOffsetMustBeRepresentable_A	1147	1147	0	0
EccErrorState_A	461541576	9269	0	0
ErrorKnown_A	461541576	460690025	0	0
FsmStateKnown_A	461541576	460690025	0	0
InitDoneKnown_A	461541576	460690025	0	0
InitReadLocksPartition_A	461541576	94431626	0	0
InitWriteLocksPartition_A	461541576	94431626	0	0
OffsetMustBeBlockAligned_A	1147	1147	0	0
OtpAddrKnown_A	461541576	460690025	0	0
OtpCmdKnown_A	461541576	460690025	0	0
OtpErrorState_A	461541576	52	0	0
OtpReqKnown_A	461541576	460690025	0	0
OtpSizeKnown_A	461541576	460690025	0	0
OtpWdataKnown_A	461541576	460690025	0	0
ReadLockPropagation_A	461541576	209794195	0	0
SizeMustBeBlockAligned_A	1147	1147	0	0
TlulGntKnown_A	461541576	460690025	0	0
TlulRdataKnown_A	461541576	460690025	0	0
TlulReadOnReadLock_A	461541576	8214	0	0
TlulRerrorKnown_A	461541576	460690025	0	0
TlulRvalidKnown_A	461541576	460690025	0	0
WriteLockPropagation_A	461541576	1171977	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	461541576	17275663	0	0
u_state_regs_A	461541576	460690025	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	460690025	0	0
T1	16789	16473	0	0
T2	11121	10867	0	0
T3	60702	60532	0	0
T4	10462	10286	0	0
T5	295155	295127	0	0
T6	135661	134756	0	0
T8	26181	25599	0	0
T9	114020	111754	0	0
T10	15635	15369	0	0
T11	164313	163205	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	460690025	0	0
T1	16789	16473	0	0
T2	11121	10867	0	0
T3	60702	60532	0	0
T4	10462	10286	0	0
T5	295155	295127	0	0
T6	135661	134756	0	0
T8	26181	25599	0	0
T9	114020	111754	0	0
T10	15635	15369	0	0
T11	164313	163205	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147	1147	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	9269	0	0
T65	885327	0	0	0
T126	17755	0	0	0
T142	10459	2742	0	0
T143	0	3754	0	0
T144	0	2773	0	0
T193	12109	0	0	0
T194	29534	0	0	0
T195	13477	0	0	0
T196	179541	0	0	0
T197	12205	0	0	0
T198	12334	0	0	0
T199	196107	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	460690025	0	0
T1	16789	16473	0	0
T2	11121	10867	0	0
T3	60702	60532	0	0
T4	10462	10286	0	0
T5	295155	295127	0	0
T6	135661	134756	0	0
T8	26181	25599	0	0
T9	114020	111754	0	0
T10	15635	15369	0	0
T11	164313	163205	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	460690025	0	0
T1	16789	16473	0	0
T2	11121	10867	0	0
T3	60702	60532	0	0
T4	10462	10286	0	0
T5	295155	295127	0	0
T6	135661	134756	0	0
T8	26181	25599	0	0
T9	114020	111754	0	0
T10	15635	15369	0	0
T11	164313	163205	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	460690025	0	0
T1	16789	16473	0	0
T2	11121	10867	0	0
T3	60702	60532	0	0
T4	10462	10286	0	0
T5	295155	295127	0	0
T6	135661	134756	0	0
T8	26181	25599	0	0
T9	114020	111754	0	0
T10	15635	15369	0	0
T11	164313	163205	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	94431626	0	0
T1	16789	233	0	0
T2	11121	4299	0	0
T3	60702	53037	0	0
T4	10462	271	0	0
T5	295155	851076	0	0
T6	135661	172898	0	0
T8	26181	597	0	0
T9	114020	284740	0	0
T10	15635	4570	0	0
T11	164313	8410	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	94431626	0	0
T1	16789	233	0	0
T2	11121	4299	0	0
T3	60702	53037	0	0
T4	10462	271	0	0
T5	295155	851076	0	0
T6	135661	172898	0	0
T8	26181	597	0	0
T9	114020	284740	0	0
T10	15635	4570	0	0
T11	164313	8410	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147	1147	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	460690025	0	0
T1	16789	16473	0	0
T2	11121	10867	0	0
T3	60702	60532	0	0
T4	10462	10286	0	0
T5	295155	295127	0	0
T6	135661	134756	0	0
T8	26181	25599	0	0
T9	114020	111754	0	0
T10	15635	15369	0	0
T11	164313	163205	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	460690025	0	0
T1	16789	16473	0	0
T2	11121	10867	0	0
T3	60702	60532	0	0
T4	10462	10286	0	0
T5	295155	295127	0	0
T6	135661	134756	0	0
T8	26181	25599	0	0
T9	114020	111754	0	0
T10	15635	15369	0	0
T11	164313	163205	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	52	0	0
T2	11121	1	0	0
T3	60702	0	0	0
T4	10462	0	0	0
T5	295155	0	0	0
T6	135661	0	0	0
T8	26181	0	0	0
T9	114020	0	0	0
T10	15635	0	0	0
T11	164313	0	0	0
T61	16126	0	0	0
T150	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T155	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T174	0	1	0	0
T176	0	1	0	0
T177	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	460690025	0	0
T1	16789	16473	0	0
T2	11121	10867	0	0
T3	60702	60532	0	0
T4	10462	10286	0	0
T5	295155	295127	0	0
T6	135661	134756	0	0
T8	26181	25599	0	0
T9	114020	111754	0	0
T10	15635	15369	0	0
T11	164313	163205	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	460690025	0	0
T1	16789	16473	0	0
T2	11121	10867	0	0
T3	60702	60532	0	0
T4	10462	10286	0	0
T5	295155	295127	0	0
T6	135661	134756	0	0
T8	26181	25599	0	0
T9	114020	111754	0	0
T10	15635	15369	0	0
T11	164313	163205	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	460690025	0	0
T1	16789	16473	0	0
T2	11121	10867	0	0
T3	60702	60532	0	0
T4	10462	10286	0	0
T5	295155	295127	0	0
T6	135661	134756	0	0
T8	26181	25599	0	0
T9	114020	111754	0	0
T10	15635	15369	0	0
T11	164313	163205	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	209794195	0	0
T5	295155	183023	0	0
T6	135661	345901	0	0
T7	423612	143680	0	0
T8	26181	0	0	0
T9	114020	0	0	0
T10	15635	0	0	0
T11	164313	1716	0	0
T31	0	5970	0	0
T61	16126	0	0	0
T62	13905	0	0	0
T96	0	3609	0	0
T103	25353	0	0	0
T105	0	21251	0	0
T108	0	6527	0	0
T147	0	14932	0	0
T154	0	2994	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147	1147	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	460690025	0	0
T1	16789	16473	0	0
T2	11121	10867	0	0
T3	60702	60532	0	0
T4	10462	10286	0	0
T5	295155	295127	0	0
T6	135661	134756	0	0
T8	26181	25599	0	0
T9	114020	111754	0	0
T10	15635	15369	0	0
T11	164313	163205	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	460690025	0	0
T1	16789	16473	0	0
T2	11121	10867	0	0
T3	60702	60532	0	0
T4	10462	10286	0	0
T5	295155	295127	0	0
T6	135661	134756	0	0
T8	26181	25599	0	0
T9	114020	111754	0	0
T10	15635	15369	0	0
T11	164313	163205	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	8214	0	0
T3	60702	16	0	0
T4	10462	0	0	0
T5	295155	32	0	0
T6	135661	52	0	0
T7	0	37	0	0
T8	26181	0	0	0
T9	114020	112	0	0
T10	15635	0	0	0
T11	164313	1	0	0
T61	16126	0	0	0
T103	25353	0	0	0
T104	0	6	0	0
T147	0	5	0	0
T180	0	7	0	0
T181	0	16	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	460690025	0	0
T1	16789	16473	0	0
T2	11121	10867	0	0
T3	60702	60532	0	0
T4	10462	10286	0	0
T5	295155	295127	0	0
T6	135661	134756	0	0
T8	26181	25599	0	0
T9	114020	111754	0	0
T10	15635	15369	0	0
T11	164313	163205	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	460690025	0	0
T1	16789	16473	0	0
T2	11121	10867	0	0
T3	60702	60532	0	0
T4	10462	10286	0	0
T5	295155	295127	0	0
T6	135661	134756	0	0
T8	26181	25599	0	0
T9	114020	111754	0	0
T10	15635	15369	0	0
T11	164313	163205	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	1171977	0	0
T6	135661	13757	0	0
T7	423612	2377	0	0
T9	114020	0	0	0
T10	15635	0	0	0
T11	164313	0	0	0
T60	0	3671	0	0
T61	16126	0	0	0
T62	13905	0	0	0
T63	11473	0	0	0
T96	0	487	0	0
T98	0	15027	0	0
T99	0	4442	0	0
T103	25353	0	0	0
T104	118924	0	0	0
T106	0	1464	0	0
T131	0	6521	0	0
T183	0	34494	0	0
T185	0	5491	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	17275663	0	0
T2	11121	2770	0	0
T3	60702	0	0	0
T4	10462	4184	0	0
T5	295155	0	0	0
T6	135661	380654	0	0
T7	0	33913	0	0
T8	26181	0	0	0
T9	114020	0	0	0
T10	15635	0	0	0
T11	164313	0	0	0
T44	0	34611	0	0
T61	16126	0	0	0
T96	0	79223	0	0
T105	0	34926	0	0
T106	0	27367	0	0
T147	0	2674	0	0
T182	0	25753	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461541576	460690025	0	0
T1	16789	16473	0	0
T2	11121	10867	0	0
T3	60702	60532	0	0
T4	10462	10286	0	0
T5	295155	295127	0	0
T6	135661	134756	0	0
T8	26181	25599	0	0
T9	114020	111754	0	0
T10	15635	15369	0	0
T11	164313	163205	0	0