Unified Coverage Report

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ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.RDataOutKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.WidthMustBe64bit_A	0	0	1153	1153	0	0
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre.OutputsKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre.OutputsKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_state_regs.AssertConnected_A	0	0	1153	1153	0	0
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_state_regs_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[5].gen_buffered.FpvSecCmCntPartBufCheck_A	0	0	480569264	50	0	0
tb.dut.gen_partitions[5].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	0	0	480569264	50	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.AccessKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.BypassEnable1_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.CnstyChkAckKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.DataKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.DigestKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.DigestOffsetMustBeRepresentable_A	0	0	1153	1153	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.ErrorKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.InitDoneKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.InitReadLocksPartition_A	0	0	480569264	101029358	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.InitWriteLocksPartition_A	0	0	480569264	101029358	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.IntegChkAckKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.OffsetMustBeBlockAligned_A	0	0	1153	1153	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.OtpAddrKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.OtpCmdKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.OtpReqKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.OtpSizeKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.OtpWdataKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.ReadLockImpliesDigest_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.ScrmblCmdKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.ScrmblDataKnown_A	0	0	480237122	479354652	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.ScrmblModeKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.ScrmblMtxReqKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.ScrmblSelKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.ScrmblValidKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.SizeMustBeBlockAligned_A	0	0	1153	1153	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.WriteLockPropagation_A	0	0	480569264	2065481	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.gen_digest_write_lock.DigestWriteLocksPartition_A	0	0	480569264	25615824	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock.OutputsKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.DataKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.DataOutKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.EccErrKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.EccKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.RDataOutKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.WidthMustBe64bit_A	0	0	1153	1153	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre.OutputsKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre.OutputsKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_state_regs.AssertConnected_A	0	0	1153	1153	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_state_regs_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[6].gen_buffered.FpvSecCmCntPartBufCheck_A	0	0	480569264	50	0	0
tb.dut.gen_partitions[6].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	0	0	480569264	50	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.AccessKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.BypassEnable1_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.CnstyChkAckKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.DataKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.DigestKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.DigestOffsetMustBeRepresentable_A	0	0	1153	1153	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.ErrorKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.InitDoneKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.InitReadLocksPartition_A	0	0	480569264	93269956	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.InitWriteLocksPartition_A	0	0	480569264	93269956	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.IntegChkAckKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.OffsetMustBeBlockAligned_A	0	0	1153	1153	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.OtpAddrKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.OtpCmdKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.OtpReqKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.OtpSizeKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.OtpWdataKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.ReadLockImpliesDigest_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.ScrmblCmdKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.ScrmblDataKnown_A	0	0	480237122	479354652	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.ScrmblModeKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.ScrmblMtxReqKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.ScrmblSelKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.ScrmblValidKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.SizeMustBeBlockAligned_A	0	0	1153	1153	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.WriteLockPropagation_A	0	0	480569264	2387178	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.gen_digest_write_lock.DigestWriteLocksPartition_A	0	0	480569264	28745718	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock.OutputsKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.DataKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.DataOutKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.EccErrKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.EccKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.RDataOutKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.WidthMustBe64bit_A	0	0	1153	1153	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre.OutputsKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre.OutputsKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_state_regs.AssertConnected_A	0	0	1153	1153	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_state_regs_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[7].gen_buffered.FpvSecCmCntPartBufCheck_A	0	0	480569264	50	0	0
tb.dut.gen_partitions[7].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	0	0	480569264	50	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.AccessKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.BypassEnable0_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.BypassEnable1_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.CnstyChkAckKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.DataKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.DigestKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.DigestOffsetMustBeRepresentable_A	0	0	1153	1153	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.ErrorKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.InitDoneKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.InitReadLocksPartition_A	0	0	480569264	98769042	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.InitWriteLocksPartition_A	0	0	480569264	98769042	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.IntegChkAckKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.OffsetMustBeBlockAligned_A	0	0	1153	1153	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.OtpAddrKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.OtpCmdKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.OtpReqKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.OtpSizeKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.OtpWdataKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.ReadLockImpliesDigest_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.ReadLockPropagation_A	0	0	480569264	2446478	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.ScrambledImpliesDigest_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.ScrmblCmdKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.ScrmblDataKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.ScrmblModeKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.ScrmblMtxReqKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.ScrmblSelKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.ScrmblValidKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.SizeMustBeBlockAligned_A	0	0	1153	1153	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.WriteLockImpliesDigest_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.WriteLockPropagation_A	0	0	480569264	2273807	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_read_lock.DigestReadLocksPartition_A	0	0	480569264	27268918	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock.OutputsKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_write_lock.DigestWriteLocksPartition_A	0	0	480569264	27268918	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock.OutputsKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.DataKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.DataOutKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.EccErrKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.EccKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.RDataOutKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.WidthMustBe64bit_A	0	0	1153	1153	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre.OutputsKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre.OutputsKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_state_regs.AssertConnected_A	0	0	1153	1153	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_state_regs_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[8].gen_buffered.FpvSecCmCntPartBufCheck_A	0	0	480569264	50	0	0
tb.dut.gen_partitions[8].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	0	0	480569264	50	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.AccessKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.BypassEnable0_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.BypassEnable1_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.CnstyChkAckKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.DataKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.DigestKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.DigestOffsetMustBeRepresentable_A	0	0	1153	1153	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.ErrorKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.InitDoneKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.InitReadLocksPartition_A	0	0	480569264	108854980	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.InitWriteLocksPartition_A	0	0	480569264	108854980	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.IntegChkAckKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.OffsetMustBeBlockAligned_A	0	0	1153	1153	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.OtpAddrKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.OtpCmdKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.OtpReqKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.OtpSizeKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.OtpWdataKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.ReadLockImpliesDigest_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.ReadLockPropagation_A	0	0	480569264	2632016	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.ScrambledImpliesDigest_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.ScrmblCmdKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.ScrmblDataKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.ScrmblModeKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.ScrmblMtxReqKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.ScrmblSelKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.ScrmblValidKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.SizeMustBeBlockAligned_A	0	0	1153	1153	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.WriteLockImpliesDigest_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.WriteLockPropagation_A	0	0	480569264	2232576	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_read_lock.DigestReadLocksPartition_A	0	0	480569264	24968349	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock.OutputsKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_write_lock.DigestWriteLocksPartition_A	0	0	480569264	24968349	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock.OutputsKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.DataKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.DataOutKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.EccErrKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.EccKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.RDataOutKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.WidthMustBe64bit_A	0	0	1153	1153	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre.OutputsKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre.OutputsKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_state_regs.AssertConnected_A	0	0	1153	1153	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_state_regs_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[9].gen_buffered.FpvSecCmCntPartBufCheck_A	0	0	480569264	50	0	0
tb.dut.gen_partitions[9].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	0	0	480569264	50	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.AccessKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.BypassEnable0_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.BypassEnable1_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.CnstyChkAckKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.DataKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.DigestKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.DigestOffsetMustBeRepresentable_A	0	0	1153	1153	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.ErrorKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.InitDoneKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.InitReadLocksPartition_A	0	0	480569264	113321442	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.InitWriteLocksPartition_A	0	0	480569264	113321442	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.IntegChkAckKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.OffsetMustBeBlockAligned_A	0	0	1153	1153	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.OtpAddrKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.OtpCmdKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.OtpReqKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.OtpSizeKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.OtpWdataKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.ReadLockImpliesDigest_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.ReadLockPropagation_A	0	0	480569264	249510494	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.ScrambledImpliesDigest_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.ScrmblCmdKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.ScrmblDataKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.ScrmblModeKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.ScrmblMtxReqKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.ScrmblSelKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.ScrmblValidKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.SizeMustBeBlockAligned_A	0	0	1153	1153	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.WriteLockImpliesDigest_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.WriteLockPropagation_A	0	0	480569264	249430406	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_read_lock.DigestReadLocksPartition_A	0	0	480569264	16833578	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock.OutputsKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_write_lock.DigestWriteLocksPartition_A	0	0	480569264	16833578	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock.OutputsKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.DataKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.DataOutKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.EccErrKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.EccKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.RDataOutKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.WidthMustBe64bit_A	0	0	1153	1153	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre.OutputsKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre.OutputsKnown_A	0	0	480569264	479686794	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_state_regs.AssertConnected_A	0	0	1153	1153	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_state_regs_A	0	0	480569264	479686794	0	0
tb.dut.gen_reg_we_assert_generic.FpvSecCmPrimFsmCheck_A	0	0	480569264	50	0	0
tb.dut.gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A	0	0	480569264	50	0	0
tb.dut.otp_ctrl_core_csr_assert.TlulOOBAddrErr_A	0	0	483546363	8045515	0	0
tb.dut.otp_ctrl_core_csr_assert.check_regwen_rd_A	0	0	483546363	3057	0	0
tb.dut.otp_ctrl_core_csr_assert.check_timeout_rd_A	0	0	483546363	2808	0	0
tb.dut.otp_ctrl_core_csr_assert.check_trigger_regwen_rd_A	0	0	483546363	3123	0	0
tb.dut.otp_ctrl_core_csr_assert.consistency_check_period_rd_A	0	0	483546363	3406	0	0
tb.dut.otp_ctrl_core_csr_assert.creator_sw_cfg_read_lock_rd_A	0	0	483546363	2924	0	0
tb.dut.otp_ctrl_core_csr_assert.direct_access_address_rd_A	0	0	483546363	2172	0	0
tb.dut.otp_ctrl_core_csr_assert.direct_access_wdata_0_rd_A	0	0	483546363	1544	0	0
tb.dut.otp_ctrl_core_csr_assert.direct_access_wdata_1_rd_A	0	0	483546363	1844	0	0
tb.dut.otp_ctrl_core_csr_assert.integrity_check_period_rd_A	0	0	483546363	3160	0	0
tb.dut.otp_ctrl_core_csr_assert.intr_enable_rd_A	0	0	483546363	4391	0	0
tb.dut.otp_ctrl_core_csr_assert.owner_sw_cfg_read_lock_rd_A	0	0	483546363	2712	0	0
tb.dut.otp_ctrl_core_csr_assert.rot_creator_auth_codesign_read_lock_rd_A	0	0	483546363	2696	0	0
tb.dut.otp_ctrl_core_csr_assert.rot_creator_auth_state_read_lock_rd_A	0	0	483546363	2633	0	0
tb.dut.otp_ctrl_core_csr_assert.vendor_test_read_lock_rd_A	0	0	483546363	2567	0	0
tb.dut.prim_tlul_assert_device.aKnown_A	0	0	483546363	33139187	0	0
tb.dut.prim_tlul_assert_device.aKnown_AKnownEnable	0	0	483546363	482612310	0	0
tb.dut.prim_tlul_assert_device.aReadyKnown_A	0	0	483546363	482612310	0	0
tb.dut.prim_tlul_assert_device.dKnown_A	0	0	483546363	35799627	0	0
tb.dut.prim_tlul_assert_device.dKnown_AKnownEnable	0	0	483546363	482612310	0	0
tb.dut.prim_tlul_assert_device.dReadyKnown_A	0	0	483546363	482612310	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A	0	0	1328	1328	0	0

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	ASSERT	PROPERTIES	SEQUENCES
Total	1451	0	20
Category 0	1451	0	20

	ASSERT	PROPERTIES	SEQUENCES
Total	1451	0	20
Severity 0	1451	0	20

	NUMBER	PERCENT
Total Number	1451	100.00
Uncovered	54	3.72
Success	1397	96.28
Failure	0	0.00
Incomplete	11	0.76
Without Attempts	5	0.34

	NUMBER	PERCENT
Total Number	20	100.00
Uncovered	0	0.00
All Matches	20	100.00
First Matches	20	100.00