Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.71	96.75	96.15	97.06		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	483546363	8045515	0	0
check_regwen_rd_A	483546363	3057	0	0
check_timeout_rd_A	483546363	2808	0	0
check_trigger_regwen_rd_A	483546363	3123	0	0
consistency_check_period_rd_A	483546363	3406	0	0
creator_sw_cfg_read_lock_rd_A	483546363	2924	0	0
direct_access_address_rd_A	483546363	2172	0	0
direct_access_wdata_0_rd_A	483546363	1544	0	0
direct_access_wdata_1_rd_A	483546363	1844	0	0
integrity_check_period_rd_A	483546363	3160	0	0
intr_enable_rd_A	483546363	4391	0	0
owner_sw_cfg_read_lock_rd_A	483546363	2712	0	0
rot_creator_auth_codesign_read_lock_rd_A	483546363	2696	0	0
rot_creator_auth_state_read_lock_rd_A	483546363	2633	0	0
vendor_test_read_lock_rd_A	483546363	2567	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483546363	8045515	0	0
T2	433300	93999	0	0
T3	98167	0	0	0
T4	478748	94713	0	0
T6	842410	151282	0	0
T7	12333	0	0	0
T8	5262	0	0	0
T9	22582	0	0	0
T10	206650	0	0	0
T11	28596	0	0	0
T12	0	50779	0	0
T13	0	202163	0	0
T26	13309	0	0	0
T58	0	67728	0	0
T162	0	23031	0	0
T279	0	100680	0	0
T280	0	27303	0	0
T281	0	42298	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483546363	3057	0	0
T6	842410	146	0	0
T8	5262	0	0	0
T9	22582	0	0	0
T10	206650	0	0	0
T11	28596	0	0	0
T26	13309	0	0	0
T31	44191	0	0	0
T60	13721	0	0	0
T63	0	152	0	0
T100	63547	0	0	0
T101	6197	0	0	0
T258	0	32	0	0
T259	0	106	0	0
T295	0	119	0	0
T308	0	100	0	0
T363	0	49	0	0
T369	0	77	0	0
T370	0	58	0	0
T371	0	34	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483546363	2808	0	0
T6	842410	148	0	0
T8	5262	0	0	0
T9	22582	0	0	0
T10	206650	0	0	0
T11	28596	0	0	0
T26	13309	0	0	0
T31	44191	0	0	0
T60	13721	0	0	0
T63	0	154	0	0
T100	63547	0	0	0
T101	6197	0	0	0
T258	0	28	0	0
T259	0	89	0	0
T295	0	227	0	0
T308	0	174	0	0
T363	0	54	0	0
T369	0	43	0	0
T370	0	90	0	0
T371	0	12	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483546363	3123	0	0
T6	842410	169	0	0
T8	5262	0	0	0
T9	22582	0	0	0
T10	206650	0	0	0
T11	28596	0	0	0
T26	13309	0	0	0
T31	44191	0	0	0
T60	13721	0	0	0
T63	0	93	0	0
T100	63547	0	0	0
T101	6197	0	0	0
T258	0	36	0	0
T259	0	98	0	0
T295	0	130	0	0
T308	0	117	0	0
T363	0	50	0	0
T369	0	77	0	0
T370	0	73	0	0
T371	0	43	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483546363	3406	0	0
T6	842410	263	0	0
T8	5262	0	0	0
T9	22582	0	0	0
T10	206650	0	0	0
T11	28596	0	0	0
T26	13309	0	0	0
T31	44191	0	0	0
T60	13721	0	0	0
T63	0	153	0	0
T100	63547	0	0	0
T101	6197	0	0	0
T258	0	42	0	0
T259	0	92	0	0
T295	0	110	0	0
T308	0	137	0	0
T363	0	85	0	0
T369	0	67	0	0
T370	0	88	0	0
T371	0	19	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483546363	2924	0	0
T6	842410	179	0	0
T8	5262	0	0	0
T9	22582	0	0	0
T10	206650	0	0	0
T11	28596	0	0	0
T26	13309	0	0	0
T31	44191	0	0	0
T60	13721	0	0	0
T63	0	142	0	0
T100	63547	0	0	0
T101	6197	0	0	0
T258	0	42	0	0
T259	0	141	0	0
T295	0	149	0	0
T308	0	149	0	0
T363	0	64	0	0
T369	0	70	0	0
T370	0	78	0	0
T371	0	38	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483546363	2172	0	0
T6	842410	200	0	0
T8	5262	0	0	0
T9	22582	0	0	0
T10	206650	0	0	0
T11	28596	0	0	0
T26	13309	0	0	0
T31	44191	0	0	0
T60	13721	0	0	0
T63	0	75	0	0
T100	63547	0	0	0
T101	6197	0	0	0
T258	0	34	0	0
T259	0	125	0	0
T295	0	185	0	0
T308	0	114	0	0
T363	0	38	0	0
T369	0	120	0	0
T370	0	98	0	0
T371	0	18	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483546363	1544	0	0
T6	842410	141	0	0
T8	5262	0	0	0
T9	22582	0	0	0
T10	206650	0	0	0
T11	28596	0	0	0
T26	13309	0	0	0
T31	44191	0	0	0
T60	13721	0	0	0
T63	0	54	0	0
T100	63547	0	0	0
T101	6197	0	0	0
T258	0	25	0	0
T259	0	104	0	0
T295	0	89	0	0
T308	0	126	0	0
T363	0	39	0	0
T369	0	33	0	0
T370	0	66	0	0
T371	0	31	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483546363	1844	0	0
T6	842410	160	0	0
T8	5262	0	0	0
T9	22582	0	0	0
T10	206650	0	0	0
T11	28596	0	0	0
T26	13309	0	0	0
T31	44191	0	0	0
T60	13721	0	0	0
T63	0	73	0	0
T100	63547	0	0	0
T101	6197	0	0	0
T258	0	26	0	0
T259	0	99	0	0
T295	0	115	0	0
T308	0	201	0	0
T363	0	59	0	0
T369	0	60	0	0
T370	0	93	0	0
T371	0	17	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483546363	3160	0	0
T6	842410	185	0	0
T8	5262	0	0	0
T9	22582	0	0	0
T10	206650	0	0	0
T11	28596	0	0	0
T26	13309	0	0	0
T31	44191	0	0	0
T60	13721	0	0	0
T63	0	82	0	0
T100	63547	0	0	0
T101	6197	0	0	0
T258	0	21	0	0
T259	0	120	0	0
T295	0	124	0	0
T308	0	93	0	0
T363	0	49	0	0
T369	0	55	0	0
T370	0	60	0	0
T371	0	23	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483546363	4391	0	0
T6	842410	173	0	0
T8	5262	0	0	0
T9	22582	0	0	0
T10	206650	35	0	0
T11	28596	0	0	0
T26	13309	0	0	0
T31	44191	0	0	0
T60	13721	0	0	0
T63	0	120	0	0
T100	63547	0	0	0
T101	6197	0	0	0
T175	0	21	0	0
T258	0	52	0	0
T259	0	148	0	0
T295	0	167	0	0
T308	0	126	0	0
T363	0	77	0	0
T369	0	95	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483546363	2712	0	0
T6	842410	204	0	0
T8	5262	0	0	0
T9	22582	0	0	0
T10	206650	0	0	0
T11	28596	0	0	0
T26	13309	0	0	0
T31	44191	0	0	0
T60	13721	0	0	0
T63	0	86	0	0
T100	63547	0	0	0
T101	6197	0	0	0
T258	0	35	0	0
T259	0	146	0	0
T295	0	174	0	0
T308	0	101	0	0
T363	0	64	0	0
T369	0	59	0	0
T370	0	96	0	0
T371	0	19	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483546363	2696	0	0
T6	842410	143	0	0
T8	5262	0	0	0
T9	22582	0	0	0
T10	206650	0	0	0
T11	28596	0	0	0
T26	13309	0	0	0
T31	44191	0	0	0
T60	13721	0	0	0
T63	0	109	0	0
T100	63547	0	0	0
T101	6197	0	0	0
T258	0	23	0	0
T259	0	118	0	0
T295	0	134	0	0
T308	0	143	0	0
T363	0	36	0	0
T369	0	32	0	0
T370	0	88	0	0
T371	0	21	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483546363	2633	0	0
T6	842410	180	0	0
T8	5262	0	0	0
T9	22582	0	0	0
T10	206650	0	0	0
T11	28596	0	0	0
T26	13309	0	0	0
T31	44191	0	0	0
T60	13721	0	0	0
T63	0	110	0	0
T100	63547	0	0	0
T101	6197	0	0	0
T258	0	26	0	0
T259	0	140	0	0
T295	0	145	0	0
T308	0	116	0	0
T363	0	57	0	0
T369	0	73	0	0
T370	0	56	0	0
T371	0	17	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483546363	2567	0	0
T6	842410	208	0	0
T8	5262	0	0	0
T9	22582	0	0	0
T10	206650	0	0	0
T11	28596	0	0	0
T26	13309	0	0	0
T31	44191	0	0	0
T60	13721	0	0	0
T63	0	126	0	0
T100	63547	0	0	0
T101	6197	0	0	0
T258	0	51	0	0
T259	0	92	0	0
T295	0	133	0	0
T308	0	112	0	0
T363	0	51	0	0
T369	0	27	0	0
T370	0	72	0	0
T371	0	33	0	0