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Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.79 96.91 100.00 95.24 100.00 81.82


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.07 90.44 100.00 75.02 95.24 100.00 85.71


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.71 96.75 96.15 97.06 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_otp_ctrl_ecc_reg 93.70 100.00 74.82 100.00 100.00
u_prim_count 100.00 100.00
u_prim_mubi8_sender_read_lock_pre 79.17 37.50 100.00 100.00
u_prim_mubi8_sender_write_lock_pre 79.17 37.50 100.00 100.00
u_state_regs 100.00 100.00 100.00 100.00

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Module Instances:
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf
Line Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf
Line No.TotalCoveredPercent
TOTAL979496.91
CONT_ASSIGN18211100.00
CONT_ASSIGN19311100.00
ALWAYS2067777100.00
CONT_ASSIGN636100.00
CONT_ASSIGN64111100.00
CONT_ASSIGN64211100.00
CONT_ASSIGN64611100.00
CONT_ASSIGN65211100.00
CONT_ASSIGN67511100.00
CONT_ASSIGN67811100.00
CONT_ASSIGN68011100.00
CONT_ASSIGN723100.00
CONT_ASSIGN743100.00
ALWAYS75033100.00
ALWAYS75355100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
182 1 1
193 1 1
206 1 1
209 1 1
212 1 1
215 1 1
218 1 1
219 1 1
220 1 1
221 1 1
224 1 1
225 1 1
226 1 1
229 1 1
230 1 1
233 1 1
234 1 1
237 1 1
238 1 1
240 1 1
245 1 1
246 1 1
MISSING_ELSE
254 1 1
255 1 1
256 1 1
MISSING_ELSE
265 1 1
266 1 1
267 1 1
271 1 1
272 1 1
275 1 1
276 unreachable
278 1 1
279 1 1
282 1 1
283 1 1
MISSING_ELSE
286 1 1
287 1 1
MISSING_ELSE
298 excluded
Exclude Annotation: VC_COV_UNR
299 excluded
Exclude Annotation: VC_COV_UNR
300 excluded
Exclude Annotation: VC_COV_UNR
301 excluded
Exclude Annotation: VC_COV_UNR
302 excluded
Exclude Annotation: VC_COV_UNR
303 unreachable
==> MISSING_ELSE
311 excluded
Exclude Annotation: VC_COV_UNR
312 excluded
Exclude Annotation: VC_COV_UNR
313 excluded
Exclude Annotation: VC_COV_UNR
314 excluded
Exclude Annotation: VC_COV_UNR
315 unreachable
316 unreachable
317 unreachable
==> MISSING_ELSE
324 1 1
325 1 1
326 unreachable
331 1 1
333 1 1
334 1 1
335 1 1
MISSING_ELSE
343 1 1
348 1 1
349 unreachable
MISSING_ELSE
351 1 1
352 1 1
MISSING_ELSE
362 1 1
363 1 1
366 1 1
368 unreachable
369 unreachable
370 unreachable
373 unreachable
374 unreachable
376 unreachable
381 1 1
385 1 1
386 1 1
387 1 1
390 1 1
391 1 1
394 1 1
395 1 1
397 1 1
401 1 1
402 1 1
MISSING_ELSE
405 1 1
406 1 1
408 1 1
MISSING_ELSE
417 1 1
418 unreachable
419 unreachable
420 unreachable
423 unreachable
424 unreachable
425 unreachable
426 unreachable
427 unreachable
==> MISSING_ELSE
432 unreachable
433 unreachable
434 unreachable
==> MISSING_ELSE
443 1 1
444 1 1
445 1 1
==> MISSING_ELSE
455 excluded
Exclude Annotation: VC_COV_UNR
456 excluded
Exclude Annotation: VC_COV_UNR
457 excluded
Exclude Annotation: VC_COV_UNR
458 excluded
Exclude Annotation: VC_COV_UNR
459 excluded
Exclude Annotation: VC_COV_UNR
460 unreachable
==> MISSING_ELSE
467 excluded
Exclude Annotation: VC_COV_UNR
468 excluded
Exclude Annotation: VC_COV_UNR
469 excluded
Exclude Annotation: VC_COV_UNR
470 unreachable
==> MISSING_ELSE
480 excluded
Exclude Annotation: VC_COV_UNR
481 excluded
Exclude Annotation: VC_COV_UNR
482 excluded
Exclude Annotation: VC_COV_UNR
483 unreachable
485 unreachable
489 unreachable
490 unreachable
491 unreachable
493 unreachable
494 unreachable
498 unreachable
499 unreachable
==> MISSING_ELSE
503 unreachable
504 unreachable
==> MISSING_ELSE
==> MISSING_ELSE
516 excluded
Exclude Annotation: VC_COV_UNR
517 excluded
Exclude Annotation: VC_COV_UNR
518 excluded
Exclude Annotation: VC_COV_UNR
519 excluded
Exclude Annotation: VC_COV_UNR
520 unreachable
==> MISSING_ELSE
528 excluded
Exclude Annotation: VC_COV_UNR
529 excluded
Exclude Annotation: VC_COV_UNR
530 excluded
Exclude Annotation: VC_COV_UNR
531 excluded
Exclude Annotation: VC_COV_UNR
532 unreachable
==> MISSING_ELSE
542 excluded
Exclude Annotation: VC_COV_UNR
543 excluded
Exclude Annotation: VC_COV_UNR
544 excluded
Exclude Annotation: VC_COV_UNR
547 unreachable
548 unreachable
551 unreachable
552 unreachable
556 unreachable
560 unreachable
561 unreachable
563 unreachable
==> MISSING_ELSE
572 1 1
573 1 1
574 1 1
MISSING_ELSE
578 1 1
579 1 1
595 1 1
596 excluded
Exclude Annotation: VC_COV_UNR
597 excluded
Exclude Annotation: VC_COV_UNR
598 excluded
Exclude Annotation: VC_COV_UNR
==> MISSING_ELSE
MISSING_ELSE
602 1 1
603 1 1
604 1 1
605 1 1
606 1 1
MISSING_ELSE
MISSING_ELSE
636 0 1
641 1 1
642 1 1
646 1 1
652 1 1
675 1 1
678 1 1
680 1 1
723 0 1
743 0 1
750 3 3
753 1 1
754 1 1
756 1 1
758 1 1
759 1 1


Cond Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf
TotalCoveredPercent
Conditions1818100.00
Logical1818100.00
Non-Logical00
Event00

 LINE       271
 EXPRESSION (cnt == LastScrmblBlock)
            ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       282
 EXPRESSION (otp_err != NoError)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT20,T21,T49

 LINE       302
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------
-1--2-StatusTests
01Unreachable
10Unreachable
11Unreachable

 LINE       368
 EXPRESSION ((digest_o == data_mux) || (digest_o == '0))
             -----------1----------    --------2-------
-1--2-StatusTests
00Unreachable
01Unreachable
10Unreachable

 LINE       368
 SUB-EXPRESSION (digest_o == data_mux)
                -----------1----------
-1-StatusTests
0Unreachable
1Unreachable

 LINE       368
 SUB-EXPRESSION (digest_o == '0)
                --------1-------
-1-StatusTests
0Unreachable
1Unreachable

 LINE       385
 EXPRESSION (cnt == LastScrmblBlock)
            ------------1-----------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       401
 EXPRESSION (otp_err != NoError)
            ----------1---------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT32,T50,T51

 LINE       426
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------
-1--2-StatusTests
01Unreachable
10Unreachable
11Unreachable

 LINE       433
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------
-1--2-StatusTests
01Unreachable
10Unreachable
11Unreachable

 LINE       485
 EXPRESSION (cnt == PenultimateScrmblBlock)
            ---------------1---------------
-1-StatusTests
0Unreachable
1Unreachable

 LINE       547
 EXPRESSION ((digest_o == data_mux) || (digest_o == '0))
             -----------1----------    --------2-------
-1--2-StatusTests
00Unreachable
01Unreachable
10Unreachable

 LINE       547
 SUB-EXPRESSION (digest_o == data_mux)
                -----------1----------
-1-StatusTests
0Unreachable
1Unreachable

 LINE       547
 SUB-EXPRESSION (digest_o == '0)
                --------1-------
-1-StatusTests
0Unreachable
1Unreachable

 LINE       573
 EXPRESSION (error_q == NoError)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT17,T18,T19

 LINE       597
 EXPRESSION (state_q != ErrorSt)
            ----------1---------
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1Excluded VC_COV_UNR

 LINE       605
 EXPRESSION (state_q != ErrorSt)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T4

 LINE       636
 EXPRESSION ((base_sel == DigOffset) ? DigestOffset : 11'b11110101000)
             -----------1-----------
-1-StatusTestsExclude Annotation
0CoveredT1,T2,T3
1Excluded VC_COV_UNR

 LINE       636
 SUB-EXPRESSION (base_sel == DigOffset)
                -----------1-----------
-1-StatusTestsExclude Annotation
0CoveredT1,T2,T3
1Excluded VC_COV_UNR

 LINE       652
 EXPRESSION ((data_sel == ScrmblData) ? scrmbl_data_i : otp_rdata_i)
             ------------1-----------
-1-StatusTestsExclude Annotation
0CoveredT1,T2,T3
1Excluded VC_COV_UNR

 LINE       652
 SUB-EXPRESSION (data_sel == ScrmblData)
                ------------1-----------
-1-StatusTestsExclude Annotation
0CoveredT1,T2,T3
1Excluded VC_COV_UNR

 LINE       678
 EXPRESSION (init_done_o ? data : DataDefault)
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

FSM Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf
Summary for FSM :: state_q
TotalCoveredPercent
States 8 8 100.00 (Not included in score)
Transitions 16 15 93.75
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTestsExclude Annotation
CnstyReadSt 334 Covered T2,T3,T4
CnstyReadWaitSt 352 Covered T2,T3,T4
ErrorSt 286 Covered T1,T2,T4
IdleSt 369 Covered T1,T2,T3
InitDescrSt 276 Excluded VC_COV_UNR
InitDescrWaitSt 303 Excluded VC_COV_UNR
InitSt 246 Covered T1,T2,T3
InitWaitSt 256 Covered T1,T2,T3
IntegDigClrSt 272 Covered T1,T2,T3
IntegDigFinSt 491 Excluded VC_COV_UNR
IntegDigPadSt 493 Excluded VC_COV_UNR
IntegDigSt 434 Excluded VC_COV_UNR
IntegDigWaitSt 532 Excluded VC_COV_UNR
IntegScrSt 427 Excluded VC_COV_UNR
IntegScrWaitSt 460 Excluded VC_COV_UNR
ResetSt 244 Covered T1,T2,T3


transitionsLine No.CoveredTestsExclude Annotation
CnstyReadSt->CnstyReadWaitSt 352 Covered T2,T3,T4
CnstyReadSt->ErrorSt 596 Covered T2,T4,T58
CnstyReadWaitSt->CnstyReadSt 390 Covered T2,T3,T4
CnstyReadWaitSt->ErrorSt 373 Covered T32,T23,T21
CnstyReadWaitSt->IdleSt 369 Covered T2,T3,T4
IdleSt->CnstyReadSt 334 Covered T2,T3,T4
IdleSt->ErrorSt 596 Covered T4,T6,T10
IdleSt->IntegDigClrSt 326 Excluded VC_COV_UNR
InitDescrSt->ErrorSt 596 Excluded
InitDescrSt->InitDescrWaitSt 303 Excluded
InitDescrWaitSt->ErrorSt 596 Excluded
InitDescrWaitSt->InitSt 315 Excluded
InitSt->ErrorSt 596 Covered T1,T7,T60
InitSt->InitWaitSt 256 Covered T1,T2,T3
InitWaitSt->ErrorSt 286 Covered T22,T36,T132
InitWaitSt->InitDescrSt 276 Excluded
InitWaitSt->InitSt 278 Covered T1,T2,T3
InitWaitSt->IntegDigClrSt 272 Covered T1,T2,T3
IntegDigClrSt->ErrorSt 596 Not Covered
IntegDigClrSt->IdleSt 443 Covered T1,T2,T3
IntegDigClrSt->IntegDigSt 434 Excluded
IntegDigClrSt->IntegScrSt 427 Excluded
IntegDigFinSt->ErrorSt 596 Excluded
IntegDigFinSt->IntegDigWaitSt 532 Excluded
IntegDigPadSt->ErrorSt 596 Excluded
IntegDigPadSt->IntegDigFinSt 520 Excluded
IntegDigSt->ErrorSt 596 Excluded
IntegDigSt->IntegDigFinSt 491 Excluded
IntegDigSt->IntegDigPadSt 493 Excluded
IntegDigSt->IntegScrSt 504 Excluded
IntegDigWaitSt->ErrorSt 560 Excluded
IntegDigWaitSt->IdleSt 548 Excluded
IntegScrSt->ErrorSt 596 Excluded
IntegScrSt->IntegScrWaitSt 460 Excluded
IntegScrWaitSt->ErrorSt 596 Excluded
IntegScrWaitSt->IntegDigSt 470 Excluded
ResetSt->ErrorSt 596 Covered T69,T70,T71
ResetSt->InitSt 246 Covered T1,T2,T3


Summary for FSM :: error_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 5 5 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: error_q
statesLine No.CoveredTests
CheckFailError 374 Covered T21,T52,T53
FsmStateError 574 Covered T1,T2,T4
MacroEccCorrError 283 Covered T20,T32,T21
NoError 573 Covered T1,T2,T3


transitionsLine No.CoveredTestsExclude Annotation
CheckFailError->FsmStateError 606 Excluded VC_COV_UNR
CheckFailError->MacroEccCorrError 283 Excluded VC_COV_UNR
FsmStateError->CheckFailError 374 Excluded VC_COV_UNR
FsmStateError->MacroEccCorrError 283 Excluded VC_COV_UNR
MacroEccCorrError->CheckFailError 374 Covered T21,T53,T29
MacroEccCorrError->FsmStateError 606 Covered T20,T49,T35
NoError->CheckFailError 374 Covered T52,T133,T134
NoError->FsmStateError 574 Covered T1,T2,T4
NoError->MacroEccCorrError 283 Covered T20,T32,T21



Branch Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf
Line No.TotalCoveredPercent
Branches 39 39 100.00
TERNARY 636 1 1 100.00
TERNARY 652 1 1 100.00
TERNARY 678 2 2 100.00
CASE 240 27 27 100.00
IF 595 1 1 100.00
IF 602 3 3 100.00
IF 750 2 2 100.00
IF 753 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 636 ((base_sel == DigOffset)) ?

Branches:
-1-StatusTestsExclude Annotation
1 Excluded VC_COV_UNR
0 Covered T1,T2,T3


LineNo. Expression -1-: 652 ((data_sel == ScrmblData)) ?

Branches:
-1-StatusTestsExclude Annotation
1 Excluded VC_COV_UNR
0 Covered T1,T2,T3


LineNo. Expression -1-: 678 (init_done_o) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 240 case (state_q) -2-: 245 if (init_req_i) -3-: 255 if (otp_gnt_i) -4-: 265 if (otp_rvalid_i) -5-: 267 if ((otp_err inside {NoError, MacroEccCorrError})) -6-: 271 if ((cnt == LastScrmblBlock)) -7-: 275 if (1'b0) -8-: 282 if ((otp_err != NoError)) -9-: 302 if ((scrmbl_mtx_gnt_i && scrmbl_ready_i)) -10-: 314 if (scrmbl_valid_i) -11-: 324 if (integ_chk_req_i) -12-: 325 if (1'b0) -13-: 333 if (cnsty_chk_req_i) -14-: 348 if (1'b0) -15-: 351 if (otp_gnt_i) -16-: 362 if (otp_rvalid_i) -17-: 363 if ((otp_err inside {NoError, MacroEccCorrError})) -18-: 366 if (1'b0) -19-: 368 if (((digest_o == data_mux) || (digest_o == '0))) -20-: 381 if (((scrmbl_data_o == data_mux) || lc_ctrl_pkg::lc_tx_test_true_strict(check_byp_en_i))) -21-: 385 if ((cnt == LastScrmblBlock)) -22-: 401 if ((otp_err != NoError)) -23-: 417 if (1'b0) -24-: 424 if (1'b0) -25-: 426 if ((scrmbl_mtx_gnt_i && scrmbl_ready_i)) -26-: 433 if ((scrmbl_mtx_gnt_i && scrmbl_ready_i)) -27-: 444 if (prim_mubi_pkg::mubi8_test_true_strict(dout_locked_q)) -28-: 459 if (scrmbl_ready_i) -29-: 469 if (scrmbl_valid_i) -30-: 482 if (scrmbl_ready_i) -31-: 485 if ((cnt == PenultimateScrmblBlock)) -32-: 489 if (cnt[0]) -33-: 498 if (cnt[0]) -34-: 503 if (1'b0) -35-: 519 if (scrmbl_ready_i) -36-: 531 if (scrmbl_ready_i) -37-: 544 if (scrmbl_valid_i) -38-: 547 if (((digest_o == data_mux) || (digest_o == '0))) -39-: 551 if (prim_mubi_pkg::mubi8_test_true_strict(dout_locked_q)) -40-: 573 if ((error_q == NoError))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15--16--17--18--19--20--21--22--23--24--25--26--27--28--29--30--31--32--33--34--35--36--37--38--39--40-StatusTestsExclude Annotation
ResetSt 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
ResetSt 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
InitSt - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
InitSt - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
InitWaitSt - - 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
InitWaitSt - - 1 1 0 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Unreachable
InitWaitSt - - 1 1 0 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
InitWaitSt - - 1 1 - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T20,T21,T49
InitWaitSt - - 1 1 - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
InitWaitSt - - 1 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T22,T36,T76
InitWaitSt - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
InitDescrSt - - - - - - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Unreachable
InitDescrSt - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Excluded VC_COV_UNR
InitDescrWaitSt - - - - - - - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Unreachable
InitDescrWaitSt - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Excluded VC_COV_UNR
IdleSt - - - - - - - - - 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - Unreachable
IdleSt - - - - - - - - - 1 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T2,T3,T4
IdleSt - - - - - - - - - 0 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T2,T3,T4
IdleSt - - - - - - - - - 0 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
CnstyReadSt - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - Unreachable
CnstyReadSt - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T2,T3,T4
CnstyReadSt - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - Covered T2,T3,T4
CnstyReadSt - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - Covered T2,T3,T4
CnstyReadWaitSt - - - - - - - - - - - - - - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - Unreachable
CnstyReadWaitSt - - - - - - - - - - - - - - 1 1 1 0 - - - - - - - - - - - - - - - - - - - - - Unreachable
CnstyReadWaitSt - - - - - - - - - - - - - - 1 1 0 - 1 1 - - - - - - - - - - - - - - - - - - - Covered T2,T3,T4
CnstyReadWaitSt - - - - - - - - - - - - - - 1 1 0 - 1 0 - - - - - - - - - - - - - - - - - - - Covered T2,T3,T4
CnstyReadWaitSt - - - - - - - - - - - - - - 1 1 0 - 0 - - - - - - - - - - - - - - - - - - - - Covered T21,T52,T53
CnstyReadWaitSt - - - - - - - - - - - - - - 1 1 - - - - 1 - - - - - - - - - - - - - - - - - - Covered T32,T50,T51
CnstyReadWaitSt - - - - - - - - - - - - - - 1 1 - - - - 0 - - - - - - - - - - - - - - - - - - Covered T2,T3,T4
CnstyReadWaitSt - - - - - - - - - - - - - - 1 0 - - - - - - - - - - - - - - - - - - - - - - - Covered T54,T77,T78
CnstyReadWaitSt - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - Covered T2,T3,T4
IntegDigClrSt - - - - - - - - - - - - - - - - - - - - - 1 1 1 - - - - - - - - - - - - - - - Unreachable
IntegDigClrSt - - - - - - - - - - - - - - - - - - - - - 1 1 0 - - - - - - - - - - - - - - - Excluded VC_COV_UNR
IntegDigClrSt - - - - - - - - - - - - - - - - - - - - - 1 0 - 1 - - - - - - - - - - - - - - Unreachable
IntegDigClrSt - - - - - - - - - - - - - - - - - - - - - 1 0 - 0 - - - - - - - - - - - - - - Excluded VC_COV_UNR
IntegDigClrSt - - - - - - - - - - - - - - - - - - - - - 0 - - - 1 - - - - - - - - - - - - - Covered T1,T2,T3
IntegDigClrSt - - - - - - - - - - - - - - - - - - - - - 0 - - - 0 - - - - - - - - - - - - - Excluded VC_COV_UNR
IntegScrSt - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - Unreachable
IntegScrSt - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - Excluded VC_COV_UNR
IntegScrWaitSt - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - Unreachable
IntegScrWaitSt - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - Excluded VC_COV_UNR
IntegDigSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 - - - - - - - - Unreachable
IntegDigSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 0 - - - - - - - - Unreachable
IntegDigSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 0 - 1 - - - - - - - Unreachable
IntegDigSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 0 - 0 - - - - - - - Excluded VC_COV_UNR
IntegDigSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 0 - - 1 - - - - - - Unreachable
IntegDigSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 0 - - 0 - - - - - - Excluded VC_COV_UNR
IntegDigSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - Excluded VC_COV_UNR
IntegDigPadSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - Unreachable
IntegDigPadSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - Excluded VC_COV_UNR
IntegDigFinSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - - Unreachable
IntegDigFinSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - Excluded VC_COV_UNR
IntegDigWaitSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 - Unreachable
IntegDigWaitSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 0 - Unreachable
IntegDigWaitSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 0 - - Unreachable
IntegDigWaitSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - Excluded VC_COV_UNR
ErrorSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 Covered T17,T18,T19
ErrorSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 Covered T1,T2,T4
default - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T17,T18,T19


LineNo. Expression -1-: 595 if (ecc_err) -2-: 597 if ((state_q != ErrorSt))

Branches:
-1--2-StatusTestsExclude Annotation
1 1 Excluded VC_COV_UNR
1 0 Excluded VC_COV_UNR
0 - Covered T1,T2,T3


LineNo. Expression -1-: 602 if ((lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i) || cnt_err)) -2-: 605 if ((state_q != ErrorSt))

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T4
1 0 Covered T1,T2,T4
0 - Covered T1,T2,T3


LineNo. Expression -1-: 750 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 753 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 33 33 100.00 27 81.82
Cover properties 0 0 0
Cover sequences 0 0 0
Total 33 33 100.00 27 81.82




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AccessKnown_A 480569264 479686794 0 0
BypassEnable0_A 480569264 0 0 0
BypassEnable1_A 480569264 0 0 0
CnstyChkAckKnown_A 480569264 479686794 0 0
DataKnown_A 480569264 479686794 0 0
DigestKnown_A 480569264 479686794 0 0
DigestOffsetMustBeRepresentable_A 1153 1153 0 0
EccErrorState_A 480569264 0 0 0
ErrorKnown_A 480569264 479686794 0 0
InitDoneKnown_A 480569264 479686794 0 0
InitReadLocksPartition_A 480569264 97533448 0 0
InitWriteLocksPartition_A 480569264 97533448 0 0
IntegChkAckKnown_A 480569264 479686794 0 0
OffsetMustBeBlockAligned_A 1153 1153 0 0
OtpAddrKnown_A 480569264 479686794 0 0
OtpCmdKnown_A 480569264 479686794 0 0
OtpErrorState_A 480569264 12 0 0
OtpReqKnown_A 480569264 479686794 0 0
OtpSizeKnown_A 480569264 479686794 0 0
OtpWdataKnown_A 480569264 479686794 0 0
ReadLockImpliesDigest_A 480569264 0 0 0
ReadLockPropagation_A 480569264 479686794 0 0
ScrambledImpliesDigest_A 480569264 0 0 0
ScrmblCmdKnown_A 480569264 479686794 0 0
ScrmblDataKnown_A 480569264 479686794 0 0
ScrmblModeKnown_A 480569264 479686794 0 0
ScrmblMtxReqKnown_A 480569264 479686794 0 0
ScrmblSelKnown_A 480569264 479686794 0 0
ScrmblValidKnown_A 480569264 479686794 0 0
SizeMustBeBlockAligned_A 1153 1153 0 0
WriteLockImpliesDigest_A 480569264 0 0 0
WriteLockPropagation_A 480569264 479686794 0 0
u_state_regs_A 480569264 479686794 0 0


AccessKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 480569264 479686794 0 0
T1 11275 10981 0 0
T2 433300 433283 0 0
T3 98167 96843 0 0
T4 478748 478713 0 0
T6 842410 842382 0 0
T7 12333 12056 0 0
T8 5262 5208 0 0
T9 22582 22152 0 0
T10 206650 206080 0 0
T11 28596 27992 0 0

BypassEnable0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 480569264 0 0 0

BypassEnable1_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 480569264 0 0 0

CnstyChkAckKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 480569264 479686794 0 0
T1 11275 10981 0 0
T2 433300 433283 0 0
T3 98167 96843 0 0
T4 478748 478713 0 0
T6 842410 842382 0 0
T7 12333 12056 0 0
T8 5262 5208 0 0
T9 22582 22152 0 0
T10 206650 206080 0 0
T11 28596 27992 0 0

DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 480569264 479686794 0 0
T1 11275 10981 0 0
T2 433300 433283 0 0
T3 98167 96843 0 0
T4 478748 478713 0 0
T6 842410 842382 0 0
T7 12333 12056 0 0
T8 5262 5208 0 0
T9 22582 22152 0 0
T10 206650 206080 0 0
T11 28596 27992 0 0

DigestKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 480569264 479686794 0 0
T1 11275 10981 0 0
T2 433300 433283 0 0
T3 98167 96843 0 0
T4 478748 478713 0 0
T6 842410 842382 0 0
T7 12333 12056 0 0
T8 5262 5208 0 0
T9 22582 22152 0 0
T10 206650 206080 0 0
T11 28596 27992 0 0

DigestOffsetMustBeRepresentable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1153 1153 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

EccErrorState_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 480569264 0 0 0

ErrorKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 480569264 479686794 0 0
T1 11275 10981 0 0
T2 433300 433283 0 0
T3 98167 96843 0 0
T4 478748 478713 0 0
T6 842410 842382 0 0
T7 12333 12056 0 0
T8 5262 5208 0 0
T9 22582 22152 0 0
T10 206650 206080 0 0
T11 28596 27992 0 0

InitDoneKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 480569264 479686794 0 0
T1 11275 10981 0 0
T2 433300 433283 0 0
T3 98167 96843 0 0
T4 478748 478713 0 0
T6 842410 842382 0 0
T7 12333 12056 0 0
T8 5262 5208 0 0
T9 22582 22152 0 0
T10 206650 206080 0 0
T11 28596 27992 0 0

InitReadLocksPartition_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 480569264 97533448 0 0
T1 11275 6071 0 0
T2 433300 275045 0 0
T3 98167 11514 0 0
T4 478748 282316 0 0
T6 842410 164431 0 0
T7 12333 6539 0 0
T8 5262 755 0 0
T9 22582 4597 0 0
T10 206650 398484 0 0
T11 28596 5895 0 0

InitWriteLocksPartition_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 480569264 97533448 0 0
T1 11275 6071 0 0
T2 433300 275045 0 0
T3 98167 11514 0 0
T4 478748 282316 0 0
T6 842410 164431 0 0
T7 12333 6539 0 0
T8 5262 755 0 0
T9 22582 4597 0 0
T10 206650 398484 0 0
T11 28596 5895 0 0

IntegChkAckKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 480569264 479686794 0 0
T1 11275 10981 0 0
T2 433300 433283 0 0
T3 98167 96843 0 0
T4 478748 478713 0 0
T6 842410 842382 0 0
T7 12333 12056 0 0
T8 5262 5208 0 0
T9 22582 22152 0 0
T10 206650 206080 0 0
T11 28596 27992 0 0

OffsetMustBeBlockAligned_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1153 1153 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

OtpAddrKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 480569264 479686794 0 0
T1 11275 10981 0 0
T2 433300 433283 0 0
T3 98167 96843 0 0
T4 478748 478713 0 0
T6 842410 842382 0 0
T7 12333 12056 0 0
T8 5262 5208 0 0
T9 22582 22152 0 0
T10 206650 206080 0 0
T11 28596 27992 0 0

OtpCmdKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 480569264 479686794 0 0
T1 11275 10981 0 0
T2 433300 433283 0 0
T3 98167 96843 0 0
T4 478748 478713 0 0
T6 842410 842382 0 0
T7 12333 12056 0 0
T8 5262 5208 0 0
T9 22582 22152 0 0
T10 206650 206080 0 0
T11 28596 27992 0 0

OtpErrorState_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 480569264 12 0 0
T22 13811 1 0 0
T35 14757 0 0 0
T36 0 1 0 0
T54 0 1 0 0
T76 0 1 0 0
T77 0 1 0 0
T78 0 1 0 0
T79 0 1 0 0
T80 0 1 0 0
T81 0 1 0 0
T82 0 1 0 0
T83 99555 0 0 0
T84 27129 0 0 0
T85 45761 0 0 0
T86 15379 0 0 0
T87 25130 0 0 0
T88 205584 0 0 0
T89 63734 0 0 0
T90 12304 0 0 0

OtpReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 480569264 479686794 0 0
T1 11275 10981 0 0
T2 433300 433283 0 0
T3 98167 96843 0 0
T4 478748 478713 0 0
T6 842410 842382 0 0
T7 12333 12056 0 0
T8 5262 5208 0 0
T9 22582 22152 0 0
T10 206650 206080 0 0
T11 28596 27992 0 0

OtpSizeKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 480569264 479686794 0 0
T1 11275 10981 0 0
T2 433300 433283 0 0
T3 98167 96843 0 0
T4 478748 478713 0 0
T6 842410 842382 0 0
T7 12333 12056 0 0
T8 5262 5208 0 0
T9 22582 22152 0 0
T10 206650 206080 0 0
T11 28596 27992 0 0

OtpWdataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 480569264 479686794 0 0
T1 11275 10981 0 0
T2 433300 433283 0 0
T3 98167 96843 0 0
T4 478748 478713 0 0
T6 842410 842382 0 0
T7 12333 12056 0 0
T8 5262 5208 0 0
T9 22582 22152 0 0
T10 206650 206080 0 0
T11 28596 27992 0 0

ReadLockImpliesDigest_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 480569264 0 0 0

ReadLockPropagation_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 480569264 479686794 0 0
T1 11275 10981 0 0
T2 433300 433283 0 0
T3 98167 96843 0 0
T4 478748 478713 0 0
T6 842410 842382 0 0
T7 12333 12056 0 0
T8 5262 5208 0 0
T9 22582 22152 0 0
T10 206650 206080 0 0
T11 28596 27992 0 0

ScrambledImpliesDigest_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 480569264 0 0 0

ScrmblCmdKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 480569264 479686794 0 0
T1 11275 10981 0 0
T2 433300 433283 0 0
T3 98167 96843 0 0
T4 478748 478713 0 0
T6 842410 842382 0 0
T7 12333 12056 0 0
T8 5262 5208 0 0
T9 22582 22152 0 0
T10 206650 206080 0 0
T11 28596 27992 0 0

ScrmblDataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 480569264 479686794 0 0
T1 11275 10981 0 0
T2 433300 433283 0 0
T3 98167 96843 0 0
T4 478748 478713 0 0
T6 842410 842382 0 0
T7 12333 12056 0 0
T8 5262 5208 0 0
T9 22582 22152 0 0
T10 206650 206080 0 0
T11 28596 27992 0 0

ScrmblModeKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 480569264 479686794 0 0
T1 11275 10981 0 0
T2 433300 433283 0 0
T3 98167 96843 0 0
T4 478748 478713 0 0
T6 842410 842382 0 0
T7 12333 12056 0 0
T8 5262 5208 0 0
T9 22582 22152 0 0
T10 206650 206080 0 0
T11 28596 27992 0 0

ScrmblMtxReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 480569264 479686794 0 0
T1 11275 10981 0 0
T2 433300 433283 0 0
T3 98167 96843 0 0
T4 478748 478713 0 0
T6 842410 842382 0 0
T7 12333 12056 0 0
T8 5262 5208 0 0
T9 22582 22152 0 0
T10 206650 206080 0 0
T11 28596 27992 0 0

ScrmblSelKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 480569264 479686794 0 0
T1 11275 10981 0 0
T2 433300 433283 0 0
T3 98167 96843 0 0
T4 478748 478713 0 0
T6 842410 842382 0 0
T7 12333 12056 0 0
T8 5262 5208 0 0
T9 22582 22152 0 0
T10 206650 206080 0 0
T11 28596 27992 0 0

ScrmblValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 480569264 479686794 0 0
T1 11275 10981 0 0
T2 433300 433283 0 0
T3 98167 96843 0 0
T4 478748 478713 0 0
T6 842410 842382 0 0
T7 12333 12056 0 0
T8 5262 5208 0 0
T9 22582 22152 0 0
T10 206650 206080 0 0
T11 28596 27992 0 0

SizeMustBeBlockAligned_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1153 1153 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

WriteLockImpliesDigest_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 480569264 0 0 0

WriteLockPropagation_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 480569264 479686794 0 0
T1 11275 10981 0 0
T2 433300 433283 0 0
T3 98167 96843 0 0
T4 478748 478713 0 0
T6 842410 842382 0 0
T7 12333 12056 0 0
T8 5262 5208 0 0
T9 22582 22152 0 0
T10 206650 206080 0 0
T11 28596 27992 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 480569264 479686794 0 0
T1 11275 10981 0 0
T2 433300 433283 0 0
T3 98167 96843 0 0
T4 478748 478713 0 0
T6 842410 842382 0 0
T7 12333 12056 0 0
T8 5262 5208 0 0
T9 22582 22152 0 0
T10 206650 206080 0 0
T11 28596 27992 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%