Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_otp_rsp_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.68 100.00 94.74 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.83 100.00 92.31 95.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.71 96.75 96.15 97.06 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 93.64 100.00 90.00 90.91



Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 fifo_h


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 fifo_h


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[0].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[0].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[1].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[1].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.36 95.00 87.10 83.33 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.64 100.00 94.55 100.00 100.00 u_tlul_adapter_sram


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 81.58 92.00 80.00 72.73



Module Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.36 95.00 87.10 83.33 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.64 100.00 94.55 100.00 100.00 u_tlul_adapter_sram


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 81.58 92.00 80.00 72.73



Module Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.37 95.00 89.47 85.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.64 100.00 94.55 100.00 100.00 u_tlul_adapter_sram


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 81.58 92.00 80.00 72.73

Line Coverage for Module : prim_fifo_sync ( parameter Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_tlul_adapter_sram.u_reqfifo

Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
133 1 1
134 1 1
138 1 1


Line Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_tlul_adapter_sram.u_sramreqfifo

Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
133 1 1
134 1 1
138 1 1


Line Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_tlul_adapter_sram.u_rspfifo

Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
130 1 1
131 1 1
138 1 1


Line Coverage for Module : prim_fifo_sync ( parameter Width=4,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
98.68 100.00
tb.dut.u_otp_rsp_fifo

Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
130 1 1
131 1 1
138 1 1


Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_tlul_adapter_sram.u_sramreqfifo

TotalCoveredPercent
Conditions161168.75
Logical161168.75
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_tlul_adapter_sram.u_rspfifo

TotalCoveredPercent
Conditions241875.00
Logical241875.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT2,T4,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T4,T6
110Not Covered
111CoveredT1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT2,T4,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_tlul_adapter_sram.u_reqfifo

TotalCoveredPercent
Conditions161168.75
Logical161168.75
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=4,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
98.68 94.74
tb.dut.u_otp_rsp_fifo

TotalCoveredPercent
Conditions241875.00
Logical241875.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (4'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=4,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :
SCOREBRANCH
100.00 100.00
tb.dut.u_tlul_adapter_sram.u_rspfifo

SCOREBRANCH
98.68 100.00
tb.dut.u_otp_rsp_fifo

Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Branch Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :
SCOREBRANCH
100.00 100.00
tb.dut.u_tlul_adapter_sram.u_reqfifo

SCOREBRANCH
100.00 100.00
tb.dut.u_tlul_adapter_sram.u_sramreqfifo

Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_fifo_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 2147483647 275134904 0 0
DepthKnown_A 2147483647 2147483647 0 0
RvalidKnown_A 2147483647 2147483647 0 0
WreadyKnown_A 2147483647 2147483647 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 1922277056 41458850 0 0
gen_passthru_fifo.paramCheckPass 7968 7968 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 275134904 0 0
T1 112750 6832 0 0
T2 4333000 1981514 0 0
T3 981670 92275 0 0
T4 4787480 1941270 0 0
T6 8424100 1932368 0 0
T7 123330 6696 0 0
T8 52620 1392 0 0
T9 225820 18831 0 0
T10 2066500 911794 0 0
T11 285960 25777 0 0
T26 0 483 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 112750 109810 0 0
T2 4333000 4332830 0 0
T3 981670 968430 0 0
T4 4787480 4787130 0 0
T6 8424100 8423820 0 0
T7 123330 120560 0 0
T8 52620 52080 0 0
T9 225820 221520 0 0
T10 2066500 2060800 0 0
T11 285960 279920 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 112750 109810 0 0
T2 4333000 4332830 0 0
T3 981670 968430 0 0
T4 4787480 4787130 0 0
T6 8424100 8423820 0 0
T7 123330 120560 0 0
T8 52620 52080 0 0
T9 225820 221520 0 0
T10 2066500 2060800 0 0
T11 285960 279920 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 112750 109810 0 0
T2 4333000 4332830 0 0
T3 981670 968430 0 0
T4 4787480 4787130 0 0
T6 8424100 8423820 0 0
T7 123330 120560 0 0
T8 52620 52080 0 0
T9 225820 221520 0 0
T10 2066500 2060800 0 0
T11 285960 279920 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 1922277056 41458850 0 0
T1 45100 3252 0 0
T2 1733200 399700 0 0
T3 392668 22887 0 0
T4 1914992 272848 0 0
T6 3369640 184526 0 0
T7 49332 3256 0 0
T8 21048 936 0 0
T9 90328 7491 0 0
T10 826600 167816 0 0
T11 114384 14005 0 0
T26 0 441 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 7968 7968 0 0
T1 6 6 0 0
T2 6 6 0 0
T3 6 6 0 0
T4 6 6 0 0
T6 6 6 0 0
T7 6 6 0 0
T8 6 6 0 0
T9 6 6 0 0
T10 6 6 0 0
T11 6 6 0 0

Line Coverage for Instance : tb.dut.u_otp_rsp_fifo
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
130 1 1
131 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_otp_rsp_fifo
TotalCoveredPercent
Conditions191894.74
Logical191894.74
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011CoveredT1,T2,T3
101Excluded VC_COV_UNR
110Excluded VC_COV_UNR
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011Excluded VC_COV_UNR
101CoveredT1,T2,T3
110Excluded VC_COV_UNR
111CoveredT1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (4'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_otp_rsp_fifo
Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_otp_rsp_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 480569264 18170337 0 0
DepthKnown_A 480569264 479686794 0 0
RvalidKnown_A 480569264 479686794 0 0
WreadyKnown_A 480569264 479686794 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 480569264 18170337 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 480569264 18170337 0 0
T1 11275 2895 0 0
T2 433300 249366 0 0
T3 98167 21822 0 0
T4 478748 100589 0 0
T6 842410 66466 0 0
T7 12333 2878 0 0
T8 5262 936 0 0
T9 22582 7218 0 0
T10 206650 117332 0 0
T11 28596 13524 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 480569264 479686794 0 0
T1 11275 10981 0 0
T2 433300 433283 0 0
T3 98167 96843 0 0
T4 478748 478713 0 0
T6 842410 842382 0 0
T7 12333 12056 0 0
T8 5262 5208 0 0
T9 22582 22152 0 0
T10 206650 206080 0 0
T11 28596 27992 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 480569264 479686794 0 0
T1 11275 10981 0 0
T2 433300 433283 0 0
T3 98167 96843 0 0
T4 478748 478713 0 0
T6 842410 842382 0 0
T7 12333 12056 0 0
T8 5262 5208 0 0
T9 22582 22152 0 0
T10 206650 206080 0 0
T11 28596 27992 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 480569264 479686794 0 0
T1 11275 10981 0 0
T2 433300 433283 0 0
T3 98167 96843 0 0
T4 478748 478713 0 0
T6 842410 842382 0 0
T7 12333 12056 0 0
T8 5262 5208 0 0
T9 22582 22152 0 0
T10 206650 206080 0 0
T11 28596 27992 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 480569264 18170337 0 0
T1 11275 2895 0 0
T2 433300 249366 0 0
T3 98167 21822 0 0
T4 478748 100589 0 0
T6 842410 66466 0 0
T7 12333 2878 0 0
T8 5262 936 0 0
T9 22582 7218 0 0
T10 206650 117332 0 0
T11 28596 13524 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 483546363 62590323 0 0
DepthKnown_A 483546363 482612310 0 0
RvalidKnown_A 483546363 482612310 0 0
WreadyKnown_A 483546363 482612310 0 0
gen_passthru_fifo.paramCheckPass 1328 1328 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 483546363 62590323 0 0
T1 11275 895 0 0
T2 433300 487283 0 0
T3 98167 17347 0 0
T4 478748 507621 0 0
T6 842410 146466 0 0
T7 12333 860 0 0
T8 5262 114 0 0
T9 22582 2835 0 0
T10 206650 67588 0 0
T11 28596 2943 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 483546363 482612310 0 0
T1 11275 10981 0 0
T2 433300 433283 0 0
T3 98167 96843 0 0
T4 478748 478713 0 0
T6 842410 842382 0 0
T7 12333 12056 0 0
T8 5262 5208 0 0
T9 22582 22152 0 0
T10 206650 206080 0 0
T11 28596 27992 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 483546363 482612310 0 0
T1 11275 10981 0 0
T2 433300 433283 0 0
T3 98167 96843 0 0
T4 478748 478713 0 0
T6 842410 842382 0 0
T7 12333 12056 0 0
T8 5262 5208 0 0
T9 22582 22152 0 0
T10 206650 206080 0 0
T11 28596 27992 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 483546363 482612310 0 0
T1 11275 10981 0 0
T2 433300 433283 0 0
T3 98167 96843 0 0
T4 478748 478713 0 0
T6 842410 842382 0 0
T7 12333 12056 0 0
T8 5262 5208 0 0
T9 22582 22152 0 0
T10 206650 206080 0 0
T11 28596 27992 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1328 1328 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 483546363 58903740 0 0
DepthKnown_A 483546363 482612310 0 0
RvalidKnown_A 483546363 482612310 0 0
WreadyKnown_A 483546363 482612310 0 0
gen_passthru_fifo.paramCheckPass 1328 1328 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 483546363 58903740 0 0
T1 11275 895 0 0
T2 433300 310396 0 0
T3 98167 17347 0 0
T4 478748 333410 0 0
T6 842410 252376 0 0
T7 12333 860 0 0
T8 5262 114 0 0
T9 22582 2835 0 0
T10 206650 304401 0 0
T11 28596 2943 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 483546363 482612310 0 0
T1 11275 10981 0 0
T2 433300 433283 0 0
T3 98167 96843 0 0
T4 478748 478713 0 0
T6 842410 842382 0 0
T7 12333 12056 0 0
T8 5262 5208 0 0
T9 22582 22152 0 0
T10 206650 206080 0 0
T11 28596 27992 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 483546363 482612310 0 0
T1 11275 10981 0 0
T2 433300 433283 0 0
T3 98167 96843 0 0
T4 478748 478713 0 0
T6 842410 842382 0 0
T7 12333 12056 0 0
T8 5262 5208 0 0
T9 22582 22152 0 0
T10 206650 206080 0 0
T11 28596 27992 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 483546363 482612310 0 0
T1 11275 10981 0 0
T2 433300 433283 0 0
T3 98167 96843 0 0
T4 478748 478713 0 0
T6 842410 842382 0 0
T7 12333 12056 0 0
T8 5262 5208 0 0
T9 22582 22152 0 0
T10 206650 206080 0 0
T11 28596 27992 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1328 1328 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 483546363 26950246 0 0
DepthKnown_A 483546363 482612310 0 0
RvalidKnown_A 483546363 482612310 0 0
WreadyKnown_A 483546363 482612310 0 0
gen_passthru_fifo.paramCheckPass 1328 1328 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 483546363 26950246 0 0
T1 11275 17 0 0
T2 433300 306413 0 0
T3 98167 115 0 0
T4 478748 306083 0 0
T6 842410 587909 0 0
T7 12333 18 0 0
T8 5262 0 0 0
T9 22582 13 0 0
T10 206650 2032 0 0
T11 28596 35 0 0
T26 0 21 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 483546363 482612310 0 0
T1 11275 10981 0 0
T2 433300 433283 0 0
T3 98167 96843 0 0
T4 478748 478713 0 0
T6 842410 842382 0 0
T7 12333 12056 0 0
T8 5262 5208 0 0
T9 22582 22152 0 0
T10 206650 206080 0 0
T11 28596 27992 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 483546363 482612310 0 0
T1 11275 10981 0 0
T2 433300 433283 0 0
T3 98167 96843 0 0
T4 478748 478713 0 0
T6 842410 842382 0 0
T7 12333 12056 0 0
T8 5262 5208 0 0
T9 22582 22152 0 0
T10 206650 206080 0 0
T11 28596 27992 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 483546363 482612310 0 0
T1 11275 10981 0 0
T2 433300 433283 0 0
T3 98167 96843 0 0
T4 478748 478713 0 0
T6 842410 842382 0 0
T7 12333 12056 0 0
T8 5262 5208 0 0
T9 22582 22152 0 0
T10 206650 206080 0 0
T11 28596 27992 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1328 1328 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 483546363 21698835 0 0
DepthKnown_A 483546363 482612310 0 0
RvalidKnown_A 483546363 482612310 0 0
WreadyKnown_A 483546363 482612310 0 0
gen_passthru_fifo.paramCheckPass 1328 1328 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 483546363 21698835 0 0
T1 11275 17 0 0
T2 433300 150003 0 0
T3 98167 115 0 0
T4 478748 152750 0 0
T6 842410 110107 0 0
T7 12333 18 0 0
T8 5262 0 0 0
T9 22582 13 0 0
T10 206650 8773 0 0
T11 28596 35 0 0
T26 0 21 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 483546363 482612310 0 0
T1 11275 10981 0 0
T2 433300 433283 0 0
T3 98167 96843 0 0
T4 478748 478713 0 0
T6 842410 842382 0 0
T7 12333 12056 0 0
T8 5262 5208 0 0
T9 22582 22152 0 0
T10 206650 206080 0 0
T11 28596 27992 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 483546363 482612310 0 0
T1 11275 10981 0 0
T2 433300 433283 0 0
T3 98167 96843 0 0
T4 478748 478713 0 0
T6 842410 842382 0 0
T7 12333 12056 0 0
T8 5262 5208 0 0
T9 22582 22152 0 0
T10 206650 206080 0 0
T11 28596 27992 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 483546363 482612310 0 0
T1 11275 10981 0 0
T2 433300 433283 0 0
T3 98167 96843 0 0
T4 478748 478713 0 0
T6 842410 842382 0 0
T7 12333 12056 0 0
T8 5262 5208 0 0
T9 22582 22152 0 0
T10 206650 206080 0 0
T11 28596 27992 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1328 1328 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 483546363 26328005 0 0
DepthKnown_A 483546363 482612310 0 0
RvalidKnown_A 483546363 482612310 0 0
WreadyKnown_A 483546363 482612310 0 0
gen_passthru_fifo.paramCheckPass 1328 1328 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 483546363 26328005 0 0
T1 11275 878 0 0
T2 433300 167326 0 0
T3 98167 17232 0 0
T4 478748 187898 0 0
T6 842410 508716 0 0
T7 12333 842 0 0
T8 5262 114 0 0
T9 22582 2822 0 0
T10 206650 65556 0 0
T11 28596 2908 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 483546363 482612310 0 0
T1 11275 10981 0 0
T2 433300 433283 0 0
T3 98167 96843 0 0
T4 478748 478713 0 0
T6 842410 842382 0 0
T7 12333 12056 0 0
T8 5262 5208 0 0
T9 22582 22152 0 0
T10 206650 206080 0 0
T11 28596 27992 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 483546363 482612310 0 0
T1 11275 10981 0 0
T2 433300 433283 0 0
T3 98167 96843 0 0
T4 478748 478713 0 0
T6 842410 842382 0 0
T7 12333 12056 0 0
T8 5262 5208 0 0
T9 22582 22152 0 0
T10 206650 206080 0 0
T11 28596 27992 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 483546363 482612310 0 0
T1 11275 10981 0 0
T2 433300 433283 0 0
T3 98167 96843 0 0
T4 478748 478713 0 0
T6 842410 842382 0 0
T7 12333 12056 0 0
T8 5262 5208 0 0
T9 22582 22152 0 0
T10 206650 206080 0 0
T11 28596 27992 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1328 1328 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 483546363 37204905 0 0
DepthKnown_A 483546363 482612310 0 0
RvalidKnown_A 483546363 482612310 0 0
WreadyKnown_A 483546363 482612310 0 0
gen_passthru_fifo.paramCheckPass 1328 1328 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 483546363 37204905 0 0
T1 11275 878 0 0
T2 433300 160393 0 0
T3 98167 17232 0 0
T4 478748 180660 0 0
T6 842410 142268 0 0
T7 12333 842 0 0
T8 5262 114 0 0
T9 22582 2822 0 0
T10 206650 295628 0 0
T11 28596 2908 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 483546363 482612310 0 0
T1 11275 10981 0 0
T2 433300 433283 0 0
T3 98167 96843 0 0
T4 478748 478713 0 0
T6 842410 842382 0 0
T7 12333 12056 0 0
T8 5262 5208 0 0
T9 22582 22152 0 0
T10 206650 206080 0 0
T11 28596 27992 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 483546363 482612310 0 0
T1 11275 10981 0 0
T2 433300 433283 0 0
T3 98167 96843 0 0
T4 478748 478713 0 0
T6 842410 842382 0 0
T7 12333 12056 0 0
T8 5262 5208 0 0
T9 22582 22152 0 0
T10 206650 206080 0 0
T11 28596 27992 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 483546363 482612310 0 0
T1 11275 10981 0 0
T2 433300 433283 0 0
T3 98167 96843 0 0
T4 478748 478713 0 0
T6 842410 842382 0 0
T7 12333 12056 0 0
T8 5262 5208 0 0
T9 22582 22152 0 0
T10 206650 206080 0 0
T11 28596 27992 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1328 1328 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo
Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
133 1 1
134 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo
TotalCoveredPercent
Conditions1111100.00
Logical1111100.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011CoveredT1,T2,T3
101Excluded VC_COV_UNR
110Excluded VC_COV_UNR
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011Excluded VC_COV_UNR
101CoveredT1,T2,T3
110Excluded VC_COV_UNR
111CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 480569264 22286907 0 0
DepthKnown_A 480569264 479686794 0 0
RvalidKnown_A 480569264 479686794 0 0
WreadyKnown_A 480569264 479686794 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 480569264 22286907 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 480569264 22286907 0 0
T1 11275 170 0 0
T2 433300 150052 0 0
T3 98167 475 0 0
T4 478748 160233 0 0
T6 842410 110478 0 0
T7 12333 180 0 0
T8 5262 0 0 0
T9 22582 130 0 0
T10 206650 24226 0 0
T11 28596 223 0 0
T26 0 210 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 480569264 479686794 0 0
T1 11275 10981 0 0
T2 433300 433283 0 0
T3 98167 96843 0 0
T4 478748 478713 0 0
T6 842410 842382 0 0
T7 12333 12056 0 0
T8 5262 5208 0 0
T9 22582 22152 0 0
T10 206650 206080 0 0
T11 28596 27992 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 480569264 479686794 0 0
T1 11275 10981 0 0
T2 433300 433283 0 0
T3 98167 96843 0 0
T4 478748 478713 0 0
T6 842410 842382 0 0
T7 12333 12056 0 0
T8 5262 5208 0 0
T9 22582 22152 0 0
T10 206650 206080 0 0
T11 28596 27992 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 480569264 479686794 0 0
T1 11275 10981 0 0
T2 433300 433283 0 0
T3 98167 96843 0 0
T4 478748 478713 0 0
T6 842410 842382 0 0
T7 12333 12056 0 0
T8 5262 5208 0 0
T9 22582 22152 0 0
T10 206650 206080 0 0
T11 28596 27992 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 480569264 22286907 0 0
T1 11275 170 0 0
T2 433300 150052 0 0
T3 98167 475 0 0
T4 478748 160233 0 0
T6 842410 110478 0 0
T7 12333 180 0 0
T8 5262 0 0 0
T9 22582 130 0 0
T10 206650 24226 0 0
T11 28596 223 0 0
T26 0 210 0 0

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo
Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
133 1 1
134 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo
TotalCoveredPercent
Conditions1111100.00
Logical1111100.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011CoveredT1,T2,T3
101Excluded VC_COV_UNR
110Excluded VC_COV_UNR
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011Excluded VC_COV_UNR
101CoveredT1,T2,T3
110Excluded VC_COV_UNR
111CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 480569264 726457 0 0
DepthKnown_A 480569264 479686794 0 0
RvalidKnown_A 480569264 479686794 0 0
WreadyKnown_A 480569264 479686794 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 480569264 726457 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 480569264 726457 0 0
T1 11275 170 0 0
T2 433300 155 0 0
T3 98167 475 0 0
T4 478748 8476 0 0
T6 842410 4401 0 0
T7 12333 180 0 0
T8 5262 0 0 0
T9 22582 130 0 0
T10 206650 17485 0 0
T11 28596 223 0 0
T26 0 210 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 480569264 479686794 0 0
T1 11275 10981 0 0
T2 433300 433283 0 0
T3 98167 96843 0 0
T4 478748 478713 0 0
T6 842410 842382 0 0
T7 12333 12056 0 0
T8 5262 5208 0 0
T9 22582 22152 0 0
T10 206650 206080 0 0
T11 28596 27992 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 480569264 479686794 0 0
T1 11275 10981 0 0
T2 433300 433283 0 0
T3 98167 96843 0 0
T4 478748 478713 0 0
T6 842410 842382 0 0
T7 12333 12056 0 0
T8 5262 5208 0 0
T9 22582 22152 0 0
T10 206650 206080 0 0
T11 28596 27992 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 480569264 479686794 0 0
T1 11275 10981 0 0
T2 433300 433283 0 0
T3 98167 96843 0 0
T4 478748 478713 0 0
T6 842410 842382 0 0
T7 12333 12056 0 0
T8 5262 5208 0 0
T9 22582 22152 0 0
T10 206650 206080 0 0
T11 28596 27992 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 480569264 726457 0 0
T1 11275 170 0 0
T2 433300 155 0 0
T3 98167 475 0 0
T4 478748 8476 0 0
T6 842410 4401 0 0
T7 12333 180 0 0
T8 5262 0 0 0
T9 22582 130 0 0
T10 206650 17485 0 0
T11 28596 223 0 0
T26 0 210 0 0

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo
Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
130 1 1
131 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo
TotalCoveredPercent
Conditions1818100.00
Logical1818100.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT2,T4,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011CoveredT1,T2,T3
101Excluded VC_COV_UNR
110Excluded VC_COV_UNR
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011Excluded VC_COV_UNR
101CoveredT2,T4,T6
110Excluded VC_COV_UNR
111CoveredT1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT2,T4,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo
Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 480569264 275149 0 0
DepthKnown_A 480569264 479686794 0 0
RvalidKnown_A 480569264 479686794 0 0
WreadyKnown_A 480569264 479686794 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 480569264 275149 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 480569264 275149 0 0
T1 11275 17 0 0
T2 433300 127 0 0
T3 98167 115 0 0
T4 478748 3550 0 0
T6 842410 3181 0 0
T7 12333 18 0 0
T8 5262 0 0 0
T9 22582 13 0 0
T10 206650 8773 0 0
T11 28596 35 0 0
T26 0 21 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 480569264 479686794 0 0
T1 11275 10981 0 0
T2 433300 433283 0 0
T3 98167 96843 0 0
T4 478748 478713 0 0
T6 842410 842382 0 0
T7 12333 12056 0 0
T8 5262 5208 0 0
T9 22582 22152 0 0
T10 206650 206080 0 0
T11 28596 27992 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 480569264 479686794 0 0
T1 11275 10981 0 0
T2 433300 433283 0 0
T3 98167 96843 0 0
T4 478748 478713 0 0
T6 842410 842382 0 0
T7 12333 12056 0 0
T8 5262 5208 0 0
T9 22582 22152 0 0
T10 206650 206080 0 0
T11 28596 27992 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 480569264 479686794 0 0
T1 11275 10981 0 0
T2 433300 433283 0 0
T3 98167 96843 0 0
T4 478748 478713 0 0
T6 842410 842382 0 0
T7 12333 12056 0 0
T8 5262 5208 0 0
T9 22582 22152 0 0
T10 206650 206080 0 0
T11 28596 27992 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 480569264 275149 0 0
T1 11275 17 0 0
T2 433300 127 0 0
T3 98167 115 0 0
T4 478748 3550 0 0
T6 842410 3181 0 0
T7 12333 18 0 0
T8 5262 0 0 0
T9 22582 13 0 0
T10 206650 8773 0 0
T11 28596 35 0 0
T26 0 21 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%