Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.20	94.16	96.15	97.08		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	445460873	7409288	0	0
check_regwen_rd_A	445460873	3589	0	0
check_timeout_rd_A	445460873	3540	0	0
check_trigger_regwen_rd_A	445460873	3946	0	0
consistency_check_period_rd_A	445460873	4068	0	0
creator_sw_cfg_read_lock_rd_A	445460873	3510	0	0
direct_access_address_rd_A	445460873	2404	0	0
direct_access_wdata_0_rd_A	445460873	1591	0	0
direct_access_wdata_1_rd_A	445460873	1833	0	0
integrity_check_period_rd_A	445460873	3679	0	0
intr_enable_rd_A	445460873	4550	0	0
owner_sw_cfg_read_lock_rd_A	445460873	3302	0	0
rot_creator_auth_codesign_read_lock_rd_A	445460873	3524	0	0
rot_creator_auth_state_read_lock_rd_A	445460873	3339	0	0
vendor_test_read_lock_rd_A	445460873	3166	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445460873	7409288	0	0
T7	200484	58222	0	0
T15	0	58461	0	0
T16	0	5108	0	0
T20	0	151489	0	0
T21	0	13127	0	0
T22	0	76051	0	0
T32	0	54530	0	0
T55	68304	0	0	0
T103	9674	0	0	0
T104	188082	0	0	0
T105	26842	0	0	0
T110	30122	0	0	0
T115	94924	0	0	0
T116	155859	0	0	0
T117	54542	0	0	0
T160	0	57300	0	0
T184	12955	0	0	0
T281	0	44332	0	0
T302	0	58816	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445460873	3589	0	0
T21	625203	42	0	0
T22	0	35	0	0
T23	0	21	0	0
T32	359492	60	0	0
T39	18608	0	0	0
T59	14299	0	0	0
T158	0	138	0	0
T160	0	59	0	0
T220	12995	0	0	0
T280	61497	0	0	0
T281	231246	77	0	0
T310	0	194	0	0
T389	0	35	0	0
T390	0	43	0	0
T391	127167	0	0	0
T392	45945	0	0	0
T393	14489	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445460873	3540	0	0
T21	625203	32	0	0
T22	0	70	0	0
T23	0	33	0	0
T32	359492	64	0	0
T39	18608	0	0	0
T59	14299	0	0	0
T158	0	108	0	0
T160	0	32	0	0
T220	12995	0	0	0
T280	61497	0	0	0
T281	231246	55	0	0
T310	0	202	0	0
T389	0	66	0	0
T390	0	56	0	0
T391	127167	0	0	0
T392	45945	0	0	0
T393	14489	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445460873	3946	0	0
T21	625203	49	0	0
T22	0	53	0	0
T23	0	19	0	0
T32	359492	56	0	0
T39	18608	0	0	0
T59	14299	0	0	0
T158	0	133	0	0
T160	0	38	0	0
T220	12995	0	0	0
T280	61497	0	0	0
T281	231246	56	0	0
T310	0	249	0	0
T389	0	68	0	0
T390	0	66	0	0
T391	127167	0	0	0
T392	45945	0	0	0
T393	14489	0	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445460873	4068	0	0
T21	625203	25	0	0
T22	0	86	0	0
T23	0	14	0	0
T32	359492	77	0	0
T39	18608	0	0	0
T59	14299	0	0	0
T158	0	166	0	0
T160	0	27	0	0
T220	12995	0	0	0
T280	61497	0	0	0
T281	231246	43	0	0
T310	0	135	0	0
T389	0	60	0	0
T390	0	68	0	0
T391	127167	0	0	0
T392	45945	0	0	0
T393	14489	0	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445460873	3510	0	0
T21	625203	10	0	0
T22	0	91	0	0
T23	0	22	0	0
T32	359492	51	0	0
T39	18608	0	0	0
T59	14299	0	0	0
T158	0	161	0	0
T160	0	56	0	0
T220	12995	0	0	0
T280	61497	0	0	0
T281	231246	57	0	0
T310	0	177	0	0
T389	0	28	0	0
T390	0	50	0	0
T391	127167	0	0	0
T392	45945	0	0	0
T393	14489	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445460873	2404	0	0
T21	625203	28	0	0
T22	0	59	0	0
T23	0	21	0	0
T32	359492	91	0	0
T39	18608	0	0	0
T59	14299	0	0	0
T158	0	126	0	0
T160	0	43	0	0
T220	12995	0	0	0
T280	61497	0	0	0
T281	231246	107	0	0
T310	0	153	0	0
T389	0	58	0	0
T390	0	84	0	0
T391	127167	0	0	0
T392	45945	0	0	0
T393	14489	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445460873	1591	0	0
T21	625203	3	0	0
T22	0	10	0	0
T23	0	6	0	0
T32	359492	33	0	0
T39	18608	0	0	0
T59	14299	0	0	0
T158	0	123	0	0
T160	0	6	0	0
T220	12995	0	0	0
T280	61497	0	0	0
T281	231246	57	0	0
T310	0	140	0	0
T389	0	55	0	0
T390	0	37	0	0
T391	127167	0	0	0
T392	45945	0	0	0
T393	14489	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445460873	1833	0	0
T21	625203	9	0	0
T22	0	58	0	0
T23	0	9	0	0
T32	359492	57	0	0
T39	18608	0	0	0
T59	14299	0	0	0
T158	0	66	0	0
T160	0	22	0	0
T220	12995	0	0	0
T280	61497	0	0	0
T281	231246	26	0	0
T310	0	160	0	0
T389	0	34	0	0
T390	0	36	0	0
T391	127167	0	0	0
T392	45945	0	0	0
T393	14489	0	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445460873	3679	0	0
T21	625203	19	0	0
T22	0	37	0	0
T23	0	16	0	0
T32	359492	65	0	0
T39	18608	0	0	0
T59	14299	0	0	0
T158	0	157	0	0
T160	0	46	0	0
T220	12995	0	0	0
T280	61497	0	0	0
T281	231246	63	0	0
T310	0	155	0	0
T389	0	61	0	0
T390	0	31	0	0
T391	127167	0	0	0
T392	45945	0	0	0
T393	14489	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445460873	4550	0	0
T21	0	55	0	0
T22	0	91	0	0
T23	0	8	0	0
T32	0	97	0	0
T52	14428	0	0	0
T71	39755	0	0	0
T91	51202	0	0	0
T100	114043	86	0	0
T101	201586	0	0	0
T111	36368	0	0	0
T158	0	115	0	0
T160	0	16	0	0
T219	15337	0	0	0
T231	32317	0	0	0
T281	0	79	0	0
T304	24354	0	0	0
T305	23879	0	0	0
T389	0	47	0	0
T390	0	75	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445460873	3302	0	0
T21	625203	32	0	0
T22	0	53	0	0
T23	0	22	0	0
T32	359492	83	0	0
T39	18608	0	0	0
T59	14299	0	0	0
T158	0	130	0	0
T160	0	34	0	0
T220	12995	0	0	0
T280	61497	0	0	0
T281	231246	59	0	0
T310	0	155	0	0
T389	0	31	0	0
T390	0	54	0	0
T391	127167	0	0	0
T392	45945	0	0	0
T393	14489	0	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445460873	3524	0	0
T21	625203	29	0	0
T22	0	44	0	0
T23	0	17	0	0
T32	359492	77	0	0
T39	18608	0	0	0
T59	14299	0	0	0
T158	0	142	0	0
T160	0	54	0	0
T220	12995	0	0	0
T280	61497	0	0	0
T281	231246	53	0	0
T310	0	160	0	0
T389	0	54	0	0
T390	0	35	0	0
T391	127167	0	0	0
T392	45945	0	0	0
T393	14489	0	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445460873	3339	0	0
T21	625203	28	0	0
T22	0	34	0	0
T23	0	38	0	0
T32	359492	114	0	0
T39	18608	0	0	0
T59	14299	0	0	0
T158	0	128	0	0
T160	0	61	0	0
T220	12995	0	0	0
T280	61497	0	0	0
T281	231246	48	0	0
T310	0	91	0	0
T389	0	80	0	0
T390	0	63	0	0
T391	127167	0	0	0
T392	45945	0	0	0
T393	14489	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445460873	3166	0	0
T21	625203	22	0	0
T22	0	28	0	0
T23	0	15	0	0
T32	359492	68	0	0
T39	18608	0	0	0
T59	14299	0	0	0
T158	0	127	0	0
T160	0	17	0	0
T220	12995	0	0	0
T280	61497	0	0	0
T281	231246	40	0	0
T310	0	118	0	0
T389	0	53	0	0
T390	0	66	0	0
T391	127167	0	0	0
T392	45945	0	0	0
T393	14489	0	0	0