Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : otp_ctrl
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.51 92.95 86.96 87.35 93.10 97.18

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 96.20 94.16 96.15 97.08 96.43 97.18



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.20 94.16 96.15 97.08 96.43 97.18


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.29 93.76 96.65 96.21 91.65 97.15 96.34


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
core_tlul_assert_device 100.00 100.00 100.00 100.00
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
gen_alert_tx[1].u_prim_alert_sender 100.00 100.00
gen_alert_tx[2].u_prim_alert_sender 100.00 100.00
gen_alert_tx[3].u_prim_alert_sender 100.00 100.00
gen_alert_tx[4].u_prim_alert_sender 100.00 100.00
gen_bufs[0].u_prim_mubi8_sender_read_lock 100.00 100.00 100.00 100.00
gen_bufs[0].u_prim_mubi8_sender_write_lock 79.17 37.50 100.00 100.00
gen_bufs[10].u_prim_mubi8_sender_read_lock 79.17 37.50 100.00 100.00
gen_bufs[10].u_prim_mubi8_sender_write_lock 79.17 37.50 100.00 100.00
gen_bufs[1].u_prim_mubi8_sender_read_lock 100.00 100.00 100.00 100.00
gen_bufs[1].u_prim_mubi8_sender_write_lock 79.17 37.50 100.00 100.00
gen_bufs[2].u_prim_mubi8_sender_read_lock 100.00 100.00 100.00 100.00
gen_bufs[2].u_prim_mubi8_sender_write_lock 79.17 37.50 100.00 100.00
gen_bufs[3].u_prim_mubi8_sender_read_lock 100.00 100.00 100.00 100.00
gen_bufs[3].u_prim_mubi8_sender_write_lock 79.17 37.50 100.00 100.00
gen_bufs[4].u_prim_mubi8_sender_read_lock 100.00 100.00 100.00 100.00
gen_bufs[4].u_prim_mubi8_sender_write_lock 79.17 37.50 100.00 100.00
gen_bufs[5].u_prim_mubi8_sender_read_lock 79.17 37.50 100.00 100.00
gen_bufs[5].u_prim_mubi8_sender_write_lock 79.17 37.50 100.00 100.00
gen_bufs[6].u_prim_mubi8_sender_read_lock 79.17 37.50 100.00 100.00
gen_bufs[6].u_prim_mubi8_sender_write_lock 79.17 37.50 100.00 100.00
gen_bufs[7].u_prim_mubi8_sender_read_lock 79.17 37.50 100.00 100.00
gen_bufs[7].u_prim_mubi8_sender_write_lock 79.17 37.50 100.00 100.00
gen_bufs[8].u_prim_mubi8_sender_read_lock 79.17 37.50 100.00 100.00
gen_bufs[8].u_prim_mubi8_sender_write_lock 79.17 37.50 100.00 100.00
gen_bufs[9].u_prim_mubi8_sender_read_lock 100.00 100.00 100.00 100.00
gen_bufs[9].u_prim_mubi8_sender_write_lock 100.00 100.00 100.00 100.00
gen_partitions[0].gen_unbuffered.u_part_unbuf 97.56 100.00 100.00 100.00 90.00 98.15 97.22
gen_partitions[10].gen_lifecycle.u_part_buf 91.58 90.44 100.00 77.75 95.24 100.00 86.05
gen_partitions[1].gen_unbuffered.u_part_unbuf 98.32 100.00 100.00 100.00 91.67 98.25 100.00
gen_partitions[2].gen_unbuffered.u_part_unbuf 97.83 100.00 97.06 100.00 91.67 98.25 100.00
gen_partitions[3].gen_unbuffered.u_part_unbuf 98.32 100.00 100.00 100.00 91.67 98.25 100.00
gen_partitions[4].gen_unbuffered.u_part_unbuf 98.32 100.00 100.00 100.00 91.67 98.25 100.00
gen_partitions[5].gen_buffered.u_part_buf 94.87 98.28 95.24 100.00 92.00 97.06 86.67
gen_partitions[6].gen_buffered.u_part_buf 93.40 96.65 92.86 100.00 91.67 92.54 86.67
gen_partitions[7].gen_buffered.u_part_buf 96.45 98.54 93.75 100.00 94.44 96.25 95.74
gen_partitions[8].gen_buffered.u_part_buf 96.45 98.54 93.75 100.00 94.44 96.25 95.74
gen_partitions[9].gen_buffered.u_part_buf 94.73 97.07 91.67 100.00 88.89 95.00 95.74
otp_ctrl_core_csr_assert 100.00 100.00
prim_tlul_assert_device 100.00 100.00 100.00 100.00
u_edn_arb 93.86 92.31 89.80 100.00 93.33
u_intr_error 100.00 100.00 100.00 100.00 100.00
u_intr_operation_done 100.00 100.00 100.00 100.00 100.00
u_keygmr_key_valid 100.00 100.00 100.00
u_otp 98.91 93.68 99.80 100.00 100.00 100.00 100.00
u_otp_arb 97.29 98.07 97.35 100.00 93.75
u_otp_ctrl_dai 89.97 85.64 91.96 100.00 85.96 89.04 87.23
u_otp_ctrl_kdi 96.45 99.63 99.64 100.00 86.36 95.70 97.37
u_otp_ctrl_lci 100.00 100.00 100.00 100.00 100.00 100.00 100.00
u_otp_ctrl_lfsr_timer 97.49 100.00 97.47 87.50 100.00 100.00 100.00
u_otp_ctrl_scrmbl 96.92 81.50 100.00 100.00 100.00 100.00 100.00
u_otp_init_sync 100.00 100.00 100.00
u_otp_rsp_fifo 96.83 100.00 92.31 95.00 100.00
u_part_sel_idx 74.55 65.65 89.83 88.89 53.85
u_prim_edn_req 92.19 100.00 93.75 100.00 75.00
u_prim_lc_sender_otp_broadcast_valid 100.00 100.00 100.00
u_prim_lc_sender_rma_token_valid 100.00 100.00 100.00
u_prim_lc_sender_secrets_valid 100.00 100.00 100.00
u_prim_lc_sender_test_tokens_valid 100.00 100.00 100.00
u_prim_lc_sync_check_byp_en 100.00 100.00 100.00 100.00
u_prim_lc_sync_creator_seed_sw_rw_en 100.00 100.00 100.00 100.00
u_prim_lc_sync_dft_en 100.00 100.00 100.00 100.00
u_prim_lc_sync_escalate_en 100.00 100.00 100.00 100.00
u_prim_lc_sync_owner_seed_sw_rw_en 100.00 100.00 100.00 100.00
u_prim_lc_sync_seed_hw_rd_en 100.00 100.00 100.00 100.00
u_reg_core 99.17 99.65 96.20 100.00 100.00 100.00
u_scrmbl_mtx 79.48 75.00 99.17 100.00 43.75
u_tlul_adapter_sram 93.06 89.80 92.65 89.77 100.00
u_tlul_lc_gate 92.41 99.21 92.86 85.71 96.77 87.50

Line Coverage for Module : otp_ctrl
Line No.TotalCoveredPercent
TOTAL15614592.95
CONT_ASSIGN25111100.00
CONT_ASSIGN25311100.00
CONT_ASSIGN25311100.00
CONT_ASSIGN25311100.00
CONT_ASSIGN25311100.00
CONT_ASSIGN25311100.00
CONT_ASSIGN25311100.00
CONT_ASSIGN25311100.00
CONT_ASSIGN25311100.00
CONT_ASSIGN25311100.00
CONT_ASSIGN25311100.00
ALWAYS284141392.86
ALWAYS30833100.00
ALWAYS324111090.91
CONT_ASSIGN38211100.00
CONT_ASSIGN38611100.00
CONT_ASSIGN39011100.00
CONT_ASSIGN39411100.00
CONT_ASSIGN39511100.00
CONT_ASSIGN40311100.00
CONT_ASSIGN40411100.00
ALWAYS40755100.00
ALWAYS4341919100.00
CONT_ASSIGN48811100.00
CONT_ASSIGN49611100.00
ALWAYS49999100.00
ALWAYS5211010100.00
CONT_ASSIGN58511100.00
CONT_ASSIGN59311100.00
CONT_ASSIGN64011100.00
CONT_ASSIGN64211100.00
CONT_ASSIGN76511100.00
CONT_ASSIGN76611100.00
CONT_ASSIGN76711100.00
CONT_ASSIGN79711100.00
CONT_ASSIGN79911100.00
ALWAYS87622100.00
ALWAYS93422100.00
ALWAYS96144100.00
CONT_ASSIGN98811100.00
ALWAYS99133100.00
CONT_ASSIGN104311100.00
CONT_ASSIGN104511100.00
CONT_ASSIGN1079100.00
CONT_ASSIGN1130100.00
CONT_ASSIGN118511100.00
CONT_ASSIGN118511100.00
CONT_ASSIGN118511100.00
CONT_ASSIGN118511100.00
CONT_ASSIGN118511100.00
CONT_ASSIGN1240100.00
CONT_ASSIGN1240100.00
CONT_ASSIGN1240100.00
CONT_ASSIGN1240100.00
CONT_ASSIGN1240100.00
CONT_ASSIGN1300100.00
CONT_ASSIGN1312100.00
CONT_ASSIGN133611100.00
ALWAYS134822100.00
CONT_ASSIGN136211100.00
ALWAYS139099100.00
CONT_ASSIGN142111100.00
CONT_ASSIGN142211100.00
CONT_ASSIGN142411100.00
CONT_ASSIGN142611100.00
CONT_ASSIGN143011100.00
CONT_ASSIGN143211100.00
CONT_ASSIGN143411100.00
CONT_ASSIGN143911100.00
CONT_ASSIGN144111100.00
CONT_ASSIGN144311100.00
CONT_ASSIGN147511100.00
CONT_ASSIGN147711100.00
CONT_ASSIGN148111100.00
CONT_ASSIGN148511100.00
CONT_ASSIGN148911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
251 1 1
253 10 10
284 1 1
285 1 1
286 1 1
287 1 1
288 1 1
289 1 1
292 0 1
MISSING_ELSE
297 1 1
298 1 1
299 1 1
300 1 1
301 1 1
302 1 1
303 1 1
308 1 1
309 1 1
311 1 1
324 1 1
329 1 1
330 1 1
334 1 1
335 1 1
336 1 1
337 1 1
MISSING_ELSE
MISSING_ELSE
341 1 1
342 1 1
343 1 1
344 0 1
MISSING_ELSE
MISSING_ELSE
382 1 1
386 1 1
390 1 1
394 1 1
395 1 1
403 1 1
404 1 1
407 1 1
408 1 1
410 1 1
412 1 1
413 1 1
434 1 1
435 1 1
436 1 1
438 1 1
440 1 1
443 1 1
445 1 1
448 1 1
449 1 1
MISSING_ELSE
453 1 1
455 1 1
459 1 1
462 1 1
464 1 1
469 1 1
470 1 1
MISSING_ELSE
472 1 1
473 1 1
MISSING_ELSE
478 1 1
488 1 1
496 1 1
499 1 1
500 1 1
501 1 1
502 1 1
503 1 1
505 1 1
506 1 1
507 1 1
508 1 1
521 1 1
523 1 1
525 1 1
527 1 1
529 1 1
538 1 1
540 1 1
541 1 1
542 1 1
543 1 1
585 1 1
593 1 1
640 1 1
642 1 1
765 1 1
766 1 1
767 1 1
797 1 1
799 1 1
876 1 1
877 1 1
934 1 1
935 1 1
961 1 1
962 1 1
963 1 1
964 1 1
988 1 1
991 1 1
992 1 1
994 1 1
1043 1 1
1045 1 1
1079 0 1
1130 0 1
1185 5 5
1240 0 5
1300 0 1
1312 0 1
1336 1 1
1348 1 1
1349 1 1
1362 1 1
1390 1 1
1391 1 1
1392 1 1
1393 1 1
1395 1 1
1396 1 1
1397 1 1
1398 1 1
1399 1 1
1421 1 1
1422 1 1
1424 1 1
1426 1 1
1430 1 1
1432 1 1
1434 1 1
1439 1 1
1441 1 1
1443 1 1
1475 1 1
1477 1 1
1481 1 1
1485 1 1
1489 1 1


Cond Coverage for Module : otp_ctrl
TotalCoveredPercent
Conditions11510086.96
Logical11510086.96
Non-Logical00
Event00

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b00001000000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[1].PartEnd))
             -------------------1------------------   --------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b00111011000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[2].PartEnd))
             -------------------1------------------   --------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b10001111000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[3].PartEnd))
             -------------------1------------------   --------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11001010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[4].PartEnd))
             -------------------1------------------   --------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT7,T15,T16
11CoveredT1,T2,T3

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11001111000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[5].PartEnd))
             -------------------1------------------   --------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT7,T15,T16
11CoveredT7,T15,T16

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011000000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[6].PartEnd))
             -------------------1------------------   --------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT7,T15,T16
11CoveredT7,T15,T16

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[7].PartEnd))
             -------------------1------------------   --------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT7,T15,T16
11CoveredT7,T15,T16

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011111000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[8].PartEnd))
             -------------------1------------------   --------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT7,T15,T16
11CoveredT7,T15,T16

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11101010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[9].PartEnd))
             -------------------1------------------   --------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT7,T15,T16
11CoveredT7,T15,T16

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11110101000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[10].PartEnd))
             -------------------1------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT7,T15,T16

 LINE       288
 EXPRESSION (tlul_part_sel_oh != '0)
            ------------1-----------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       297
 EXPRESSION (((|part_tlul_gnt)) | tlul_oob_err_q)
             ---------1--------   -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T2,T3

 LINE       298
 EXPRESSION (((|part_tlul_rvalid)) | tlul_oob_err_q)
             ----------1----------   -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T2,T3

 LINE       382
 EXPRESSION ((reg2hw.direct_access_regwen.qe && ((!reg2hw.direct_access_regwen.q))) ? 1'b0 : direct_access_regwen_q)
             -----------------------------------1----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       382
 SUB-EXPRESSION (reg2hw.direct_access_regwen.qe && ((!reg2hw.direct_access_regwen.q)))
                 ---------------1--------------    -----------------2----------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       386
 EXPRESSION (reg2hw.direct_access_cmd.digest.qe | reg2hw.direct_access_cmd.wr.qe | reg2hw.direct_access_cmd.rd.qe)
             -----------------1----------------   ---------------2--------------   ---------------3--------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010Not Covered
100Not Covered

 LINE       403
 EXPRESSION (lci_prog_idle & dai_prog_idle)
             ------1------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       436
 EXPRESSION (fatal_bus_integ_error_q | ((|intg_error)))
             -----------1-----------   -------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT26,T27,T28
10Not Covered

 LINE       445
 EXPRESSION (part_error[k] == MacroError)
            --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       449
 EXPRESSION (part_error[k] == MacroEccUncorrError)
            -------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T13,T118

 LINE       469
 EXPRESSION (fatal_macro_error_q || fatal_check_error_q)
             ---------1---------    ---------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T9,T12
10CoveredT3,T13,T118

 LINE       478
 EXPRESSION (chk_timeout | lfsr_fsm_err | scrmbl_fsm_err | ((|part_fsm_err)))
             -----1-----   ------2-----   -------3------   --------4--------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001CoveredT2,T3,T9
0010CoveredT26,T27,T28
0100CoveredT26,T27,T28
1000CoveredT15,T41,T74

 LINE       527
 EXPRESSION (direct_access_regwen_q & dai_idle)
             -----------1----------   ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       593
 SUB-EXPRESSION (reg2hw.alert_test.recov_prim_otp_alert.q & reg2hw.alert_test.recov_prim_otp_alert.qe)
                 --------------------1-------------------   --------------------2--------------------
-1--2-StatusTests
01CoveredT10,T11,T14
10CoveredT1,T2,T3
11CoveredT10,T11,T14

 LINE       593
 SUB-EXPRESSION (reg2hw.alert_test.fatal_prim_otp_alert.q & reg2hw.alert_test.fatal_prim_otp_alert.qe)
                 --------------------1-------------------   --------------------2--------------------
-1--2-StatusTests
01CoveredT10,T11,T14
10CoveredT1,T2,T3
11CoveredT10,T11,T14

 LINE       593
 SUB-EXPRESSION (reg2hw.alert_test.fatal_bus_integ_error.q & reg2hw.alert_test.fatal_bus_integ_error.qe)
                 --------------------1--------------------   ---------------------2--------------------
-1--2-StatusTests
01CoveredT10,T11,T14
10CoveredT1,T2,T3
11CoveredT10,T11,T14

 LINE       593
 SUB-EXPRESSION (reg2hw.alert_test.fatal_check_error.q & reg2hw.alert_test.fatal_check_error.qe)
                 ------------------1------------------   -------------------2------------------
-1--2-StatusTests
01CoveredT10,T11,T14
10CoveredT1,T2,T3
11CoveredT10,T11,T14

 LINE       593
 SUB-EXPRESSION (reg2hw.alert_test.fatal_macro_error.q & reg2hw.alert_test.fatal_macro_error.qe)
                 ------------------1------------------   -------------------2------------------
-1--2-StatusTests
01CoveredT10,T11,T14
10CoveredT1,T2,T3
11CoveredT10,T11,T14

 LINE       640
 EXPRESSION (reg2hw.check_trigger.integrity.q & reg2hw.check_trigger.integrity.qe)
             ----------------1---------------   ----------------2----------------
-1--2-StatusTests
01CoveredT1,T18,T45
10CoveredT1,T2,T3
11CoveredT4,T18,T19

 LINE       642
 EXPRESSION (reg2hw.check_trigger.consistency.q & reg2hw.check_trigger.consistency.qe)
             -----------------1----------------   -----------------2-----------------
-1--2-StatusTests
01CoveredT4,T18,T45
10CoveredT1,T2,T3
11CoveredT1,T4,T18

 LINE       765
 EXPRESSION (otp_prim_ready & otp_rsp_fifo_ready)
             -------1------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       766
 EXPRESSION (otp_arb_valid & otp_rsp_fifo_ready)
             ------1------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       767
 EXPRESSION (otp_prim_ready & otp_prim_valid)
             -------1------   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       877
 EXPRESSION (otp_rvalid & otp_fifo_valid)
             -----1----   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       1421
 EXPRESSION (part_digest[Secret1Idx] != '0)
            ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T9,T4

 LINE       1439
 EXPRESSION ((part_digest[Secret0Idx] != '0) ? On : Off)
             ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T4,T5

 LINE       1439
 SUB-EXPRESSION (part_digest[Secret0Idx] != '0)
                ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T4,T5

 LINE       1441
 EXPRESSION ((part_digest[Secret2Idx] != '0) ? On : Off)
             ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T4,T18

 LINE       1441
 SUB-EXPRESSION (part_digest[Secret2Idx] != '0)
                ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T4,T18

 LINE       1443
 EXPRESSION ((part_digest[Secret2Idx] != '0) ? On : Off)
             ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T4,T18

 LINE       1443
 SUB-EXPRESSION (part_digest[Secret2Idx] != '0)
                ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T4,T18

Toggle Coverage for Module : otp_ctrl
TotalCoveredPercent
Totals 156 142 91.03
Total Bits 11096 9692 87.35
Total Bits 0->1 5548 4846 87.35
Total Bits 1->0 5548 4846 87.35

Ports 156 142 91.03
Port Bits 11096 9692 87.35
Port Bits 0->1 5548 4846 87.35
Port Bits 1->0 5548 4846 87.35

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_edn_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_edn_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_o.edn_req Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
edn_i.edn_bus[31:0] Yes Yes T1,T4,T5 Yes T1,T4,T5 INPUT
edn_i.edn_fips Yes Yes T1,T4,T5 Yes T1,T4,T5 INPUT
edn_i.edn_ack Yes Yes T1,T4,T5 Yes T1,T4,T5 INPUT
core_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_user.instr_type[3:0] Yes Yes T3,T10,T5 Yes T3,T10,T5 INPUT
core_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
core_tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_address[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_source[7:0] Yes Yes T1,T3,T10 Yes T1,T2,T3 INPUT
core_tl_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
core_tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
core_tl_o.d_error Yes Yes T1,T18,T19 Yes T1,T18,T19 OUTPUT
core_tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
core_tl_o.d_user.rsp_intg[5:0] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
core_tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
core_tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
core_tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
core_tl_o.d_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
core_tl_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
core_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
core_tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
core_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
core_tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
prim_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
prim_tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
prim_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
prim_tl_i.a_user.instr_type[3:0] Yes Yes T2,T3,T13 Yes T2,T13,T123 INPUT
prim_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
prim_tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
prim_tl_i.a_mask[3:0] Yes Yes T2,T3,T13 Yes T2,T3,T13 INPUT
prim_tl_i.a_address[31:0] Yes Yes T2,T3,T123 Yes T2,T3,T13 INPUT
prim_tl_i.a_source[7:0] Yes Yes T2,T3,T4 Yes T3,T4,T13 INPUT
prim_tl_i.a_size[1:0] Yes Yes T2,T3,T13 Yes T2,T3,T13 INPUT
prim_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
prim_tl_i.a_opcode[2:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
prim_tl_i.a_valid Yes Yes T1,T4,T5 Yes T1,T4,T5 INPUT
prim_tl_o.a_ready Yes Yes T1,T10,T11 Yes T1,T10,T11 OUTPUT
prim_tl_o.d_error Yes Yes T1,T10,T11 Yes T1,T19,T7 OUTPUT
prim_tl_o.d_user.data_intg[6:0] Yes Yes T1,T19,T55 Yes T1,T19,T55 OUTPUT
prim_tl_o.d_user.rsp_intg[5:0] Yes Yes *T1,*T4,*T5 Yes T1,T4,T5 OUTPUT
prim_tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
prim_tl_o.d_data[31:0] Yes Yes T1,T10,T11 Yes T1,T19,T7 OUTPUT
prim_tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
prim_tl_o.d_source[7:0] Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
prim_tl_o.d_size[1:0] Yes Yes T7,T15,T16 Yes T7,T15,T16 OUTPUT
prim_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
prim_tl_o.d_opcode[0] Yes Yes *T1,*T10,*T11 Yes T1,T4,T5 OUTPUT
prim_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
prim_tl_o.d_valid Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
intr_otp_operation_done_o Yes Yes T1,T3,T9 Yes T1,T3,T9 OUTPUT
intr_otp_error_o Yes Yes T1,T3,T9 Yes T1,T3,T9 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T3,T10,T11 Yes T3,T10,T11 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T2,T3,T10 Yes T2,T3,T10 INPUT
alert_rx_i[1].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[2].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[2].ack_p Yes Yes T10,T11,T14 Yes T10,T11,T14 INPUT
alert_rx_i[2].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[2].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[3].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[3].ack_p Yes Yes T10,T11,T14 Yes T10,T11,T14 INPUT
alert_rx_i[3].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[3].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[4].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[4].ack_p Yes Yes T10,T11,T14 Yes T10,T11,T14 INPUT
alert_rx_i[4].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[4].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T3,T10,T11 Yes T3,T10,T11 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T2,T3,T10 Yes T2,T3,T10 OUTPUT
alert_tx_o[2].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[2].alert_p Yes Yes T10,T11,T14 Yes T10,T11,T14 OUTPUT
alert_tx_o[3].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[3].alert_p Yes Yes T10,T11,T14 Yes T10,T11,T14 OUTPUT
alert_tx_o[4].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[4].alert_p Yes Yes T10,T11,T14 Yes T10,T11,T14 OUTPUT
obs_ctrl_i.obmen[3:0] No No No INPUT
obs_ctrl_i.obmsl[3:0] No No No INPUT
obs_ctrl_i.obgsl[3:0] No No No INPUT
otp_obs_o[7:0] Unreachable Unreachable Unreachable OUTPUT
otp_ast_pwr_seq_o.pwr_seq[1:0] No No No OUTPUT
otp_ast_pwr_seq_h_i.pwr_seq_h[1:0] Yes Yes T3,T4,T18 Yes T4,T13,T18 INPUT
pwr_otp_i.otp_init Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
pwr_otp_o.otp_idle Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
pwr_otp_o.otp_done Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
lc_otp_vendor_test_i.ctrl[31:0] No No No INPUT
lc_otp_vendor_test_o.status[31:0] No No No OUTPUT
lc_otp_program_i.count[383:0] Yes Yes T7,T15,T41 Yes T7,T15,T16 INPUT
lc_otp_program_i.state[319:0] Yes Yes T15,T41,T100 Yes T15,T41,T100 INPUT
lc_otp_program_i.req Yes Yes T1,T4,T5 Yes T1,T4,T5 INPUT
lc_otp_program_o.ack Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
lc_otp_program_o.err Yes Yes T15,T100,T257 Yes T15,T100,T257 OUTPUT
lc_creator_seed_sw_rw_en_i[3:0] Yes Yes T1,T5,T18 Yes T1,T5,T18 INPUT
lc_owner_seed_sw_rw_en_i[3:0] Yes Yes T1,T5,T18 Yes T1,T5,T18 INPUT
lc_seed_hw_rd_en_i[3:0] Yes Yes T1,T9,T4 Yes T1,T2,T3 INPUT
lc_dft_en_i[3:0] Yes Yes T1,T118,T19 Yes T1,T2,T10 INPUT
lc_escalate_en_i[3:0] Yes Yes T114,T7,T115 Yes T114,T7,T115 INPUT
lc_check_byp_en_i[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
otp_lc_data_o.rma_token[127:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.rma_token_valid[3:0] Yes Yes T9,T18,T45 Yes T9,T4,T18 OUTPUT
otp_lc_data_o.test_exit_token[127:0] Yes Yes T18,T19,T48 Yes T18,T19,T48 OUTPUT
otp_lc_data_o.test_unlock_token[127:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.test_tokens_valid[3:0] Yes Yes T9,T4,T5 Yes T9,T4,T5 OUTPUT
otp_lc_data_o.secrets_valid[3:0] Yes Yes T9,T18,T45 Yes T9,T4,T18 OUTPUT
otp_lc_data_o.count[0] No No No OUTPUT
otp_lc_data_o.count[3:1] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[4] No No No OUTPUT
otp_lc_data_o.count[8:5] Yes Yes T1,T4,*T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.count[9] No No No OUTPUT
otp_lc_data_o.count[10] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[11] No No No OUTPUT
otp_lc_data_o.count[27:12] Yes Yes T1,*T4,*T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.count[28] No No No OUTPUT
otp_lc_data_o.count[29] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[32:30] No No No OUTPUT
otp_lc_data_o.count[54:33] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[55] No No No OUTPUT
otp_lc_data_o.count[64:56] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[65] No No No OUTPUT
otp_lc_data_o.count[101:66] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[102] No No No OUTPUT
otp_lc_data_o.count[105:103] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[106] No No No OUTPUT
otp_lc_data_o.count[118:107] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[119] No No No OUTPUT
otp_lc_data_o.count[124:120] Yes Yes T1,*T4,*T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.count[125] No No No OUTPUT
otp_lc_data_o.count[134:126] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[135] No No No OUTPUT
otp_lc_data_o.count[137:136] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[138] No No No OUTPUT
otp_lc_data_o.count[142:139] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[143] No No No OUTPUT
otp_lc_data_o.count[147:144] Yes Yes T1,T4,*T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.count[148] No No No OUTPUT
otp_lc_data_o.count[164:149] Yes Yes T1,*T4,*T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.count[165] No No No OUTPUT
otp_lc_data_o.count[171:166] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[172] No No No OUTPUT
otp_lc_data_o.count[174:173] Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.count[175] No No No OUTPUT
otp_lc_data_o.count[188:176] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[189] No No No OUTPUT
otp_lc_data_o.count[191:190] Yes Yes *T5,*T18,*T45 Yes T1,T5,T18 OUTPUT
otp_lc_data_o.count[192] No No No OUTPUT
otp_lc_data_o.count[196:193] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[197] No No No OUTPUT
otp_lc_data_o.count[198] Yes Yes *T1,*T4,*T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.count[199] No No No OUTPUT
otp_lc_data_o.count[202:200] Yes Yes *T5,*T18,*T45 Yes T1,T5,T18 OUTPUT
otp_lc_data_o.count[203] No No No OUTPUT
otp_lc_data_o.count[206:204] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[208:207] No No No OUTPUT
otp_lc_data_o.count[217:209] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[218] No No No OUTPUT
otp_lc_data_o.count[225:219] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[226] No No No OUTPUT
otp_lc_data_o.count[237:227] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[238] No No No OUTPUT
otp_lc_data_o.count[240:239] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[241] No No No OUTPUT
otp_lc_data_o.count[243:242] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[244] No No No OUTPUT
otp_lc_data_o.count[266:245] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[267] No No No OUTPUT
otp_lc_data_o.count[269:268] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[270] No No No OUTPUT
otp_lc_data_o.count[272:271] Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.count[273] No No No OUTPUT
otp_lc_data_o.count[284:274] Yes Yes *T5,*T18,*T45 Yes T1,T5,T18 OUTPUT
otp_lc_data_o.count[286:285] No No No OUTPUT
otp_lc_data_o.count[303:287] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[304] No No No OUTPUT
otp_lc_data_o.count[309:305] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[310] No No No OUTPUT
otp_lc_data_o.count[312:311] Yes Yes T1,T4,*T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.count[313] No No No OUTPUT
otp_lc_data_o.count[324:314] Yes Yes T1,T4,*T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.count[325] No No No OUTPUT
otp_lc_data_o.count[330:326] Yes Yes T1,T4,*T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.count[331] No No No OUTPUT
otp_lc_data_o.count[335:332] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[336] No No No OUTPUT
otp_lc_data_o.count[343:337] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[344] No No No OUTPUT
otp_lc_data_o.count[345] Yes Yes *T1,*T4,*T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.count[346] No No No OUTPUT
otp_lc_data_o.count[364:347] Yes Yes T1,T4,*T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.count[365] No No No OUTPUT
otp_lc_data_o.count[366] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[367] No No No OUTPUT
otp_lc_data_o.count[371:368] Yes Yes T1,T4,*T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.count[372] No No No OUTPUT
otp_lc_data_o.count[375:373] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[376] No No No OUTPUT
otp_lc_data_o.count[383:377] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[9:0] Yes Yes T1,T4,*T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.state[10] No No No OUTPUT
otp_lc_data_o.state[14:11] Yes Yes T1,T4,*T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.state[15] No No No OUTPUT
otp_lc_data_o.state[17:16] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[18] No No No OUTPUT
otp_lc_data_o.state[34:19] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[35] No No No OUTPUT
otp_lc_data_o.state[36] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[37] No No No OUTPUT
otp_lc_data_o.state[42:38] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[43] No No No OUTPUT
otp_lc_data_o.state[46:44] Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.state[48:47] No No No OUTPUT
otp_lc_data_o.state[51:49] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[52] No No No OUTPUT
otp_lc_data_o.state[68:53] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[69] No No No OUTPUT
otp_lc_data_o.state[75:70] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[76] No No No OUTPUT
otp_lc_data_o.state[79:77] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[80] No No No OUTPUT
otp_lc_data_o.state[84:81] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[85] No No No OUTPUT
otp_lc_data_o.state[98:86] Yes Yes T1,T4,*T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.state[99] No No No OUTPUT
otp_lc_data_o.state[101:100] Yes Yes T1,T4,*T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.state[102] No No No OUTPUT
otp_lc_data_o.state[103] Yes Yes *T1,*T4,*T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.state[104] No No No OUTPUT
otp_lc_data_o.state[105] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[107:106] No No No OUTPUT
otp_lc_data_o.state[110:108] Yes Yes T1,T4,*T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.state[111] No No No OUTPUT
otp_lc_data_o.state[126:112] Yes Yes T1,T4,*T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.state[127] No No No OUTPUT
otp_lc_data_o.state[136:128] Yes Yes T1,T4,*T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.state[137] No No No OUTPUT
otp_lc_data_o.state[141:138] Yes Yes T1,T4,*T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.state[142] No No No OUTPUT
otp_lc_data_o.state[145:143] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[146] No No No OUTPUT
otp_lc_data_o.state[151:147] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[152] No No No OUTPUT
otp_lc_data_o.state[153] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[154] No No No OUTPUT
otp_lc_data_o.state[160:155] Yes Yes T1,T4,*T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.state[161] No No No OUTPUT
otp_lc_data_o.state[163:162] Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.state[164] No No No OUTPUT
otp_lc_data_o.state[177:165] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[178] No No No OUTPUT
otp_lc_data_o.state[180:179] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[181] No No No OUTPUT
otp_lc_data_o.state[182] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[184:183] No No No OUTPUT
otp_lc_data_o.state[191:185] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[192] No No No OUTPUT
otp_lc_data_o.state[198:193] Yes Yes T1,T4,*T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.state[199] No No No OUTPUT
otp_lc_data_o.state[210:200] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[211] No No No OUTPUT
otp_lc_data_o.state[214:212] Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.state[215] No No No OUTPUT
otp_lc_data_o.state[217:216] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[218] No No No OUTPUT
otp_lc_data_o.state[219] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[220] No No No OUTPUT
otp_lc_data_o.state[226:221] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[227] No No No OUTPUT
otp_lc_data_o.state[230:228] Yes Yes T1,T5,T18 Yes T1,T5,T18 OUTPUT
otp_lc_data_o.state[231] No No No OUTPUT
otp_lc_data_o.state[234:232] Yes Yes T1,*T5,*T18 Yes T1,T5,T18 OUTPUT
otp_lc_data_o.state[235] No No No OUTPUT
otp_lc_data_o.state[236] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[237] No No No OUTPUT
otp_lc_data_o.state[239:238] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[240] No No No OUTPUT
otp_lc_data_o.state[241] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[242] No No No OUTPUT
otp_lc_data_o.state[250:243] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[251] No No No OUTPUT
otp_lc_data_o.state[263:252] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[264] No No No OUTPUT
otp_lc_data_o.state[277:265] Yes Yes *T1,*T4,*T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.state[278] No No No OUTPUT
otp_lc_data_o.state[284:279] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[285] No No No OUTPUT
otp_lc_data_o.state[301:286] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[302] No No No OUTPUT
otp_lc_data_o.state[307:303] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[308] No No No OUTPUT
otp_lc_data_o.state[311:309] Yes Yes *T5,*T19,*T48 Yes T5,T19,T48 OUTPUT
otp_lc_data_o.state[312] No No No OUTPUT
otp_lc_data_o.state[316:313] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[317] No No No OUTPUT
otp_lc_data_o.state[319:318] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.error Yes Yes T2,T3,T9 Yes T2,T3,T9 OUTPUT
otp_lc_data_o.valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_keymgr_key_o.owner_seed_valid No No No OUTPUT
otp_keymgr_key_o.owner_seed[255:0] No No No OUTPUT
otp_keymgr_key_o.creator_seed_valid No No No OUTPUT
otp_keymgr_key_o.creator_seed[255:0] No No No OUTPUT
otp_keymgr_key_o.creator_root_key_share1_valid Yes Yes T9,T18,T45 Yes T9,T4,T18 OUTPUT
otp_keymgr_key_o.creator_root_key_share1[255:0] Yes Yes T1,T9,T4 Yes T1,T11,T9 OUTPUT
otp_keymgr_key_o.creator_root_key_share0_valid Yes Yes T9,T18,T45 Yes T9,T4,T18 OUTPUT
otp_keymgr_key_o.creator_root_key_share0[255:0] Yes Yes T4,T117,T41 Yes T41,T74,T146 OUTPUT
flash_otp_key_i.addr_req Yes Yes T1,T4,T5 Yes T1,T4,T5 INPUT
flash_otp_key_i.data_req Yes Yes T1,T4,T5 Yes T1,T4,T5 INPUT
flash_otp_key_o.seed_valid Yes Yes T18,T45,T19 Yes T1,T4,T18 OUTPUT
flash_otp_key_o.rand_key[127:0] Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
flash_otp_key_o.key[127:0] Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
flash_otp_key_o.addr_ack Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
flash_otp_key_o.data_ack Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
sram_otp_key_i[0].req Yes Yes T1,T4,T5 Yes T1,T4,T5 INPUT
sram_otp_key_i[1].req Yes Yes T1,T4,T5 Yes T1,T4,T5 INPUT
sram_otp_key_i[2].req Yes Yes T1,T4,T5 Yes T1,T4,T5 INPUT
sram_otp_key_i[3].req Yes Yes T1,T4,T5 Yes T1,T4,T5 INPUT
sram_otp_key_o[0].seed_valid Yes Yes T18,T45,T19 Yes T1,T4,T18 OUTPUT
sram_otp_key_o[0].nonce[127:0] Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
sram_otp_key_o[0].key[127:0] Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
sram_otp_key_o[0].ack Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
sram_otp_key_o[1].seed_valid Yes Yes T18,T45,T19 Yes T1,T4,T18 OUTPUT
sram_otp_key_o[1].nonce[127:0] Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
sram_otp_key_o[1].key[127:0] Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
sram_otp_key_o[1].ack Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
sram_otp_key_o[2].seed_valid Yes Yes T18,T45,T19 Yes T1,T4,T18 OUTPUT
sram_otp_key_o[2].nonce[127:0] Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
sram_otp_key_o[2].key[127:0] Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
sram_otp_key_o[2].ack Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
sram_otp_key_o[3].seed_valid Yes Yes T18,T45,T19 Yes T1,T4,T18 OUTPUT
sram_otp_key_o[3].nonce[127:0] Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
sram_otp_key_o[3].key[127:0] Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
sram_otp_key_o[3].ack Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
otbn_otp_key_i.req Yes Yes T1,T4,T5 Yes T1,T4,T5 INPUT
otbn_otp_key_o.seed_valid Yes Yes T18,T45,T19 Yes T1,T4,T18 OUTPUT
otbn_otp_key_o.nonce[63:0] Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
otbn_otp_key_o.key[127:0] Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
otbn_otp_key_o.ack Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
otp_broadcast_o.hw_cfg0_data.device_id[255:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_broadcast_o.hw_cfg0_data.manuf_state[255:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_broadcast_o.hw_cfg0_data.hw_cfg0_digest[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_broadcast_o.hw_cfg1_data.en_sram_ifetch[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_broadcast_o.hw_cfg1_data.en_csrng_sw_app_read[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_broadcast_o.hw_cfg1_data.dis_rv_dm_late_debug[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_broadcast_o.hw_cfg1_data.unallocated[39:0] Yes Yes T48,T110,T41 Yes T4,T48,T114 OUTPUT
otp_broadcast_o.hw_cfg1_data.hw_cfg1_digest[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_broadcast_o.valid[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_ext_voltage_h_io No No No INOUT
scan_en_i Yes Yes T1,T2,T4 Yes T1,T13,T18 INPUT
scan_rst_ni Yes Yes T1,T9,T4 Yes T2,T3,T4 INPUT
scanmode_i[3:0] Yes Yes T1,T3,T5 Yes T1,T2,T13 INPUT
cio_test_o[7:0] No No No OUTPUT
cio_test_en_o[7:0] Yes Yes T1,T19,T7 Yes T1,T10,T11 OUTPUT

*Tests covering at least one bit in the range

Branch Coverage for Module : otp_ctrl
Line No.TotalCoveredPercent
Branches 29 27 93.10
TERNARY 382 2 1 50.00
TERNARY 1439 2 2 100.00
TERNARY 1441 2 2 100.00
TERNARY 1443 2 2 100.00
IF 287 3 2 66.67
IF 308 2 2 100.00
IF 334 2 2 100.00
IF 341 2 2 100.00
IF 407 2 2 100.00
IF 448 2 2 100.00
IF 469 2 2 100.00
IF 472 2 2 100.00
IF 499 2 2 100.00
IF 991 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 382 ((reg2hw.direct_access_regwen.qe && (!reg2hw.direct_access_regwen.q))) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 1439 ((part_digest[Secret0Idx] != '0)) ?

Branches:
-1-StatusTests
1 Covered T9,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 1441 ((part_digest[Secret2Idx] != '0)) ?

Branches:
-1-StatusTests
1 Covered T9,T4,T18
0 Covered T1,T2,T3


LineNo. Expression -1-: 1443 ((part_digest[Secret2Idx] != '0)) ?

Branches:
-1-StatusTests
1 Covered T9,T4,T18
0 Covered T1,T2,T3


LineNo. Expression -1-: 287 if (tlul_req) -2-: 288 if ((tlul_part_sel_oh != '0))

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T3
1 0 Not Covered
0 - Covered T1,T2,T3


LineNo. Expression -1-: 308 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 334 if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_creator_seed_sw_rw_en))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 341 if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_owner_seed_sw_rw_en))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 407 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 448 if (otp_ctrl_part_pkg::PartInfo[k].integrity)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 469 if ((fatal_macro_error_q || fatal_check_error_q))

Branches:
-1-StatusTests
1 Covered T2,T3,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 472 if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_escalate_en[k]))

Branches:
-1-StatusTests
1 Covered T2,T3,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 499 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 991 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : otp_ctrl
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 71 71 100.00 69 97.18
Cover properties 0 0 0
Cover sequences 0 0 0
Total 71 71 100.00 69 97.18




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertTxKnown_A 442410951 441597661 0 0
CoreTlOutKnown_A 442410951 441597661 0 0
CreatorRootKeyShare0Size_A 1153 1153 0 0
CreatorRootKeyShare1Size_A 1153 1153 0 0
ErrorCodeWidth_A 1153 1153 0 0
FlashAddrKeySeedSize_A 1153 1153 0 0
FlashDataKeySeedSize_A 1153 1153 0 0
FlashOtpKeyRspKnown_A 442410951 441597661 0 0
FpvSecCmCntCnstyCheck_A 442410951 50 0 0
FpvSecCmCntDaiCheck_A 442410951 50 0 0
FpvSecCmCntIntegCheck_A 442410951 50 0 0
FpvSecCmCntKdiEntropyCheck_A 442410951 50 0 0
FpvSecCmCntKdiSeedCheck_A 442410951 50 0 0
FpvSecCmCntLciCheck_A 442410951 50 0 0
FpvSecCmCntScrmblCheck_A 442410951 50 0 0
FpvSecCmCtrlDaiFsmCheck_A 442410951 50 0 0
FpvSecCmCtrlKdiFsmCheck_A 442410951 50 0 0
FpvSecCmCtrlLciFsmCheck_A 442410951 50 0 0
FpvSecCmCtrlLfsrTimerFsmCheck_A 442410951 50 0 0
FpvSecCmCtrlScrambleFsmCheck_A 442410951 50 0 0
FpvSecCmDoubleLfsrCheck_A 442410951 50 0 0
FpvSecCmRegWeOnehotCheck_A 442410951 50 0 0
FpvSecCmTlLcGateFsm_A 442410951 50 0 0
IntrOtpErrorKnown_A 442410951 441597661 0 0
IntrOtpOperationDoneKnown_A 442410951 441597661 0 0
LcOtpProgramRspKnown_A 442410951 441597661 0 0
LcSeedHwRdEnStable0_A 442410951 1882 0 0
LcSeedHwRdEnStable1_A 442410951 1882 0 0
LcSeedHwRdEnStable2_A 442410951 0 0 0
LcSeedHwRdEnStable3_A 442410951 0 0 0
LcStateSize_A 1153 1153 0 0
LcTransitionCntSize_A 1153 1153 0 0
OtpAstPwrSeqKnown_A 442410951 441597661 0 0
OtpBroadcastKnown_A 442410951 441597661 0 0
OtpErrorCode0_A 1153 1153 0 0
OtpErrorCode1_A 1153 1153 0 0
OtpErrorCode2_A 1153 1153 0 0
OtpErrorCode3_A 1153 1153 0 0
OtpErrorCode4_A 1153 1153 0 0
OtpIfWidth_A 1153 1153 0 0
OtpKeymgrKeyKnown_A 442410951 441597661 0 0
OtpLcDataKnown_A 442410951 441597661 0 0
OtpOtgnKeyKnown_A 442410951 441597661 0 0
OtpRespFifoUnderflow_A 442410951 1324421 0 0
OtpSramKeyKnown_A 442410951 441597661 0 0
PartSelMustBeOnehot_A 442410951 441597661 0 0
PrimTlOutKnown_A 442410951 441597661 0 0
PwrOtpInitRspKnown_A 442410951 441597661 0 0
RmaTokenSize_A 1153 1153 0 0
SramDataKeySeedSize_A 1153 1153 0 0
TestExitTokenSize_A 1153 1153 0 0
TestUnlockTokenSize_A 1153 1153 0 0
gen_partitions[0].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A 442410951 50 0 0
gen_partitions[10].gen_lifecycle.FpvSecCmCntPartLcCheck_A 442410951 50 0 0
gen_partitions[10].gen_lifecycle.FpvSecCmCtrlPartLcFsmCheck_A 442410951 50 0 0
gen_partitions[1].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A 442410951 50 0 0
gen_partitions[2].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A 442410951 50 0 0
gen_partitions[3].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A 442410951 50 0 0
gen_partitions[4].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A 442410951 50 0 0
gen_partitions[5].gen_buffered.FpvSecCmCntPartBufCheck_A 442410951 50 0 0
gen_partitions[5].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A 442410951 50 0 0
gen_partitions[6].gen_buffered.FpvSecCmCntPartBufCheck_A 442410951 50 0 0
gen_partitions[6].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A 442410951 50 0 0
gen_partitions[7].gen_buffered.FpvSecCmCntPartBufCheck_A 442410951 50 0 0
gen_partitions[7].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A 442410951 50 0 0
gen_partitions[8].gen_buffered.FpvSecCmCntPartBufCheck_A 442410951 50 0 0
gen_partitions[8].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A 442410951 50 0 0
gen_partitions[9].gen_buffered.FpvSecCmCntPartBufCheck_A 442410951 50 0 0
gen_partitions[9].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A 442410951 50 0 0
gen_reg_we_assert_generic.FpvSecCmPrimFsmCheck_A 442410951 50 0 0
gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A 442410951 50 0 0


AlertTxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 441597661 0 0
T1 27746 27237 0 0
T2 8495 8216 0 0
T3 11001 10780 0 0
T4 39533 39049 0 0
T9 13971 13711 0 0
T10 4853 4777 0 0
T11 10429 10352 0 0
T12 16443 16188 0 0
T13 10573 10360 0 0
T14 4734 4666 0 0

CoreTlOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 441597661 0 0
T1 27746 27237 0 0
T2 8495 8216 0 0
T3 11001 10780 0 0
T4 39533 39049 0 0
T9 13971 13711 0 0
T10 4853 4777 0 0
T11 10429 10352 0 0
T12 16443 16188 0 0
T13 10573 10360 0 0
T14 4734 4666 0 0

CreatorRootKeyShare0Size_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1153 1153 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0

CreatorRootKeyShare1Size_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1153 1153 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0

ErrorCodeWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1153 1153 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0

FlashAddrKeySeedSize_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1153 1153 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0

FlashDataKeySeedSize_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1153 1153 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0

FlashOtpKeyRspKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 441597661 0 0
T1 27746 27237 0 0
T2 8495 8216 0 0
T3 11001 10780 0 0
T4 39533 39049 0 0
T9 13971 13711 0 0
T10 4853 4777 0 0
T11 10429 10352 0 0
T12 16443 16188 0 0
T13 10573 10360 0 0
T14 4734 4666 0 0

FpvSecCmCntCnstyCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

FpvSecCmCntDaiCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

FpvSecCmCntIntegCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

FpvSecCmCntKdiEntropyCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

FpvSecCmCntKdiSeedCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

FpvSecCmCntLciCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

FpvSecCmCntScrmblCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

FpvSecCmCtrlDaiFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

FpvSecCmCtrlKdiFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

FpvSecCmCtrlLciFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

FpvSecCmCtrlLfsrTimerFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

FpvSecCmCtrlScrambleFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

FpvSecCmDoubleLfsrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

FpvSecCmTlLcGateFsm_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

IntrOtpErrorKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 441597661 0 0
T1 27746 27237 0 0
T2 8495 8216 0 0
T3 11001 10780 0 0
T4 39533 39049 0 0
T9 13971 13711 0 0
T10 4853 4777 0 0
T11 10429 10352 0 0
T12 16443 16188 0 0
T13 10573 10360 0 0
T14 4734 4666 0 0

IntrOtpOperationDoneKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 441597661 0 0
T1 27746 27237 0 0
T2 8495 8216 0 0
T3 11001 10780 0 0
T4 39533 39049 0 0
T9 13971 13711 0 0
T10 4853 4777 0 0
T11 10429 10352 0 0
T12 16443 16188 0 0
T13 10573 10360 0 0
T14 4734 4666 0 0

LcOtpProgramRspKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 441597661 0 0
T1 27746 27237 0 0
T2 8495 8216 0 0
T3 11001 10780 0 0
T4 39533 39049 0 0
T9 13971 13711 0 0
T10 4853 4777 0 0
T11 10429 10352 0 0
T12 16443 16188 0 0
T13 10573 10360 0 0
T14 4734 4666 0 0

LcSeedHwRdEnStable0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 1882 0 0
T4 39533 1 0 0
T5 18478 0 0 0
T9 13971 1 0 0
T12 16443 0 0 0
T13 10573 0 0 0
T14 4734 0 0 0
T18 135070 10 0 0
T19 0 3 0 0
T41 0 13 0 0
T45 20422 2 0 0
T51 11783 0 0 0
T99 0 8 0 0
T108 0 1 0 0
T116 0 1 0 0
T117 0 1 0 0
T118 10705 0 0 0

LcSeedHwRdEnStable1_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 1882 0 0
T4 39533 1 0 0
T5 18478 0 0 0
T9 13971 1 0 0
T12 16443 0 0 0
T13 10573 0 0 0
T14 4734 0 0 0
T18 135070 10 0 0
T19 0 3 0 0
T41 0 13 0 0
T45 20422 2 0 0
T51 11783 0 0 0
T99 0 8 0 0
T108 0 1 0 0
T116 0 1 0 0
T117 0 1 0 0
T118 10705 0 0 0

LcSeedHwRdEnStable2_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 0 0 0

LcSeedHwRdEnStable3_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 0 0 0

LcStateSize_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1153 1153 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0

LcTransitionCntSize_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1153 1153 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0

OtpAstPwrSeqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 441597661 0 0
T1 27746 27237 0 0
T2 8495 8216 0 0
T3 11001 10780 0 0
T4 39533 39049 0 0
T9 13971 13711 0 0
T10 4853 4777 0 0
T11 10429 10352 0 0
T12 16443 16188 0 0
T13 10573 10360 0 0
T14 4734 4666 0 0

OtpBroadcastKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 441597661 0 0
T1 27746 27237 0 0
T2 8495 8216 0 0
T3 11001 10780 0 0
T4 39533 39049 0 0
T9 13971 13711 0 0
T10 4853 4777 0 0
T11 10429 10352 0 0
T12 16443 16188 0 0
T13 10573 10360 0 0
T14 4734 4666 0 0

OtpErrorCode0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1153 1153 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0

OtpErrorCode1_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1153 1153 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0

OtpErrorCode2_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1153 1153 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0

OtpErrorCode3_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1153 1153 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0

OtpErrorCode4_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1153 1153 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0

OtpIfWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1153 1153 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0

OtpKeymgrKeyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 441597661 0 0
T1 27746 27237 0 0
T2 8495 8216 0 0
T3 11001 10780 0 0
T4 39533 39049 0 0
T9 13971 13711 0 0
T10 4853 4777 0 0
T11 10429 10352 0 0
T12 16443 16188 0 0
T13 10573 10360 0 0
T14 4734 4666 0 0

OtpLcDataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 441597661 0 0
T1 27746 27237 0 0
T2 8495 8216 0 0
T3 11001 10780 0 0
T4 39533 39049 0 0
T9 13971 13711 0 0
T10 4853 4777 0 0
T11 10429 10352 0 0
T12 16443 16188 0 0
T13 10573 10360 0 0
T14 4734 4666 0 0

OtpOtgnKeyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 441597661 0 0
T1 27746 27237 0 0
T2 8495 8216 0 0
T3 11001 10780 0 0
T4 39533 39049 0 0
T9 13971 13711 0 0
T10 4853 4777 0 0
T11 10429 10352 0 0
T12 16443 16188 0 0
T13 10573 10360 0 0
T14 4734 4666 0 0

OtpRespFifoUnderflow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 1324421 0 0
T1 27746 462 0 0
T2 8495 109 0 0
T3 11001 141 0 0
T4 39533 475 0 0
T9 13971 268 0 0
T10 4853 55 0 0
T11 10429 55 0 0
T12 16443 223 0 0
T13 10573 129 0 0
T14 4734 55 0 0

OtpSramKeyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 441597661 0 0
T1 27746 27237 0 0
T2 8495 8216 0 0
T3 11001 10780 0 0
T4 39533 39049 0 0
T9 13971 13711 0 0
T10 4853 4777 0 0
T11 10429 10352 0 0
T12 16443 16188 0 0
T13 10573 10360 0 0
T14 4734 4666 0 0

PartSelMustBeOnehot_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 441597661 0 0
T1 27746 27237 0 0
T2 8495 8216 0 0
T3 11001 10780 0 0
T4 39533 39049 0 0
T9 13971 13711 0 0
T10 4853 4777 0 0
T11 10429 10352 0 0
T12 16443 16188 0 0
T13 10573 10360 0 0
T14 4734 4666 0 0

PrimTlOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 441597661 0 0
T1 27746 27237 0 0
T2 8495 8216 0 0
T3 11001 10780 0 0
T4 39533 39049 0 0
T9 13971 13711 0 0
T10 4853 4777 0 0
T11 10429 10352 0 0
T12 16443 16188 0 0
T13 10573 10360 0 0
T14 4734 4666 0 0

PwrOtpInitRspKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 441597661 0 0
T1 27746 27237 0 0
T2 8495 8216 0 0
T3 11001 10780 0 0
T4 39533 39049 0 0
T9 13971 13711 0 0
T10 4853 4777 0 0
T11 10429 10352 0 0
T12 16443 16188 0 0
T13 10573 10360 0 0
T14 4734 4666 0 0

RmaTokenSize_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1153 1153 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0

SramDataKeySeedSize_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1153 1153 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0

TestExitTokenSize_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1153 1153 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0

TestUnlockTokenSize_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1153 1153 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0

gen_partitions[0].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

gen_partitions[10].gen_lifecycle.FpvSecCmCntPartLcCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

gen_partitions[10].gen_lifecycle.FpvSecCmCtrlPartLcFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

gen_partitions[1].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

gen_partitions[2].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

gen_partitions[3].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

gen_partitions[4].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

gen_partitions[5].gen_buffered.FpvSecCmCntPartBufCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

gen_partitions[5].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

gen_partitions[6].gen_buffered.FpvSecCmCntPartBufCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

gen_partitions[6].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

gen_partitions[7].gen_buffered.FpvSecCmCntPartBufCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

gen_partitions[7].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

gen_partitions[8].gen_buffered.FpvSecCmCntPartBufCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

gen_partitions[8].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

gen_partitions[9].gen_buffered.FpvSecCmCntPartBufCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

gen_partitions[9].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

gen_reg_we_assert_generic.FpvSecCmPrimFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

Line Coverage for Instance : tb.dut
Line No.TotalCoveredPercent
TOTAL15414594.16
CONT_ASSIGN25111100.00
CONT_ASSIGN25311100.00
CONT_ASSIGN25311100.00
CONT_ASSIGN25311100.00
CONT_ASSIGN25311100.00
CONT_ASSIGN25311100.00
CONT_ASSIGN25311100.00
CONT_ASSIGN25311100.00
CONT_ASSIGN25311100.00
CONT_ASSIGN25311100.00
CONT_ASSIGN25311100.00
ALWAYS2841313100.00
ALWAYS30833100.00
ALWAYS3241010100.00
CONT_ASSIGN38211100.00
CONT_ASSIGN38611100.00
CONT_ASSIGN39011100.00
CONT_ASSIGN39411100.00
CONT_ASSIGN39511100.00
CONT_ASSIGN40311100.00
CONT_ASSIGN40411100.00
ALWAYS40755100.00
ALWAYS4341919100.00
CONT_ASSIGN48811100.00
CONT_ASSIGN49611100.00
ALWAYS49999100.00
ALWAYS5211010100.00
CONT_ASSIGN58511100.00
CONT_ASSIGN59311100.00
CONT_ASSIGN64011100.00
CONT_ASSIGN64211100.00
CONT_ASSIGN76511100.00
CONT_ASSIGN76611100.00
CONT_ASSIGN76711100.00
CONT_ASSIGN79711100.00
CONT_ASSIGN79911100.00
ALWAYS87622100.00
ALWAYS93422100.00
ALWAYS96144100.00
CONT_ASSIGN98811100.00
ALWAYS99133100.00
CONT_ASSIGN104311100.00
CONT_ASSIGN104511100.00
CONT_ASSIGN1079100.00
CONT_ASSIGN1130100.00
CONT_ASSIGN118511100.00
CONT_ASSIGN118511100.00
CONT_ASSIGN118511100.00
CONT_ASSIGN118511100.00
CONT_ASSIGN118511100.00
CONT_ASSIGN1240100.00
CONT_ASSIGN1240100.00
CONT_ASSIGN1240100.00
CONT_ASSIGN1240100.00
CONT_ASSIGN1240100.00
CONT_ASSIGN1300100.00
CONT_ASSIGN1312100.00
CONT_ASSIGN133611100.00
ALWAYS134822100.00
CONT_ASSIGN136211100.00
ALWAYS139099100.00
CONT_ASSIGN142111100.00
CONT_ASSIGN142211100.00
CONT_ASSIGN142411100.00
CONT_ASSIGN142611100.00
CONT_ASSIGN143011100.00
CONT_ASSIGN143211100.00
CONT_ASSIGN143411100.00
CONT_ASSIGN143911100.00
CONT_ASSIGN144111100.00
CONT_ASSIGN144311100.00
CONT_ASSIGN147511100.00
CONT_ASSIGN147711100.00
CONT_ASSIGN148111100.00
CONT_ASSIGN148511100.00
CONT_ASSIGN148911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
251 1 1
253 10 10
284 1 1
285 1 1
286 1 1
287 1 1
288 1 1
289 1 1
292 excluded
Exclude Annotation: VC_COV_UNR
MISSING_ELSE
297 1 1
298 1 1
299 1 1
300 1 1
301 1 1
302 1 1
303 1 1
308 1 1
309 1 1
311 1 1
324 1 1
329 1 1
330 1 1
334 1 1
335 1 1
336 1 1
337 1 1
MISSING_ELSE
MISSING_ELSE
341 1 1
342 1 1
343 1 1
344 excluded
Exclude Annotation: VC_COV_UNR
MISSING_ELSE
MISSING_ELSE
382 1 1
386 1 1
390 1 1
394 1 1
395 1 1
403 1 1
404 1 1
407 1 1
408 1 1
410 1 1
412 1 1
413 1 1
434 1 1
435 1 1
436 1 1
438 1 1
440 1 1
443 1 1
445 1 1
448 1 1
449 1 1
MISSING_ELSE
453 1 1
455 1 1
459 1 1
462 1 1
464 1 1
469 1 1
470 1 1
MISSING_ELSE
472 1 1
473 1 1
MISSING_ELSE
478 1 1
488 1 1
496 1 1
499 1 1
500 1 1
501 1 1
502 1 1
503 1 1
505 1 1
506 1 1
507 1 1
508 1 1
521 1 1
523 1 1
525 1 1
527 1 1
529 1 1
538 1 1
540 1 1
541 1 1
542 1 1
543 1 1
585 1 1
593 1 1
640 1 1
642 1 1
765 1 1
766 1 1
767 1 1
797 1 1
799 1 1
876 1 1
877 1 1
934 1 1
935 1 1
961 1 1
962 1 1
963 1 1
964 1 1
988 1 1
991 1 1
992 1 1
994 1 1
1043 1 1
1045 1 1
1079 0 1
1130 0 1
1185 5 5
1240 0 5
1300 0 1
1312 0 1
1336 1 1
1348 1 1
1349 1 1
1362 1 1
1390 1 1
1391 1 1
1392 1 1
1393 1 1
1395 1 1
1396 1 1
1397 1 1
1398 1 1
1399 1 1
1421 1 1
1422 1 1
1424 1 1
1426 1 1
1430 1 1
1432 1 1
1434 1 1
1439 1 1
1441 1 1
1443 1 1
1475 1 1
1477 1 1
1481 1 1
1485 1 1
1489 1 1


Cond Coverage for Instance : tb.dut
TotalCoveredPercent
Conditions10410096.15
Logical10410096.15
Non-Logical00
Event00

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b00001000000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[1].PartEnd))
             -------------------1------------------   --------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b00111011000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[2].PartEnd))
             -------------------1------------------   --------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b10001111000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[3].PartEnd))
             -------------------1------------------   --------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11001010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[4].PartEnd))
             -------------------1------------------   --------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT7,T15,T16
11CoveredT1,T2,T3

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11001111000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[5].PartEnd))
             -------------------1------------------   --------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT7,T15,T16
11CoveredT7,T15,T16

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011000000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[6].PartEnd))
             -------------------1------------------   --------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT7,T15,T16
11CoveredT7,T15,T16

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[7].PartEnd))
             -------------------1------------------   --------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT7,T15,T16
11CoveredT7,T15,T16

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011111000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[8].PartEnd))
             -------------------1------------------   --------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT7,T15,T16
11CoveredT7,T15,T16

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11101010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[9].PartEnd))
             -------------------1------------------   --------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT7,T15,T16
11CoveredT7,T15,T16

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11110101000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[10].PartEnd))
             -------------------1------------------   ---------------------------2--------------------------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded vcs_gen_start:k=10:vcs_gen_end:VC_COV_UNR
11CoveredT7,T15,T16

 LINE       288
 EXPRESSION (tlul_part_sel_oh != '0)
            ------------1-----------
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1CoveredT1,T2,T3

 LINE       297
 EXPRESSION (((|part_tlul_gnt)) | tlul_oob_err_q)
             ---------1--------   -------2------
-1--2-StatusTestsExclude Annotation
00CoveredT1,T2,T3
01Excluded VC_COV_UNR
10CoveredT1,T2,T3

 LINE       298
 EXPRESSION (((|part_tlul_rvalid)) | tlul_oob_err_q)
             ----------1----------   -------2------
-1--2-StatusTestsExclude Annotation
00CoveredT1,T2,T3
01Excluded VC_COV_UNR
10CoveredT1,T2,T3

 LINE       382
 EXPRESSION ((reg2hw.direct_access_regwen.qe && ((!reg2hw.direct_access_regwen.q))) ? 1'b0 : direct_access_regwen_q)
             -----------------------------------1----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       382
 SUB-EXPRESSION (reg2hw.direct_access_regwen.qe && ((!reg2hw.direct_access_regwen.q)))
                 ---------------1--------------    -----------------2----------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       386
 EXPRESSION (reg2hw.direct_access_cmd.digest.qe | reg2hw.direct_access_cmd.wr.qe | reg2hw.direct_access_cmd.rd.qe)
             -----------------1----------------   ---------------2--------------   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
000CoveredT1,T2,T3
001Excluded VC_COV_UNR
010Excluded VC_COV_UNR
100Excluded VC_COV_UNR

 LINE       403
 EXPRESSION (lci_prog_idle & dai_prog_idle)
             ------1------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       436
 EXPRESSION (fatal_bus_integ_error_q | ((|intg_error)))
             -----------1-----------   -------2-------
-1--2-StatusTestsExclude Annotation
00CoveredT1,T2,T3
01CoveredT26,T27,T28
10Excluded VC_COV_UNR

 LINE       445
 EXPRESSION (part_error[k] == MacroError)
            --------------1--------------
-1-StatusTestsExclude Annotation
0CoveredT1,T2,T3
1Excluded VC_COV_UNR

 LINE       449
 EXPRESSION (part_error[k] == MacroEccUncorrError)
            -------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T13,T118

 LINE       469
 EXPRESSION (fatal_macro_error_q || fatal_check_error_q)
             ---------1---------    ---------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T9,T12
10CoveredT3,T13,T118

 LINE       478
 EXPRESSION (chk_timeout | lfsr_fsm_err | scrmbl_fsm_err | ((|part_fsm_err)))
             -----1-----   ------2-----   -------3------   --------4--------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001CoveredT2,T3,T9
0010CoveredT26,T27,T28
0100CoveredT26,T27,T28
1000CoveredT15,T41,T74

 LINE       527
 EXPRESSION (direct_access_regwen_q & dai_idle)
             -----------1----------   ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       593
 SUB-EXPRESSION (reg2hw.alert_test.recov_prim_otp_alert.q & reg2hw.alert_test.recov_prim_otp_alert.qe)
                 --------------------1-------------------   --------------------2--------------------
-1--2-StatusTests
01CoveredT10,T11,T14
10CoveredT1,T2,T3
11CoveredT10,T11,T14

 LINE       593
 SUB-EXPRESSION (reg2hw.alert_test.fatal_prim_otp_alert.q & reg2hw.alert_test.fatal_prim_otp_alert.qe)
                 --------------------1-------------------   --------------------2--------------------
-1--2-StatusTests
01CoveredT10,T11,T14
10CoveredT1,T2,T3
11CoveredT10,T11,T14

 LINE       593
 SUB-EXPRESSION (reg2hw.alert_test.fatal_bus_integ_error.q & reg2hw.alert_test.fatal_bus_integ_error.qe)
                 --------------------1--------------------   ---------------------2--------------------
-1--2-StatusTests
01CoveredT10,T11,T14
10CoveredT1,T2,T3
11CoveredT10,T11,T14

 LINE       593
 SUB-EXPRESSION (reg2hw.alert_test.fatal_check_error.q & reg2hw.alert_test.fatal_check_error.qe)
                 ------------------1------------------   -------------------2------------------
-1--2-StatusTests
01CoveredT10,T11,T14
10CoveredT1,T2,T3
11CoveredT10,T11,T14

 LINE       593
 SUB-EXPRESSION (reg2hw.alert_test.fatal_macro_error.q & reg2hw.alert_test.fatal_macro_error.qe)
                 ------------------1------------------   -------------------2------------------
-1--2-StatusTests
01CoveredT10,T11,T14
10CoveredT1,T2,T3
11CoveredT10,T11,T14

 LINE       640
 EXPRESSION (reg2hw.check_trigger.integrity.q & reg2hw.check_trigger.integrity.qe)
             ----------------1---------------   ----------------2----------------
-1--2-StatusTests
01CoveredT1,T18,T45
10CoveredT1,T2,T3
11CoveredT4,T18,T19

 LINE       642
 EXPRESSION (reg2hw.check_trigger.consistency.q & reg2hw.check_trigger.consistency.qe)
             -----------------1----------------   -----------------2-----------------
-1--2-StatusTests
01CoveredT4,T18,T45
10CoveredT1,T2,T3
11CoveredT1,T4,T18

 LINE       765
 EXPRESSION (otp_prim_ready & otp_rsp_fifo_ready)
             -------1------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       766
 EXPRESSION (otp_arb_valid & otp_rsp_fifo_ready)
             ------1------   ---------2--------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11CoveredT1,T2,T3

 LINE       767
 EXPRESSION (otp_prim_ready & otp_prim_valid)
             -------1------   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       877
 EXPRESSION (otp_rvalid & otp_fifo_valid)
             -----1----   -------2------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11CoveredT1,T2,T3

 LINE       1421
 EXPRESSION (part_digest[Secret1Idx] != '0)
            ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T9,T4

 LINE       1439
 EXPRESSION ((part_digest[Secret0Idx] != '0) ? On : Off)
             ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T4,T5

 LINE       1439
 SUB-EXPRESSION (part_digest[Secret0Idx] != '0)
                ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T4,T5

 LINE       1441
 EXPRESSION ((part_digest[Secret2Idx] != '0) ? On : Off)
             ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T4,T18

 LINE       1441
 SUB-EXPRESSION (part_digest[Secret2Idx] != '0)
                ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T4,T18

 LINE       1443
 EXPRESSION ((part_digest[Secret2Idx] != '0) ? On : Off)
             ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T4,T18

 LINE       1443
 SUB-EXPRESSION (part_digest[Secret2Idx] != '0)
                ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T4,T18

Toggle Coverage for Instance : tb.dut
TotalCoveredPercent
Totals 149 142 95.30
Total Bits 9984 9692 97.08
Total Bits 0->1 4992 4846 97.08
Total Bits 1->0 4992 4846 97.08

Ports 149 142 95.30
Port Bits 9984 9692 97.08
Port Bits 0->1 4992 4846 97.08
Port Bits 1->0 4992 4846 97.08

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_edn_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_edn_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_o.edn_req Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
edn_i.edn_bus[31:0] Yes Yes T1,T4,T5 Yes T1,T4,T5 INPUT
edn_i.edn_fips Yes Yes T1,T4,T5 Yes T1,T4,T5 INPUT
edn_i.edn_ack Yes Yes T1,T4,T5 Yes T1,T4,T5 INPUT
core_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_user.instr_type[3:0] Yes Yes T3,T10,T5 Yes T3,T10,T5 INPUT
core_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
core_tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_address[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_source[7:0] Yes Yes T1,T3,T10 Yes T1,T2,T3 INPUT
core_tl_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
core_tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
core_tl_o.d_error Yes Yes T1,T18,T19 Yes T1,T18,T19 OUTPUT
core_tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
core_tl_o.d_user.rsp_intg[5:0] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
core_tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
core_tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
core_tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
core_tl_o.d_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
core_tl_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
core_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
core_tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
core_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
core_tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
prim_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
prim_tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
prim_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
prim_tl_i.a_user.instr_type[3:0] Yes Yes T2,T3,T13 Yes T2,T13,T123 INPUT
prim_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
prim_tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
prim_tl_i.a_mask[3:0] Yes Yes T2,T3,T13 Yes T2,T3,T13 INPUT
prim_tl_i.a_address[31:0] Yes Yes T2,T3,T123 Yes T2,T3,T13 INPUT
prim_tl_i.a_source[7:0] Yes Yes T2,T3,T4 Yes T3,T4,T13 INPUT
prim_tl_i.a_size[1:0] Yes Yes T2,T3,T13 Yes T2,T3,T13 INPUT
prim_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
prim_tl_i.a_opcode[2:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
prim_tl_i.a_valid Yes Yes T1,T4,T5 Yes T1,T4,T5 INPUT
prim_tl_o.a_ready Yes Yes T1,T10,T11 Yes T1,T10,T11 OUTPUT
prim_tl_o.d_error Yes Yes T1,T10,T11 Yes T1,T19,T7 OUTPUT
prim_tl_o.d_user.data_intg[6:0] Yes Yes T1,T19,T55 Yes T1,T19,T55 OUTPUT
prim_tl_o.d_user.rsp_intg[5:0] Yes Yes *T1,*T4,*T5 Yes T1,T4,T5 OUTPUT
prim_tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
prim_tl_o.d_data[31:0] Yes Yes T1,T10,T11 Yes T1,T19,T7 OUTPUT
prim_tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
prim_tl_o.d_source[7:0] Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
prim_tl_o.d_size[1:0] Yes Yes T7,T15,T16 Yes T7,T15,T16 OUTPUT
prim_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
prim_tl_o.d_opcode[0] Yes Yes *T1,*T10,*T11 Yes T1,T4,T5 OUTPUT
prim_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
prim_tl_o.d_valid Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
intr_otp_operation_done_o Yes Yes T1,T3,T9 Yes T1,T3,T9 OUTPUT
intr_otp_error_o Yes Yes T1,T3,T9 Yes T1,T3,T9 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T3,T10,T11 Yes T3,T10,T11 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T2,T3,T10 Yes T2,T3,T10 INPUT
alert_rx_i[1].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[2].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[2].ack_p Yes Yes T10,T11,T14 Yes T10,T11,T14 INPUT
alert_rx_i[2].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[2].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[3].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[3].ack_p Yes Yes T10,T11,T14 Yes T10,T11,T14 INPUT
alert_rx_i[3].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[3].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[4].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[4].ack_p Yes Yes T10,T11,T14 Yes T10,T11,T14 INPUT
alert_rx_i[4].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[4].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T3,T10,T11 Yes T3,T10,T11 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T2,T3,T10 Yes T2,T3,T10 OUTPUT
alert_tx_o[2].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[2].alert_p Yes Yes T10,T11,T14 Yes T10,T11,T14 OUTPUT
alert_tx_o[3].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[3].alert_p Yes Yes T10,T11,T14 Yes T10,T11,T14 OUTPUT
alert_tx_o[4].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[4].alert_p Yes Yes T10,T11,T14 Yes T10,T11,T14 OUTPUT
obs_ctrl_i.obmen[3:0] No No No INPUT
obs_ctrl_i.obmsl[3:0] No No No INPUT
obs_ctrl_i.obgsl[3:0] No No No INPUT
otp_obs_o[7:0] Unreachable Unreachable Unreachable OUTPUT
otp_ast_pwr_seq_o.pwr_seq[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
otp_ast_pwr_seq_h_i.pwr_seq_h[1:0] Yes Yes T3,T4,T18 Yes T4,T13,T18 INPUT
pwr_otp_i.otp_init Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
pwr_otp_o.otp_idle Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
pwr_otp_o.otp_done Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
lc_otp_vendor_test_i.ctrl[31:0] No No No INPUT
lc_otp_vendor_test_o.status[31:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
lc_otp_program_i.count[383:0] Yes Yes T7,T15,T41 Yes T7,T15,T16 INPUT
lc_otp_program_i.state[319:0] Yes Yes T15,T41,T100 Yes T15,T41,T100 INPUT
lc_otp_program_i.req Yes Yes T1,T4,T5 Yes T1,T4,T5 INPUT
lc_otp_program_o.ack Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
lc_otp_program_o.err Yes Yes T15,T100,T257 Yes T15,T100,T257 OUTPUT
lc_creator_seed_sw_rw_en_i[3:0] Yes Yes T1,T5,T18 Yes T1,T5,T18 INPUT
lc_owner_seed_sw_rw_en_i[3:0] Yes Yes T1,T5,T18 Yes T1,T5,T18 INPUT
lc_seed_hw_rd_en_i[3:0] Yes Yes T1,T9,T4 Yes T1,T2,T3 INPUT
lc_dft_en_i[3:0] Yes Yes T1,T118,T19 Yes T1,T2,T10 INPUT
lc_escalate_en_i[3:0] Yes Yes T114,T7,T115 Yes T114,T7,T115 INPUT
lc_check_byp_en_i[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
otp_lc_data_o.rma_token[127:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.rma_token_valid[3:0] Yes Yes T9,T18,T45 Yes T9,T4,T18 OUTPUT
otp_lc_data_o.test_exit_token[127:0] Yes Yes T18,T19,T48 Yes T18,T19,T48 OUTPUT
otp_lc_data_o.test_unlock_token[127:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.test_tokens_valid[3:0] Yes Yes T9,T4,T5 Yes T9,T4,T5 OUTPUT
otp_lc_data_o.secrets_valid[3:0] Yes Yes T9,T18,T45 Yes T9,T4,T18 OUTPUT
otp_lc_data_o.count[0] No No No OUTPUT
otp_lc_data_o.count[3:1] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[4] No No No OUTPUT
otp_lc_data_o.count[8:5] Yes Yes T1,T4,*T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.count[9] No No No OUTPUT
otp_lc_data_o.count[10] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[11] No No No OUTPUT
otp_lc_data_o.count[27:12] Yes Yes T1,*T4,*T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.count[28] No No No OUTPUT
otp_lc_data_o.count[29] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[32:30] No No No OUTPUT
otp_lc_data_o.count[54:33] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[55] No No No OUTPUT
otp_lc_data_o.count[64:56] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[65] No No No OUTPUT
otp_lc_data_o.count[101:66] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[102] No No No OUTPUT
otp_lc_data_o.count[105:103] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[106] No No No OUTPUT
otp_lc_data_o.count[118:107] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[119] No No No OUTPUT
otp_lc_data_o.count[124:120] Yes Yes T1,*T4,*T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.count[125] No No No OUTPUT
otp_lc_data_o.count[134:126] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[135] No No No OUTPUT
otp_lc_data_o.count[137:136] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[138] No No No OUTPUT
otp_lc_data_o.count[142:139] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[143] No No No OUTPUT
otp_lc_data_o.count[147:144] Yes Yes T1,T4,*T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.count[148] No No No OUTPUT
otp_lc_data_o.count[164:149] Yes Yes T1,*T4,*T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.count[165] No No No OUTPUT
otp_lc_data_o.count[171:166] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[172] No No No OUTPUT
otp_lc_data_o.count[174:173] Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.count[175] No No No OUTPUT
otp_lc_data_o.count[188:176] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[189] No No No OUTPUT
otp_lc_data_o.count[191:190] Yes Yes *T5,*T18,*T45 Yes T1,T5,T18 OUTPUT
otp_lc_data_o.count[192] No No No OUTPUT
otp_lc_data_o.count[196:193] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[197] No No No OUTPUT
otp_lc_data_o.count[198] Yes Yes *T1,*T4,*T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.count[199] No No No OUTPUT
otp_lc_data_o.count[202:200] Yes Yes *T5,*T18,*T45 Yes T1,T5,T18 OUTPUT
otp_lc_data_o.count[203] No No No OUTPUT
otp_lc_data_o.count[206:204] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[208:207] No No No OUTPUT
otp_lc_data_o.count[217:209] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[218] No No No OUTPUT
otp_lc_data_o.count[225:219] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[226] No No No OUTPUT
otp_lc_data_o.count[237:227] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[238] No No No OUTPUT
otp_lc_data_o.count[240:239] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[241] No No No OUTPUT
otp_lc_data_o.count[243:242] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[244] No No No OUTPUT
otp_lc_data_o.count[266:245] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[267] No No No OUTPUT
otp_lc_data_o.count[269:268] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[270] No No No OUTPUT
otp_lc_data_o.count[272:271] Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.count[273] No No No OUTPUT
otp_lc_data_o.count[284:274] Yes Yes *T5,*T18,*T45 Yes T1,T5,T18 OUTPUT
otp_lc_data_o.count[286:285] No No No OUTPUT
otp_lc_data_o.count[303:287] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[304] No No No OUTPUT
otp_lc_data_o.count[309:305] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[310] No No No OUTPUT
otp_lc_data_o.count[312:311] Yes Yes T1,T4,*T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.count[313] No No No OUTPUT
otp_lc_data_o.count[324:314] Yes Yes T1,T4,*T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.count[325] No No No OUTPUT
otp_lc_data_o.count[330:326] Yes Yes T1,T4,*T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.count[331] No No No OUTPUT
otp_lc_data_o.count[335:332] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[336] No No No OUTPUT
otp_lc_data_o.count[343:337] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[344] No No No OUTPUT
otp_lc_data_o.count[345] Yes Yes *T1,*T4,*T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.count[346] No No No OUTPUT
otp_lc_data_o.count[364:347] Yes Yes T1,T4,*T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.count[365] No No No OUTPUT
otp_lc_data_o.count[366] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[367] No No No OUTPUT
otp_lc_data_o.count[371:368] Yes Yes T1,T4,*T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.count[372] No No No OUTPUT
otp_lc_data_o.count[375:373] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.count[376] No No No OUTPUT
otp_lc_data_o.count[383:377] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[9:0] Yes Yes T1,T4,*T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.state[10] No No No OUTPUT
otp_lc_data_o.state[14:11] Yes Yes T1,T4,*T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.state[15] No No No OUTPUT
otp_lc_data_o.state[17:16] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[18] No No No OUTPUT
otp_lc_data_o.state[34:19] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[35] No No No OUTPUT
otp_lc_data_o.state[36] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[37] No No No OUTPUT
otp_lc_data_o.state[42:38] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[43] No No No OUTPUT
otp_lc_data_o.state[46:44] Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.state[48:47] No No No OUTPUT
otp_lc_data_o.state[51:49] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[52] No No No OUTPUT
otp_lc_data_o.state[68:53] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[69] No No No OUTPUT
otp_lc_data_o.state[75:70] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[76] No No No OUTPUT
otp_lc_data_o.state[79:77] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[80] No No No OUTPUT
otp_lc_data_o.state[84:81] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[85] No No No OUTPUT
otp_lc_data_o.state[98:86] Yes Yes T1,T4,*T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.state[99] No No No OUTPUT
otp_lc_data_o.state[101:100] Yes Yes T1,T4,*T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.state[102] No No No OUTPUT
otp_lc_data_o.state[103] Yes Yes *T1,*T4,*T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.state[104] No No No OUTPUT
otp_lc_data_o.state[105] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[107:106] No No No OUTPUT
otp_lc_data_o.state[110:108] Yes Yes T1,T4,*T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.state[111] No No No OUTPUT
otp_lc_data_o.state[126:112] Yes Yes T1,T4,*T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.state[127] No No No OUTPUT
otp_lc_data_o.state[136:128] Yes Yes T1,T4,*T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.state[137] No No No OUTPUT
otp_lc_data_o.state[141:138] Yes Yes T1,T4,*T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.state[142] No No No OUTPUT
otp_lc_data_o.state[145:143] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[146] No No No OUTPUT
otp_lc_data_o.state[151:147] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[152] No No No OUTPUT
otp_lc_data_o.state[153] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[154] No No No OUTPUT
otp_lc_data_o.state[160:155] Yes Yes T1,T4,*T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.state[161] No No No OUTPUT
otp_lc_data_o.state[163:162] Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.state[164] No No No OUTPUT
otp_lc_data_o.state[177:165] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[178] No No No OUTPUT
otp_lc_data_o.state[180:179] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[181] No No No OUTPUT
otp_lc_data_o.state[182] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[184:183] No No No OUTPUT
otp_lc_data_o.state[191:185] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[192] No No No OUTPUT
otp_lc_data_o.state[198:193] Yes Yes T1,T4,*T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.state[199] No No No OUTPUT
otp_lc_data_o.state[210:200] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[211] No No No OUTPUT
otp_lc_data_o.state[214:212] Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.state[215] No No No OUTPUT
otp_lc_data_o.state[217:216] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[218] No No No OUTPUT
otp_lc_data_o.state[219] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[220] No No No OUTPUT
otp_lc_data_o.state[226:221] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[227] No No No OUTPUT
otp_lc_data_o.state[230:228] Yes Yes T1,T5,T18 Yes T1,T5,T18 OUTPUT
otp_lc_data_o.state[231] No No No OUTPUT
otp_lc_data_o.state[234:232] Yes Yes T1,*T5,*T18 Yes T1,T5,T18 OUTPUT
otp_lc_data_o.state[235] No No No OUTPUT
otp_lc_data_o.state[236] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[237] No No No OUTPUT
otp_lc_data_o.state[239:238] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[240] No No No OUTPUT
otp_lc_data_o.state[241] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[242] No No No OUTPUT
otp_lc_data_o.state[250:243] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[251] No No No OUTPUT
otp_lc_data_o.state[263:252] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[264] No No No OUTPUT
otp_lc_data_o.state[277:265] Yes Yes *T1,*T4,*T5 Yes T1,T4,T5 OUTPUT
otp_lc_data_o.state[278] No No No OUTPUT
otp_lc_data_o.state[284:279] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[285] No No No OUTPUT
otp_lc_data_o.state[301:286] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[302] No No No OUTPUT
otp_lc_data_o.state[307:303] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[308] No No No OUTPUT
otp_lc_data_o.state[311:309] Yes Yes *T5,*T19,*T48 Yes T5,T19,T48 OUTPUT
otp_lc_data_o.state[312] No No No OUTPUT
otp_lc_data_o.state[316:313] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.state[317] No No No OUTPUT
otp_lc_data_o.state[319:318] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_lc_data_o.error Yes Yes T2,T3,T9 Yes T2,T3,T9 OUTPUT
otp_lc_data_o.valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_keymgr_key_o.owner_seed_valid Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
otp_keymgr_key_o.owner_seed[255:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
otp_keymgr_key_o.creator_seed_valid Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
otp_keymgr_key_o.creator_seed[255:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
otp_keymgr_key_o.creator_root_key_share1_valid Yes Yes T9,T18,T45 Yes T9,T4,T18 OUTPUT
otp_keymgr_key_o.creator_root_key_share1[255:0] Yes Yes T1,T9,T4 Yes T1,T11,T9 OUTPUT
otp_keymgr_key_o.creator_root_key_share0_valid Yes Yes T9,T18,T45 Yes T9,T4,T18 OUTPUT
otp_keymgr_key_o.creator_root_key_share0[255:0] Yes Yes T4,T117,T41 Yes T41,T74,T146 OUTPUT
flash_otp_key_i.addr_req Yes Yes T1,T4,T5 Yes T1,T4,T5 INPUT
flash_otp_key_i.data_req Yes Yes T1,T4,T5 Yes T1,T4,T5 INPUT
flash_otp_key_o.seed_valid Yes Yes T18,T45,T19 Yes T1,T4,T18 OUTPUT
flash_otp_key_o.rand_key[127:0] Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
flash_otp_key_o.key[127:0] Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
flash_otp_key_o.addr_ack Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
flash_otp_key_o.data_ack Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
sram_otp_key_i[0].req Yes Yes T1,T4,T5 Yes T1,T4,T5 INPUT
sram_otp_key_i[1].req Yes Yes T1,T4,T5 Yes T1,T4,T5 INPUT
sram_otp_key_i[2].req Yes Yes T1,T4,T5 Yes T1,T4,T5 INPUT
sram_otp_key_i[3].req Yes Yes T1,T4,T5 Yes T1,T4,T5 INPUT
sram_otp_key_o[0].seed_valid Yes Yes T18,T45,T19 Yes T1,T4,T18 OUTPUT
sram_otp_key_o[0].nonce[127:0] Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
sram_otp_key_o[0].key[127:0] Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
sram_otp_key_o[0].ack Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
sram_otp_key_o[1].seed_valid Yes Yes T18,T45,T19 Yes T1,T4,T18 OUTPUT
sram_otp_key_o[1].nonce[127:0] Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
sram_otp_key_o[1].key[127:0] Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
sram_otp_key_o[1].ack Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
sram_otp_key_o[2].seed_valid Yes Yes T18,T45,T19 Yes T1,T4,T18 OUTPUT
sram_otp_key_o[2].nonce[127:0] Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
sram_otp_key_o[2].key[127:0] Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
sram_otp_key_o[2].ack Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
sram_otp_key_o[3].seed_valid Yes Yes T18,T45,T19 Yes T1,T4,T18 OUTPUT
sram_otp_key_o[3].nonce[127:0] Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
sram_otp_key_o[3].key[127:0] Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
sram_otp_key_o[3].ack Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
otbn_otp_key_i.req Yes Yes T1,T4,T5 Yes T1,T4,T5 INPUT
otbn_otp_key_o.seed_valid Yes Yes T18,T45,T19 Yes T1,T4,T18 OUTPUT
otbn_otp_key_o.nonce[63:0] Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
otbn_otp_key_o.key[127:0] Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
otbn_otp_key_o.ack Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
otp_broadcast_o.hw_cfg0_data.device_id[255:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_broadcast_o.hw_cfg0_data.manuf_state[255:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_broadcast_o.hw_cfg0_data.hw_cfg0_digest[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_broadcast_o.hw_cfg1_data.en_sram_ifetch[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_broadcast_o.hw_cfg1_data.en_csrng_sw_app_read[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_broadcast_o.hw_cfg1_data.dis_rv_dm_late_debug[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_broadcast_o.hw_cfg1_data.unallocated[39:0] Yes Yes T48,T110,T41 Yes T4,T48,T114 OUTPUT
otp_broadcast_o.hw_cfg1_data.hw_cfg1_digest[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_broadcast_o.valid[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_ext_voltage_h_io No No No INOUT
scan_en_i Yes Yes T1,T2,T4 Yes T1,T13,T18 INPUT
scan_rst_ni Yes Yes T1,T9,T4 Yes T2,T3,T4 INPUT
scanmode_i[3:0] Yes Yes T1,T3,T5 Yes T1,T2,T13 INPUT
cio_test_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
cio_test_en_o[7:0] Yes Yes T1,T19,T7 Yes T1,T10,T11 OUTPUT

*Tests covering at least one bit in the range

Branch Coverage for Instance : tb.dut
Line No.TotalCoveredPercent
Branches 28 27 96.43
TERNARY 382 2 1 50.00
TERNARY 1439 2 2 100.00
TERNARY 1441 2 2 100.00
TERNARY 1443 2 2 100.00
IF 287 2 2 100.00
IF 308 2 2 100.00
IF 334 2 2 100.00
IF 341 2 2 100.00
IF 407 2 2 100.00
IF 448 2 2 100.00
IF 469 2 2 100.00
IF 472 2 2 100.00
IF 499 2 2 100.00
IF 991 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 382 ((reg2hw.direct_access_regwen.qe && (!reg2hw.direct_access_regwen.q))) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 1439 ((part_digest[Secret0Idx] != '0)) ?

Branches:
-1-StatusTests
1 Covered T9,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 1441 ((part_digest[Secret2Idx] != '0)) ?

Branches:
-1-StatusTests
1 Covered T9,T4,T18
0 Covered T1,T2,T3


LineNo. Expression -1-: 1443 ((part_digest[Secret2Idx] != '0)) ?

Branches:
-1-StatusTests
1 Covered T9,T4,T18
0 Covered T1,T2,T3


LineNo. Expression -1-: 287 if (tlul_req) -2-: 288 if ((tlul_part_sel_oh != '0))

Branches:
-1--2-StatusTestsExclude Annotation
1 1 Covered T1,T2,T3
1 0 Excluded VC_COV_UNR
0 - Covered T1,T2,T3


LineNo. Expression -1-: 308 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 334 if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_creator_seed_sw_rw_en))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 341 if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_owner_seed_sw_rw_en))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 407 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 448 if (otp_ctrl_part_pkg::PartInfo[k].integrity)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 469 if ((fatal_macro_error_q || fatal_check_error_q))

Branches:
-1-StatusTests
1 Covered T2,T3,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 472 if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_escalate_en[k]))

Branches:
-1-StatusTests
1 Covered T2,T3,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 499 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 991 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 71 71 100.00 69 97.18
Cover properties 0 0 0
Cover sequences 0 0 0
Total 71 71 100.00 69 97.18




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertTxKnown_A 442410951 441597661 0 0
CoreTlOutKnown_A 442410951 441597661 0 0
CreatorRootKeyShare0Size_A 1153 1153 0 0
CreatorRootKeyShare1Size_A 1153 1153 0 0
ErrorCodeWidth_A 1153 1153 0 0
FlashAddrKeySeedSize_A 1153 1153 0 0
FlashDataKeySeedSize_A 1153 1153 0 0
FlashOtpKeyRspKnown_A 442410951 441597661 0 0
FpvSecCmCntCnstyCheck_A 442410951 50 0 0
FpvSecCmCntDaiCheck_A 442410951 50 0 0
FpvSecCmCntIntegCheck_A 442410951 50 0 0
FpvSecCmCntKdiEntropyCheck_A 442410951 50 0 0
FpvSecCmCntKdiSeedCheck_A 442410951 50 0 0
FpvSecCmCntLciCheck_A 442410951 50 0 0
FpvSecCmCntScrmblCheck_A 442410951 50 0 0
FpvSecCmCtrlDaiFsmCheck_A 442410951 50 0 0
FpvSecCmCtrlKdiFsmCheck_A 442410951 50 0 0
FpvSecCmCtrlLciFsmCheck_A 442410951 50 0 0
FpvSecCmCtrlLfsrTimerFsmCheck_A 442410951 50 0 0
FpvSecCmCtrlScrambleFsmCheck_A 442410951 50 0 0
FpvSecCmDoubleLfsrCheck_A 442410951 50 0 0
FpvSecCmRegWeOnehotCheck_A 442410951 50 0 0
FpvSecCmTlLcGateFsm_A 442410951 50 0 0
IntrOtpErrorKnown_A 442410951 441597661 0 0
IntrOtpOperationDoneKnown_A 442410951 441597661 0 0
LcOtpProgramRspKnown_A 442410951 441597661 0 0
LcSeedHwRdEnStable0_A 442410951 1882 0 0
LcSeedHwRdEnStable1_A 442410951 1882 0 0
LcSeedHwRdEnStable2_A 442410951 0 0 0
LcSeedHwRdEnStable3_A 442410951 0 0 0
LcStateSize_A 1153 1153 0 0
LcTransitionCntSize_A 1153 1153 0 0
OtpAstPwrSeqKnown_A 442410951 441597661 0 0
OtpBroadcastKnown_A 442410951 441597661 0 0
OtpErrorCode0_A 1153 1153 0 0
OtpErrorCode1_A 1153 1153 0 0
OtpErrorCode2_A 1153 1153 0 0
OtpErrorCode3_A 1153 1153 0 0
OtpErrorCode4_A 1153 1153 0 0
OtpIfWidth_A 1153 1153 0 0
OtpKeymgrKeyKnown_A 442410951 441597661 0 0
OtpLcDataKnown_A 442410951 441597661 0 0
OtpOtgnKeyKnown_A 442410951 441597661 0 0
OtpRespFifoUnderflow_A 442410951 1324421 0 0
OtpSramKeyKnown_A 442410951 441597661 0 0
PartSelMustBeOnehot_A 442410951 441597661 0 0
PrimTlOutKnown_A 442410951 441597661 0 0
PwrOtpInitRspKnown_A 442410951 441597661 0 0
RmaTokenSize_A 1153 1153 0 0
SramDataKeySeedSize_A 1153 1153 0 0
TestExitTokenSize_A 1153 1153 0 0
TestUnlockTokenSize_A 1153 1153 0 0
gen_partitions[0].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A 442410951 50 0 0
gen_partitions[10].gen_lifecycle.FpvSecCmCntPartLcCheck_A 442410951 50 0 0
gen_partitions[10].gen_lifecycle.FpvSecCmCtrlPartLcFsmCheck_A 442410951 50 0 0
gen_partitions[1].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A 442410951 50 0 0
gen_partitions[2].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A 442410951 50 0 0
gen_partitions[3].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A 442410951 50 0 0
gen_partitions[4].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A 442410951 50 0 0
gen_partitions[5].gen_buffered.FpvSecCmCntPartBufCheck_A 442410951 50 0 0
gen_partitions[5].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A 442410951 50 0 0
gen_partitions[6].gen_buffered.FpvSecCmCntPartBufCheck_A 442410951 50 0 0
gen_partitions[6].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A 442410951 50 0 0
gen_partitions[7].gen_buffered.FpvSecCmCntPartBufCheck_A 442410951 50 0 0
gen_partitions[7].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A 442410951 50 0 0
gen_partitions[8].gen_buffered.FpvSecCmCntPartBufCheck_A 442410951 50 0 0
gen_partitions[8].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A 442410951 50 0 0
gen_partitions[9].gen_buffered.FpvSecCmCntPartBufCheck_A 442410951 50 0 0
gen_partitions[9].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A 442410951 50 0 0
gen_reg_we_assert_generic.FpvSecCmPrimFsmCheck_A 442410951 50 0 0
gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A 442410951 50 0 0


AlertTxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 441597661 0 0
T1 27746 27237 0 0
T2 8495 8216 0 0
T3 11001 10780 0 0
T4 39533 39049 0 0
T9 13971 13711 0 0
T10 4853 4777 0 0
T11 10429 10352 0 0
T12 16443 16188 0 0
T13 10573 10360 0 0
T14 4734 4666 0 0

CoreTlOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 441597661 0 0
T1 27746 27237 0 0
T2 8495 8216 0 0
T3 11001 10780 0 0
T4 39533 39049 0 0
T9 13971 13711 0 0
T10 4853 4777 0 0
T11 10429 10352 0 0
T12 16443 16188 0 0
T13 10573 10360 0 0
T14 4734 4666 0 0

CreatorRootKeyShare0Size_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1153 1153 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0

CreatorRootKeyShare1Size_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1153 1153 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0

ErrorCodeWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1153 1153 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0

FlashAddrKeySeedSize_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1153 1153 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0

FlashDataKeySeedSize_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1153 1153 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0

FlashOtpKeyRspKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 441597661 0 0
T1 27746 27237 0 0
T2 8495 8216 0 0
T3 11001 10780 0 0
T4 39533 39049 0 0
T9 13971 13711 0 0
T10 4853 4777 0 0
T11 10429 10352 0 0
T12 16443 16188 0 0
T13 10573 10360 0 0
T14 4734 4666 0 0

FpvSecCmCntCnstyCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

FpvSecCmCntDaiCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

FpvSecCmCntIntegCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

FpvSecCmCntKdiEntropyCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

FpvSecCmCntKdiSeedCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

FpvSecCmCntLciCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

FpvSecCmCntScrmblCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

FpvSecCmCtrlDaiFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

FpvSecCmCtrlKdiFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

FpvSecCmCtrlLciFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

FpvSecCmCtrlLfsrTimerFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

FpvSecCmCtrlScrambleFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

FpvSecCmDoubleLfsrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

FpvSecCmTlLcGateFsm_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

IntrOtpErrorKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 441597661 0 0
T1 27746 27237 0 0
T2 8495 8216 0 0
T3 11001 10780 0 0
T4 39533 39049 0 0
T9 13971 13711 0 0
T10 4853 4777 0 0
T11 10429 10352 0 0
T12 16443 16188 0 0
T13 10573 10360 0 0
T14 4734 4666 0 0

IntrOtpOperationDoneKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 441597661 0 0
T1 27746 27237 0 0
T2 8495 8216 0 0
T3 11001 10780 0 0
T4 39533 39049 0 0
T9 13971 13711 0 0
T10 4853 4777 0 0
T11 10429 10352 0 0
T12 16443 16188 0 0
T13 10573 10360 0 0
T14 4734 4666 0 0

LcOtpProgramRspKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 441597661 0 0
T1 27746 27237 0 0
T2 8495 8216 0 0
T3 11001 10780 0 0
T4 39533 39049 0 0
T9 13971 13711 0 0
T10 4853 4777 0 0
T11 10429 10352 0 0
T12 16443 16188 0 0
T13 10573 10360 0 0
T14 4734 4666 0 0

LcSeedHwRdEnStable0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 1882 0 0
T4 39533 1 0 0
T5 18478 0 0 0
T9 13971 1 0 0
T12 16443 0 0 0
T13 10573 0 0 0
T14 4734 0 0 0
T18 135070 10 0 0
T19 0 3 0 0
T41 0 13 0 0
T45 20422 2 0 0
T51 11783 0 0 0
T99 0 8 0 0
T108 0 1 0 0
T116 0 1 0 0
T117 0 1 0 0
T118 10705 0 0 0

LcSeedHwRdEnStable1_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 1882 0 0
T4 39533 1 0 0
T5 18478 0 0 0
T9 13971 1 0 0
T12 16443 0 0 0
T13 10573 0 0 0
T14 4734 0 0 0
T18 135070 10 0 0
T19 0 3 0 0
T41 0 13 0 0
T45 20422 2 0 0
T51 11783 0 0 0
T99 0 8 0 0
T108 0 1 0 0
T116 0 1 0 0
T117 0 1 0 0
T118 10705 0 0 0

LcSeedHwRdEnStable2_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 0 0 0

LcSeedHwRdEnStable3_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 0 0 0

LcStateSize_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1153 1153 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0

LcTransitionCntSize_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1153 1153 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0

OtpAstPwrSeqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 441597661 0 0
T1 27746 27237 0 0
T2 8495 8216 0 0
T3 11001 10780 0 0
T4 39533 39049 0 0
T9 13971 13711 0 0
T10 4853 4777 0 0
T11 10429 10352 0 0
T12 16443 16188 0 0
T13 10573 10360 0 0
T14 4734 4666 0 0

OtpBroadcastKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 441597661 0 0
T1 27746 27237 0 0
T2 8495 8216 0 0
T3 11001 10780 0 0
T4 39533 39049 0 0
T9 13971 13711 0 0
T10 4853 4777 0 0
T11 10429 10352 0 0
T12 16443 16188 0 0
T13 10573 10360 0 0
T14 4734 4666 0 0

OtpErrorCode0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1153 1153 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0

OtpErrorCode1_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1153 1153 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0

OtpErrorCode2_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1153 1153 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0

OtpErrorCode3_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1153 1153 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0

OtpErrorCode4_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1153 1153 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0

OtpIfWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1153 1153 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0

OtpKeymgrKeyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 441597661 0 0
T1 27746 27237 0 0
T2 8495 8216 0 0
T3 11001 10780 0 0
T4 39533 39049 0 0
T9 13971 13711 0 0
T10 4853 4777 0 0
T11 10429 10352 0 0
T12 16443 16188 0 0
T13 10573 10360 0 0
T14 4734 4666 0 0

OtpLcDataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 441597661 0 0
T1 27746 27237 0 0
T2 8495 8216 0 0
T3 11001 10780 0 0
T4 39533 39049 0 0
T9 13971 13711 0 0
T10 4853 4777 0 0
T11 10429 10352 0 0
T12 16443 16188 0 0
T13 10573 10360 0 0
T14 4734 4666 0 0

OtpOtgnKeyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 441597661 0 0
T1 27746 27237 0 0
T2 8495 8216 0 0
T3 11001 10780 0 0
T4 39533 39049 0 0
T9 13971 13711 0 0
T10 4853 4777 0 0
T11 10429 10352 0 0
T12 16443 16188 0 0
T13 10573 10360 0 0
T14 4734 4666 0 0

OtpRespFifoUnderflow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 1324421 0 0
T1 27746 462 0 0
T2 8495 109 0 0
T3 11001 141 0 0
T4 39533 475 0 0
T9 13971 268 0 0
T10 4853 55 0 0
T11 10429 55 0 0
T12 16443 223 0 0
T13 10573 129 0 0
T14 4734 55 0 0

OtpSramKeyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 441597661 0 0
T1 27746 27237 0 0
T2 8495 8216 0 0
T3 11001 10780 0 0
T4 39533 39049 0 0
T9 13971 13711 0 0
T10 4853 4777 0 0
T11 10429 10352 0 0
T12 16443 16188 0 0
T13 10573 10360 0 0
T14 4734 4666 0 0

PartSelMustBeOnehot_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 441597661 0 0
T1 27746 27237 0 0
T2 8495 8216 0 0
T3 11001 10780 0 0
T4 39533 39049 0 0
T9 13971 13711 0 0
T10 4853 4777 0 0
T11 10429 10352 0 0
T12 16443 16188 0 0
T13 10573 10360 0 0
T14 4734 4666 0 0

PrimTlOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 441597661 0 0
T1 27746 27237 0 0
T2 8495 8216 0 0
T3 11001 10780 0 0
T4 39533 39049 0 0
T9 13971 13711 0 0
T10 4853 4777 0 0
T11 10429 10352 0 0
T12 16443 16188 0 0
T13 10573 10360 0 0
T14 4734 4666 0 0

PwrOtpInitRspKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 441597661 0 0
T1 27746 27237 0 0
T2 8495 8216 0 0
T3 11001 10780 0 0
T4 39533 39049 0 0
T9 13971 13711 0 0
T10 4853 4777 0 0
T11 10429 10352 0 0
T12 16443 16188 0 0
T13 10573 10360 0 0
T14 4734 4666 0 0

RmaTokenSize_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1153 1153 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0

SramDataKeySeedSize_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1153 1153 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0

TestExitTokenSize_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1153 1153 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0

TestUnlockTokenSize_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1153 1153 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0

gen_partitions[0].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

gen_partitions[10].gen_lifecycle.FpvSecCmCntPartLcCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

gen_partitions[10].gen_lifecycle.FpvSecCmCtrlPartLcFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

gen_partitions[1].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

gen_partitions[2].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

gen_partitions[3].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

gen_partitions[4].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

gen_partitions[5].gen_buffered.FpvSecCmCntPartBufCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

gen_partitions[5].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

gen_partitions[6].gen_buffered.FpvSecCmCntPartBufCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

gen_partitions[6].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

gen_partitions[7].gen_buffered.FpvSecCmCntPartBufCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

gen_partitions[7].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

gen_partitions[8].gen_buffered.FpvSecCmCntPartBufCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

gen_partitions[8].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

gen_partitions[9].gen_buffered.FpvSecCmCntPartBufCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

gen_partitions[9].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

gen_reg_we_assert_generic.FpvSecCmPrimFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442410951 50 0 0
T26 108879 10 0 0
T27 0 10 0 0
T28 0 10 0 0
T119 71196 0 0 0
T160 280948 0 0 0
T227 8442 0 0 0
T258 0 10 0 0
T259 0 10 0 0
T260 21791 0 0 0
T261 12725 0 0 0
T262 6995 0 0 0
T263 30973 0 0 0
T264 12236 0 0 0
T265 16105 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%