Line Coverage for Module :
otp_ctrl_part_unbuf ( parameter Info=65616,DigestOffset=56,StateWidth=10 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 93 | 86 | 92.47 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
ALWAYS | 153 | 3 | 3 | 100.00 |
ALWAYS | 164 | 68 | 61 | 89.71 |
CONT_ASSIGN | 334 | 1 | 1 | 100.00 |
CONT_ASSIGN | 336 | 1 | 1 | 100.00 |
CONT_ASSIGN | 339 | 1 | 1 | 100.00 |
CONT_ASSIGN | 349 | 1 | 1 | 100.00 |
CONT_ASSIGN | 350 | 1 | 1 | 100.00 |
CONT_ASSIGN | 354 | 1 | 1 | 100.00 |
CONT_ASSIGN | 358 | 1 | 1 | 100.00 |
CONT_ASSIGN | 395 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 454 | 1 | 1 | 100.00 |
ALWAYS | 461 | 3 | 3 | 100.00 |
ALWAYS | 464 | 8 | 8 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
138 |
1 |
1 |
153 |
1 |
1 |
154 |
1 |
1 |
156 |
1 |
1 |
164 |
1 |
1 |
167 |
1 |
1 |
170 |
1 |
1 |
171 |
1 |
1 |
174 |
1 |
1 |
175 |
1 |
1 |
176 |
1 |
1 |
179 |
1 |
1 |
182 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
186 |
1 |
1 |
191 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
196 |
|
unreachable |
|
|
|
MISSING_ELSE |
205 |
1 |
1 |
206 |
1 |
1 |
207 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
215 |
1 |
1 |
216 |
1 |
1 |
217 |
1 |
1 |
218 |
1 |
1 |
220 |
1 |
1 |
221 |
0 |
1 |
|
|
|
MISSING_ELSE |
224 |
0 |
1 |
225 |
0 |
1 |
|
|
|
MISSING_ELSE |
233 |
1 |
1 |
234 |
1 |
1 |
235 |
1 |
1 |
236 |
1 |
1 |
237 |
1 |
1 |
|
|
|
MISSING_ELSE |
246 |
1 |
1 |
248 |
1 |
1 |
249 |
1 |
1 |
250 |
1 |
1 |
251 |
1 |
1 |
252 |
1 |
1 |
|
|
|
MISSING_ELSE |
255 |
1 |
1 |
256 |
1 |
1 |
257 |
1 |
1 |
258 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
268 |
1 |
1 |
269 |
1 |
1 |
270 |
1 |
1 |
272 |
1 |
1 |
273 |
0 |
1 |
|
|
|
MISSING_ELSE |
276 |
0 |
1 |
277 |
0 |
1 |
279 |
0 |
1 |
|
|
|
MISSING_ELSE |
288 |
1 |
1 |
289 |
1 |
1 |
|
|
|
MISSING_ELSE |
293 |
1 |
1 |
294 |
1 |
1 |
295 |
1 |
1 |
296 |
1 |
1 |
297 |
1 |
1 |
298 |
1 |
1 |
|
|
|
MISSING_ELSE |
314 |
1 |
1 |
315 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
|
|
|
MISSING_ELSE |
|
|
|
MISSING_ELSE |
321 |
1 |
1 |
322 |
1 |
1 |
323 |
1 |
1 |
324 |
1 |
1 |
325 |
1 |
1 |
|
|
|
MISSING_ELSE |
|
|
|
MISSING_ELSE |
334 |
1 |
1 |
336 |
1 |
1 |
339 |
1 |
1 |
349 |
1 |
1 |
350 |
1 |
1 |
354 |
1 |
1 |
358 |
1 |
1 |
395 |
1 |
1 |
420 |
1 |
1 |
454 |
1 |
1 |
461 |
3 |
3 |
464 |
1 |
1 |
465 |
1 |
1 |
466 |
1 |
1 |
467 |
1 |
1 |
469 |
1 |
1 |
470 |
1 |
1 |
471 |
1 |
1 |
472 |
1 |
1 |
|
|
|
MISSING_ELSE |
Line Coverage for Module :
otp_ctrl_part_unbuf ( parameter Info=134635604,DigestOffset=464,StateWidth=10 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 91 | 91 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
ALWAYS | 164 | 68 | 68 | 100.00 |
CONT_ASSIGN | 334 | 1 | 1 | 100.00 |
CONT_ASSIGN | 336 | 1 | 1 | 100.00 |
CONT_ASSIGN | 342 | 1 | 1 | 100.00 |
CONT_ASSIGN | 349 | 1 | 1 | 100.00 |
CONT_ASSIGN | 350 | 1 | 1 | 100.00 |
CONT_ASSIGN | 354 | 1 | 1 | 100.00 |
CONT_ASSIGN | 358 | 1 | 1 | 100.00 |
CONT_ASSIGN | 395 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 454 | 1 | 1 | 100.00 |
ALWAYS | 461 | 3 | 3 | 100.00 |
ALWAYS | 464 | 8 | 8 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
138 |
1 |
1 |
149 |
1 |
1 |
164 |
1 |
1 |
167 |
1 |
1 |
170 |
1 |
1 |
171 |
1 |
1 |
174 |
1 |
1 |
175 |
1 |
1 |
176 |
1 |
1 |
179 |
1 |
1 |
182 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
186 |
1 |
1 |
191 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
196 |
|
unreachable |
|
|
|
MISSING_ELSE |
205 |
1 |
1 |
206 |
1 |
1 |
207 |
1 |
1 |
|
|
|
MISSING_ELSE |
215 |
1 |
1 |
216 |
1 |
1 |
217 |
1 |
1 |
218 |
1 |
1 |
220 |
1 |
1 |
221 |
1 |
1 |
|
|
|
MISSING_ELSE |
224 |
1 |
1 |
225 |
1 |
1 |
|
|
|
MISSING_ELSE |
233 |
1 |
1 |
234 |
1 |
1 |
235 |
1 |
1 |
236 |
1 |
1 |
237 |
1 |
1 |
|
|
|
MISSING_ELSE |
246 |
1 |
1 |
248 |
1 |
1 |
249 |
1 |
1 |
250 |
1 |
1 |
251 |
1 |
1 |
252 |
1 |
1 |
|
|
|
MISSING_ELSE |
255 |
1 |
1 |
256 |
1 |
1 |
257 |
1 |
1 |
258 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
268 |
1 |
1 |
269 |
1 |
1 |
270 |
1 |
1 |
272 |
1 |
1 |
273 |
1 |
1 |
|
|
|
MISSING_ELSE |
276 |
1 |
1 |
277 |
1 |
1 |
279 |
1 |
1 |
|
|
|
MISSING_ELSE |
288 |
1 |
1 |
289 |
1 |
1 |
|
|
|
MISSING_ELSE |
293 |
1 |
1 |
294 |
1 |
1 |
295 |
1 |
1 |
296 |
1 |
1 |
297 |
1 |
1 |
298 |
1 |
1 |
|
|
|
MISSING_ELSE |
314 |
1 |
1 |
315 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
|
|
|
MISSING_ELSE |
|
|
|
MISSING_ELSE |
321 |
1 |
1 |
322 |
1 |
1 |
323 |
1 |
1 |
324 |
1 |
1 |
325 |
1 |
1 |
|
|
|
MISSING_ELSE |
|
|
|
MISSING_ELSE |
334 |
1 |
1 |
336 |
1 |
1 |
342 |
1 |
1 |
349 |
1 |
1 |
350 |
1 |
1 |
354 |
1 |
1 |
358 |
1 |
1 |
395 |
1 |
1 |
420 |
1 |
1 |
454 |
1 |
1 |
461 |
3 |
3 |
464 |
1 |
1 |
465 |
1 |
1 |
466 |
1 |
1 |
467 |
1 |
1 |
469 |
1 |
1 |
470 |
1 |
1 |
471 |
1 |
1 |
472 |
1 |
1 |
|
|
|
MISSING_ELSE |
Line Coverage for Module :
otp_ctrl_part_unbuf ( parameter Info=990543956,DigestOffset=1136,StateWidth=10 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 91 | 91 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
ALWAYS | 164 | 68 | 68 | 100.00 |
CONT_ASSIGN | 334 | 1 | 1 | 100.00 |
CONT_ASSIGN | 336 | 1 | 1 | 100.00 |
CONT_ASSIGN | 342 | 1 | 1 | 100.00 |
CONT_ASSIGN | 349 | 1 | 1 | 100.00 |
CONT_ASSIGN | 350 | 1 | 1 | 100.00 |
CONT_ASSIGN | 354 | 1 | 1 | 100.00 |
CONT_ASSIGN | 358 | 1 | 1 | 100.00 |
CONT_ASSIGN | 395 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 454 | 1 | 1 | 100.00 |
ALWAYS | 461 | 3 | 3 | 100.00 |
ALWAYS | 464 | 8 | 8 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
138 |
1 |
1 |
149 |
1 |
1 |
164 |
1 |
1 |
167 |
1 |
1 |
170 |
1 |
1 |
171 |
1 |
1 |
174 |
1 |
1 |
175 |
1 |
1 |
176 |
1 |
1 |
179 |
1 |
1 |
182 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
186 |
1 |
1 |
191 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
196 |
|
unreachable |
|
|
|
MISSING_ELSE |
205 |
1 |
1 |
206 |
1 |
1 |
207 |
1 |
1 |
|
|
|
MISSING_ELSE |
215 |
1 |
1 |
216 |
1 |
1 |
217 |
1 |
1 |
218 |
1 |
1 |
220 |
1 |
1 |
221 |
1 |
1 |
|
|
|
MISSING_ELSE |
224 |
1 |
1 |
225 |
1 |
1 |
|
|
|
MISSING_ELSE |
233 |
1 |
1 |
234 |
1 |
1 |
235 |
1 |
1 |
236 |
1 |
1 |
237 |
1 |
1 |
|
|
|
MISSING_ELSE |
246 |
1 |
1 |
248 |
1 |
1 |
249 |
1 |
1 |
250 |
1 |
1 |
251 |
1 |
1 |
252 |
1 |
1 |
|
|
|
MISSING_ELSE |
255 |
1 |
1 |
256 |
1 |
1 |
257 |
1 |
1 |
258 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
268 |
1 |
1 |
269 |
1 |
1 |
270 |
1 |
1 |
272 |
1 |
1 |
273 |
1 |
1 |
|
|
|
MISSING_ELSE |
276 |
1 |
1 |
277 |
1 |
1 |
279 |
1 |
1 |
|
|
|
MISSING_ELSE |
288 |
1 |
1 |
289 |
1 |
1 |
|
|
|
MISSING_ELSE |
293 |
1 |
1 |
294 |
1 |
1 |
295 |
1 |
1 |
296 |
1 |
1 |
297 |
1 |
1 |
298 |
1 |
1 |
|
|
|
MISSING_ELSE |
314 |
1 |
1 |
315 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
|
|
|
MISSING_ELSE |
|
|
|
MISSING_ELSE |
321 |
1 |
1 |
322 |
1 |
1 |
323 |
1 |
1 |
324 |
1 |
1 |
325 |
1 |
1 |
|
|
|
MISSING_ELSE |
|
|
|
MISSING_ELSE |
334 |
1 |
1 |
336 |
1 |
1 |
342 |
1 |
1 |
349 |
1 |
1 |
350 |
1 |
1 |
354 |
1 |
1 |
358 |
1 |
1 |
395 |
1 |
1 |
420 |
1 |
1 |
454 |
1 |
1 |
461 |
3 |
3 |
464 |
1 |
1 |
465 |
1 |
1 |
466 |
1 |
1 |
467 |
1 |
1 |
469 |
1 |
1 |
470 |
1 |
1 |
471 |
1 |
1 |
472 |
1 |
1 |
|
|
|
MISSING_ELSE |
Line Coverage for Module :
otp_ctrl_part_unbuf ( parameter Info=-1,DigestOffset=1608,StateWidth=10 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 91 | 91 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
ALWAYS | 164 | 68 | 68 | 100.00 |
CONT_ASSIGN | 334 | 1 | 1 | 100.00 |
CONT_ASSIGN | 336 | 1 | 1 | 100.00 |
CONT_ASSIGN | 342 | 1 | 1 | 100.00 |
CONT_ASSIGN | 349 | 1 | 1 | 100.00 |
CONT_ASSIGN | 350 | 1 | 1 | 100.00 |
CONT_ASSIGN | 354 | 1 | 1 | 100.00 |
CONT_ASSIGN | 358 | 1 | 1 | 100.00 |
CONT_ASSIGN | 395 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 454 | 1 | 1 | 100.00 |
ALWAYS | 461 | 3 | 3 | 100.00 |
ALWAYS | 464 | 8 | 8 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
138 |
1 |
1 |
149 |
1 |
1 |
164 |
1 |
1 |
167 |
1 |
1 |
170 |
1 |
1 |
171 |
1 |
1 |
174 |
1 |
1 |
175 |
1 |
1 |
176 |
1 |
1 |
179 |
1 |
1 |
182 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
186 |
1 |
1 |
191 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
196 |
|
unreachable |
|
|
|
MISSING_ELSE |
205 |
1 |
1 |
206 |
1 |
1 |
207 |
1 |
1 |
|
|
|
MISSING_ELSE |
215 |
1 |
1 |
216 |
1 |
1 |
217 |
1 |
1 |
218 |
1 |
1 |
220 |
1 |
1 |
221 |
1 |
1 |
|
|
|
MISSING_ELSE |
224 |
1 |
1 |
225 |
1 |
1 |
|
|
|
MISSING_ELSE |
233 |
1 |
1 |
234 |
1 |
1 |
235 |
1 |
1 |
236 |
1 |
1 |
237 |
1 |
1 |
|
|
|
MISSING_ELSE |
246 |
1 |
1 |
248 |
1 |
1 |
249 |
1 |
1 |
250 |
1 |
1 |
251 |
1 |
1 |
252 |
1 |
1 |
|
|
|
MISSING_ELSE |
255 |
1 |
1 |
256 |
1 |
1 |
257 |
1 |
1 |
258 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
268 |
1 |
1 |
269 |
1 |
1 |
270 |
1 |
1 |
272 |
1 |
1 |
273 |
1 |
1 |
|
|
|
MISSING_ELSE |
276 |
1 |
1 |
277 |
1 |
1 |
279 |
1 |
1 |
|
|
|
MISSING_ELSE |
288 |
1 |
1 |
289 |
1 |
1 |
|
|
|
MISSING_ELSE |
293 |
1 |
1 |
294 |
1 |
1 |
295 |
1 |
1 |
296 |
1 |
1 |
297 |
1 |
1 |
298 |
1 |
1 |
|
|
|
MISSING_ELSE |
314 |
1 |
1 |
315 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
|
|
|
MISSING_ELSE |
|
|
|
MISSING_ELSE |
321 |
1 |
1 |
322 |
1 |
1 |
323 |
1 |
1 |
324 |
1 |
1 |
325 |
1 |
1 |
|
|
|
MISSING_ELSE |
|
|
|
MISSING_ELSE |
334 |
1 |
1 |
336 |
1 |
1 |
342 |
1 |
1 |
349 |
1 |
1 |
350 |
1 |
1 |
354 |
1 |
1 |
358 |
1 |
1 |
395 |
1 |
1 |
420 |
1 |
1 |
454 |
1 |
1 |
461 |
3 |
3 |
464 |
1 |
1 |
465 |
1 |
1 |
466 |
1 |
1 |
467 |
1 |
1 |
469 |
1 |
1 |
470 |
1 |
1 |
471 |
1 |
1 |
472 |
1 |
1 |
|
|
|
MISSING_ELSE |
Line Coverage for Module :
otp_ctrl_part_unbuf ( parameter Info=-1,DigestOffset=1648,StateWidth=10 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 91 | 91 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
ALWAYS | 164 | 68 | 68 | 100.00 |
CONT_ASSIGN | 334 | 1 | 1 | 100.00 |
CONT_ASSIGN | 336 | 1 | 1 | 100.00 |
CONT_ASSIGN | 342 | 1 | 1 | 100.00 |
CONT_ASSIGN | 349 | 1 | 1 | 100.00 |
CONT_ASSIGN | 350 | 1 | 1 | 100.00 |
CONT_ASSIGN | 354 | 1 | 1 | 100.00 |
CONT_ASSIGN | 358 | 1 | 1 | 100.00 |
CONT_ASSIGN | 395 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 454 | 1 | 1 | 100.00 |
ALWAYS | 461 | 3 | 3 | 100.00 |
ALWAYS | 464 | 8 | 8 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
138 |
1 |
1 |
149 |
1 |
1 |
164 |
1 |
1 |
167 |
1 |
1 |
170 |
1 |
1 |
171 |
1 |
1 |
174 |
1 |
1 |
175 |
1 |
1 |
176 |
1 |
1 |
179 |
1 |
1 |
182 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
186 |
1 |
1 |
191 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
196 |
|
unreachable |
|
|
|
MISSING_ELSE |
205 |
1 |
1 |
206 |
1 |
1 |
207 |
1 |
1 |
|
|
|
MISSING_ELSE |
215 |
1 |
1 |
216 |
1 |
1 |
217 |
1 |
1 |
218 |
1 |
1 |
220 |
1 |
1 |
221 |
1 |
1 |
|
|
|
MISSING_ELSE |
224 |
1 |
1 |
225 |
1 |
1 |
|
|
|
MISSING_ELSE |
233 |
1 |
1 |
234 |
1 |
1 |
235 |
1 |
1 |
236 |
1 |
1 |
237 |
1 |
1 |
|
|
|
MISSING_ELSE |
246 |
1 |
1 |
248 |
1 |
1 |
249 |
1 |
1 |
250 |
1 |
1 |
251 |
1 |
1 |
252 |
1 |
1 |
|
|
|
MISSING_ELSE |
255 |
1 |
1 |
256 |
1 |
1 |
257 |
1 |
1 |
258 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
268 |
1 |
1 |
269 |
1 |
1 |
270 |
1 |
1 |
272 |
1 |
1 |
273 |
1 |
1 |
|
|
|
MISSING_ELSE |
276 |
1 |
1 |
277 |
1 |
1 |
279 |
1 |
1 |
|
|
|
MISSING_ELSE |
288 |
1 |
1 |
289 |
1 |
1 |
|
|
|
MISSING_ELSE |
293 |
1 |
1 |
294 |
1 |
1 |
295 |
1 |
1 |
296 |
1 |
1 |
297 |
1 |
1 |
298 |
1 |
1 |
|
|
|
MISSING_ELSE |
314 |
1 |
1 |
315 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
|
|
|
MISSING_ELSE |
|
|
|
MISSING_ELSE |
321 |
1 |
1 |
322 |
1 |
1 |
323 |
1 |
1 |
324 |
1 |
1 |
325 |
1 |
1 |
|
|
|
MISSING_ELSE |
|
|
|
MISSING_ELSE |
334 |
1 |
1 |
336 |
1 |
1 |
342 |
1 |
1 |
349 |
1 |
1 |
350 |
1 |
1 |
354 |
1 |
1 |
358 |
1 |
1 |
395 |
1 |
1 |
420 |
1 |
1 |
454 |
1 |
1 |
461 |
3 |
3 |
464 |
1 |
1 |
465 |
1 |
1 |
466 |
1 |
1 |
467 |
1 |
1 |
469 |
1 |
1 |
470 |
1 |
1 |
471 |
1 |
1 |
472 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Module :
otp_ctrl_part_unbuf ( parameter Info=-1,DigestOffset=1608,StateWidth=10 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 34 | 33 | 97.06 |
Logical | 34 | 33 | 97.06 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 220
EXPRESSION (otp_err != NoError)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T93,T39,T75 |
LINE 272
EXPRESSION (otp_err != NoError)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T183,T72,T185 |
LINE 288
EXPRESSION (error_q == NoError)
----------1---------
-1- | Status | Tests |
0 | Covered | T2,T3,T9 |
1 | Covered | T26,T27,T28 |
LINE 316
EXPRESSION (state_q != ErrorSt)
----------1---------
-1- | Status | Tests |
0 | Covered | T186,T187,T188 |
1 | Covered | T186,T187,T188 |
LINE 324
EXPRESSION (state_q != ErrorSt)
----------1---------
-1- | Status | Tests |
0 | Covered | T2,T3,T9 |
1 | Covered | T2,T3,T9 |
LINE 336
EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 336
SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
------1------ ----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T18,T19 |
1 | 1 | Covered | T1,T2,T3 |
LINE 336
SUB-EXPRESSION (tlul_rerror_o == '0)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 342
EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b10001111000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
--------------------1------------------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 349
EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
---------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 349
SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
---------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 358
EXPRESSION
Number Term
1 (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 358
SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
---------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 395
EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 420
EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T18,T19 |
LINE 420
SUB-EXPRESSION (digest_o != '0)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T18,T19 |
Cond Coverage for Module :
otp_ctrl_part_unbuf ( parameter Info=65616,DigestOffset=56,StateWidth=10 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 31 | 29 | 93.55 |
Logical | 31 | 29 | 93.55 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 220
EXPRESSION (otp_err != NoError)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 272
EXPRESSION (otp_err != NoError)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 288
EXPRESSION (error_q == NoError)
----------1---------
-1- | Status | Tests |
0 | Covered | T2,T3,T9 |
1 | Covered | T26,T27,T28 |
LINE 316
EXPRESSION (state_q != ErrorSt)
----------1---------
-1- | Status | Tests |
0 | Covered | T176,T177,T189 |
1 | Covered | T176,T177,T189 |
LINE 324
EXPRESSION (state_q != ErrorSt)
----------1---------
-1- | Status | Tests |
0 | Covered | T2,T3,T9 |
1 | Covered | T2,T3,T9 |
LINE 336
EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 336
SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
------1------ ----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T18,T19 |
1 | 1 | Covered | T1,T2,T3 |
LINE 336
SUB-EXPRESSION (tlul_rerror_o == '0)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 349
EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
---------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 349
SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
---------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 358
EXPRESSION
Number Term
1 (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 358
SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
---------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 395
EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 420
EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T13 |
LINE 420
SUB-EXPRESSION (digest_o != '0)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T13 |
Cond Coverage for Module :
otp_ctrl_part_unbuf ( parameter Info=134635604,DigestOffset=464,StateWidth=10 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 34 | 33 | 97.06 |
Logical | 34 | 33 | 97.06 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 220
EXPRESSION (otp_err != NoError)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T112,T109,T190 |
LINE 272
EXPRESSION (otp_err != NoError)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T105,T183,T72 |
LINE 288
EXPRESSION (error_q == NoError)
----------1---------
-1- | Status | Tests |
0 | Covered | T2,T3,T9 |
1 | Covered | T26,T27,T28 |
LINE 316
EXPRESSION (state_q != ErrorSt)
----------1---------
-1- | Status | Tests |
0 | Covered | T176,T177,T191 |
1 | Covered | T176,T177,T191 |
LINE 324
EXPRESSION (state_q != ErrorSt)
----------1---------
-1- | Status | Tests |
0 | Covered | T2,T3,T9 |
1 | Covered | T2,T3,T9 |
LINE 336
EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 336
SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
------1------ ----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T18,T19,T6 |
1 | 1 | Covered | T1,T2,T3 |
LINE 336
SUB-EXPRESSION (tlul_rerror_o == '0)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 342
EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
--------------------1------------------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 349
EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
---------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 349
SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
---------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 358
EXPRESSION
Number Term
1 (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 358
SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
---------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 395
EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 420
EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T13,T5 |
LINE 420
SUB-EXPRESSION (digest_o != '0)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T13,T5 |
Cond Coverage for Module :
otp_ctrl_part_unbuf ( parameter Info=-1,DigestOffset=1648,StateWidth=10 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 34 | 33 | 97.06 |
Logical | 34 | 33 | 97.06 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 220
EXPRESSION (otp_err != NoError)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T46,T192 |
LINE 272
EXPRESSION (otp_err != NoError)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T106,T56,T193 |
LINE 288
EXPRESSION (error_q == NoError)
----------1---------
-1- | Status | Tests |
0 | Covered | T2,T3,T9 |
1 | Covered | T26,T27,T28 |
LINE 316
EXPRESSION (state_q != ErrorSt)
----------1---------
-1- | Status | Tests |
0 | Covered | T2,T191,T187 |
1 | Covered | T2,T191,T187 |
LINE 324
EXPRESSION (state_q != ErrorSt)
----------1---------
-1- | Status | Tests |
0 | Covered | T2,T3,T9 |
1 | Covered | T3,T9,T12 |
LINE 336
EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 336
SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
------1------ ----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T18,T6,T73 |
1 | 1 | Covered | T1,T2,T3 |
LINE 336
SUB-EXPRESSION (tlul_rerror_o == '0)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 342
EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b11001010000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
--------------------1------------------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 349
EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
---------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 349
SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
---------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 358
EXPRESSION
Number Term
1 (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 358
SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
---------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 395
EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 420
EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T18,T55 |
LINE 420
SUB-EXPRESSION (digest_o != '0)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T18,T55 |
Cond Coverage for Module :
otp_ctrl_part_unbuf ( parameter Info=990543956,DigestOffset=1136,StateWidth=10 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 34 | 33 | 97.06 |
Logical | 34 | 33 | 97.06 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 220
EXPRESSION (otp_err != NoError)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T93,T194 |
LINE 272
EXPRESSION (otp_err != NoError)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T106,T185,T33 |
LINE 288
EXPRESSION (error_q == NoError)
----------1---------
-1- | Status | Tests |
0 | Covered | T2,T3,T9 |
1 | Covered | T26,T27,T28 |
LINE 316
EXPRESSION (state_q != ErrorSt)
----------1---------
-1- | Status | Tests |
0 | Covered | T176,T177,T186 |
1 | Covered | T176,T177,T186 |
LINE 324
EXPRESSION (state_q != ErrorSt)
----------1---------
-1- | Status | Tests |
0 | Covered | T2,T3,T9 |
1 | Covered | T2,T3,T9 |
LINE 336
EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 336
SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
------1------ ----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T18,T6 |
1 | 1 | Covered | T1,T2,T3 |
LINE 336
SUB-EXPRESSION (tlul_rerror_o == '0)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 342
EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00111011000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
--------------------1------------------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 349
EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
---------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 349
SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
---------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 358
EXPRESSION
Number Term
1 (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 358
SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
---------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 395
EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 420
EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T118,T19 |
LINE 420
SUB-EXPRESSION (digest_o != '0)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T118,T19 |
FSM Coverage for Module :
otp_ctrl_part_unbuf
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
7 |
7 |
100.00 |
(Not included in score) |
Transitions |
14 |
12 |
85.71 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
ErrorSt |
224 |
Covered |
T2,T3,T9 |
IdleSt |
196 |
Covered |
T1,T2,T3 |
InitSt |
194 |
Covered |
T1,T2,T3 |
InitWaitSt |
207 |
Covered |
T1,T2,T3 |
ReadSt |
236 |
Covered |
T1,T2,T3 |
ReadWaitSt |
252 |
Covered |
T1,T2,T3 |
ResetSt |
190 |
Covered |
T1,T2,T3 |
transitions | Line No. | Covered | Tests |
IdleSt->ErrorSt |
315 |
Covered |
T3,T9,T12 |
IdleSt->ReadSt |
236 |
Covered |
T1,T2,T3 |
InitSt->ErrorSt |
315 |
Covered |
T13,T118,T123 |
InitSt->InitWaitSt |
207 |
Covered |
T1,T2,T3 |
InitWaitSt->ErrorSt |
224 |
Covered |
T13,T118,T123 |
InitWaitSt->IdleSt |
218 |
Covered |
T1,T2,T3 |
ReadSt->ErrorSt |
315 |
Not Covered |
|
ReadSt->IdleSt |
255 |
Covered |
T1,T18,T19 |
ReadSt->ReadWaitSt |
252 |
Covered |
T1,T2,T3 |
ReadWaitSt->ErrorSt |
276 |
Covered |
T183,T195,T196 |
ReadWaitSt->IdleSt |
270 |
Covered |
T1,T2,T3 |
ResetSt->ErrorSt |
315 |
Covered |
T2,T79,T80 |
ResetSt->IdleSt |
196 |
Not Covered |
|
ResetSt->InitSt |
194 |
Covered |
T1,T2,T3 |
Summary for FSM :: error_q
| Total | Covered | Percent | |
States |
5 |
5 |
100.00 |
(Not included in score) |
Transitions |
20 |
10 |
50.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: error_q
states | Line No. | Covered | Tests |
AccessError |
256 |
Covered |
T1,T18,T19 |
CheckFailError |
317 |
Covered |
T2,T176,T177 |
FsmStateError |
289 |
Covered |
T2,T3,T9 |
MacroEccCorrError |
221 |
Covered |
T3,T112,T105 |
NoError |
235 |
Covered |
T1,T2,T3 |
transitions | Line No. | Covered | Tests |
AccessError->CheckFailError |
317 |
Not Covered |
|
AccessError->FsmStateError |
325 |
Covered |
T7,T115,T104 |
AccessError->MacroEccCorrError |
221 |
Not Covered |
|
AccessError->NoError |
235 |
Covered |
T1,T18,T19 |
CheckFailError->AccessError |
256 |
Not Covered |
|
CheckFailError->FsmStateError |
325 |
Not Covered |
|
CheckFailError->MacroEccCorrError |
221 |
Not Covered |
|
CheckFailError->NoError |
235 |
Covered |
T2,T176,T177 |
FsmStateError->AccessError |
256 |
Not Covered |
|
FsmStateError->CheckFailError |
317 |
Not Covered |
|
FsmStateError->MacroEccCorrError |
221 |
Not Covered |
|
FsmStateError->NoError |
235 |
Covered |
T2,T3,T9 |
MacroEccCorrError->AccessError |
256 |
Not Covered |
|
MacroEccCorrError->CheckFailError |
317 |
Not Covered |
|
MacroEccCorrError->FsmStateError |
325 |
Covered |
T3,T112,T105 |
MacroEccCorrError->NoError |
235 |
Covered |
T106,T72,T185 |
NoError->AccessError |
256 |
Covered |
T1,T18,T19 |
NoError->CheckFailError |
317 |
Covered |
T2,T176,T177 |
NoError->FsmStateError |
289 |
Covered |
T2,T3,T9 |
NoError->MacroEccCorrError |
221 |
Covered |
T3,T112,T105 |
Branch Coverage for Module :
otp_ctrl_part_unbuf ( parameter Info=65616,DigestOffset=56,StateWidth=10 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
Branches |
|
46 |
41 |
89.13 |
TERNARY |
336 |
2 |
2 |
100.00 |
TERNARY |
349 |
2 |
2 |
100.00 |
TERNARY |
358 |
2 |
2 |
100.00 |
TERNARY |
395 |
2 |
2 |
100.00 |
TERNARY |
420 |
2 |
2 |
100.00 |
CASE |
186 |
23 |
18 |
78.26 |
IF |
314 |
3 |
3 |
100.00 |
IF |
321 |
3 |
3 |
100.00 |
IF |
461 |
2 |
2 |
100.00 |
IF |
464 |
3 |
3 |
100.00 |
IF |
153 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 336 ((tlul_rvalid_o && (tlul_rerror_o == '0))) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 349 ((otp_addr_sel == DigestAddrSel)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 358 ((otp_addr_sel == DigestAddrSel)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 395 ((~init_done_o)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 420 ((digest_o != '0)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T13 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 186 case (state_q)
-2-: 191 if (init_req_i)
-3-: 193 if (1'b1)
-4-: 206 if (otp_gnt_i)
-5-: 215 if (otp_rvalid_i)
-6-: 217 if ((otp_err inside {NoError, MacroEccCorrError}))
-7-: 220 if ((otp_err != NoError))
-8-: 234 if (tlul_req_i)
-9-: 248 if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-: 251 if (otp_gnt_i)
-11-: 267 if (otp_rvalid_i)
-12-: 269 if ((otp_err inside {NoError, MacroEccCorrError}))
-13-: 272 if ((otp_err != NoError))
-14-: 288 if ((error_q == NoError))
-15-: 293 if (pending_tlul_error_q)
-16-: 296 if (tlul_req_i)
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | -15- | -16- | Status | Tests |
ResetSt |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
ResetSt |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
ResetSt |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
InitSt |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
InitSt |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
InitWaitSt |
- |
- |
- |
1 |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
InitWaitSt |
- |
- |
- |
1 |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
InitWaitSt |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
InitWaitSt |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
IdleSt |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
IdleSt |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
ReadSt |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
ReadSt |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T48,T7,T110 |
ReadSt |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T18,T19 |
ReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
1 |
- |
- |
- |
Not Covered |
|
ReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
0 |
- |
- |
- |
Covered |
T1,T2,T3 |
ReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
Not Covered |
|
ReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T26,T27,T28 |
ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
Covered |
T2,T3,T9 |
ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
Covered |
T6,T73,T114 |
ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
Covered |
T6,T73,T114 |
ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
Covered |
T2,T3,T9 |
default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T26,T27,T28 |
LineNo. Expression
-1-: 314 if (ecc_err)
-2-: 316 if ((state_q != ErrorSt))
Branches:
-1- | -2- | Status | Tests |
1 |
1 |
Covered |
T176,T177,T189 |
1 |
0 |
Covered |
T176,T177,T189 |
0 |
- |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 321 if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-: 324 if ((state_q != ErrorSt))
Branches:
-1- | -2- | Status | Tests |
1 |
1 |
Covered |
T2,T3,T9 |
1 |
0 |
Covered |
T2,T3,T9 |
0 |
- |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 461 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 464 if ((!rst_ni))
-2-: 471 if (tlul_gnt_o)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 153 if ((otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}))
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T13,T118 |
0 |
Covered |
T1,T2,T3 |
Branch Coverage for Module :
otp_ctrl_part_unbuf ( parameter Info=134635604,DigestOffset=464,StateWidth=10 + Info=990543956,DigestOffset=1136,StateWidth=10 + Info=-1,DigestOffset=1608,StateWidth=10 + Info=-1,DigestOffset=1648,StateWidth=10 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
Branches |
|
44 |
44 |
100.00 |
TERNARY |
336 |
2 |
2 |
100.00 |
TERNARY |
349 |
2 |
2 |
100.00 |
TERNARY |
358 |
2 |
2 |
100.00 |
TERNARY |
395 |
2 |
2 |
100.00 |
TERNARY |
420 |
2 |
2 |
100.00 |
CASE |
186 |
23 |
23 |
100.00 |
IF |
314 |
3 |
3 |
100.00 |
IF |
321 |
3 |
3 |
100.00 |
IF |
461 |
2 |
2 |
100.00 |
IF |
464 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 336 ((tlul_rvalid_o && (tlul_rerror_o == '0))) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 349 ((otp_addr_sel == DigestAddrSel)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 358 ((otp_addr_sel == DigestAddrSel)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 395 ((~init_done_o)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 420 ((digest_o != '0)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T13,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 186 case (state_q)
-2-: 191 if (init_req_i)
-3-: 193 if (1'b1)
-4-: 206 if (otp_gnt_i)
-5-: 215 if (otp_rvalid_i)
-6-: 217 if ((otp_err inside {NoError, MacroEccCorrError}))
-7-: 220 if ((otp_err != NoError))
-8-: 234 if (tlul_req_i)
-9-: 248 if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-: 251 if (otp_gnt_i)
-11-: 267 if (otp_rvalid_i)
-12-: 269 if ((otp_err inside {NoError, MacroEccCorrError}))
-13-: 272 if ((otp_err != NoError))
-14-: 288 if ((error_q == NoError))
-15-: 293 if (pending_tlul_error_q)
-16-: 296 if (tlul_req_i)
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | -15- | -16- | Status | Tests |
ResetSt |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
ResetSt |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
ResetSt |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
InitSt |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
InitSt |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
InitWaitSt |
- |
- |
- |
1 |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T3,T112,T109 |
InitWaitSt |
- |
- |
- |
1 |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
InitWaitSt |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T13,T118,T123 |
InitWaitSt |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
IdleSt |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
IdleSt |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
ReadSt |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
ReadSt |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T48,T7,T110 |
ReadSt |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T18,T19 |
ReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
1 |
- |
- |
- |
Covered |
T105,T106,T183 |
ReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
0 |
- |
- |
- |
Covered |
T1,T2,T3 |
ReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
Covered |
T183,T195,T196 |
ReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T26,T27,T28 |
ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
Covered |
T2,T3,T9 |
ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
Covered |
T6,T73,T114 |
ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
Covered |
T6,T73,T114 |
ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
Covered |
T2,T3,T9 |
default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T26,T27,T28 |
LineNo. Expression
-1-: 314 if (ecc_err)
-2-: 316 if ((state_q != ErrorSt))
Branches:
-1- | -2- | Status | Tests |
1 |
1 |
Covered |
T2,T176,T177 |
1 |
0 |
Covered |
T2,T176,T177 |
0 |
- |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 321 if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-: 324 if ((state_q != ErrorSt))
Branches:
-1- | -2- | Status | Tests |
1 |
1 |
Covered |
T2,T3,T9 |
1 |
0 |
Covered |
T2,T3,T9 |
0 |
- |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 461 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 464 if ((!rst_ni))
-2-: 471 if (tlul_gnt_o)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
otp_ctrl_part_unbuf
Assertion Details
AccessKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
138730 |
136185 |
0 |
0 |
T2 |
42475 |
41080 |
0 |
0 |
T3 |
55005 |
53900 |
0 |
0 |
T4 |
197665 |
195245 |
0 |
0 |
T9 |
69855 |
68555 |
0 |
0 |
T10 |
24265 |
23885 |
0 |
0 |
T11 |
52145 |
51760 |
0 |
0 |
T12 |
82215 |
80940 |
0 |
0 |
T13 |
52865 |
51800 |
0 |
0 |
T14 |
23670 |
23330 |
0 |
0 |
DigestKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
138730 |
136185 |
0 |
0 |
T2 |
42475 |
41080 |
0 |
0 |
T3 |
55005 |
53900 |
0 |
0 |
T4 |
197665 |
195245 |
0 |
0 |
T9 |
69855 |
68555 |
0 |
0 |
T10 |
24265 |
23885 |
0 |
0 |
T11 |
52145 |
51760 |
0 |
0 |
T12 |
82215 |
80940 |
0 |
0 |
T13 |
52865 |
51800 |
0 |
0 |
T14 |
23670 |
23330 |
0 |
0 |
DigestOffsetMustBeRepresentable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
5765 |
5765 |
0 |
0 |
T1 |
5 |
5 |
0 |
0 |
T2 |
5 |
5 |
0 |
0 |
T3 |
5 |
5 |
0 |
0 |
T4 |
5 |
5 |
0 |
0 |
T9 |
5 |
5 |
0 |
0 |
T10 |
5 |
5 |
0 |
0 |
T11 |
5 |
5 |
0 |
0 |
T12 |
5 |
5 |
0 |
0 |
T13 |
5 |
5 |
0 |
0 |
T14 |
5 |
5 |
0 |
0 |
EccErrorState_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
92559 |
0 |
0 |
T2 |
8495 |
3375 |
0 |
0 |
T82 |
31872 |
0 |
0 |
0 |
T176 |
29961 |
9327 |
0 |
0 |
T177 |
0 |
6138 |
0 |
0 |
T186 |
11617 |
7302 |
0 |
0 |
T187 |
0 |
8988 |
0 |
0 |
T188 |
0 |
8040 |
0 |
0 |
T189 |
0 |
7978 |
0 |
0 |
T191 |
0 |
10548 |
0 |
0 |
T197 |
0 |
6800 |
0 |
0 |
T198 |
0 |
2629 |
0 |
0 |
T199 |
0 |
10304 |
0 |
0 |
T200 |
0 |
11130 |
0 |
0 |
T201 |
26238 |
0 |
0 |
0 |
T202 |
42654 |
0 |
0 |
0 |
T203 |
534666 |
0 |
0 |
0 |
T204 |
236766 |
0 |
0 |
0 |
T205 |
44748 |
0 |
0 |
0 |
T206 |
36120 |
0 |
0 |
0 |
T207 |
728676 |
0 |
0 |
0 |
T208 |
38823 |
0 |
0 |
0 |
T209 |
27974 |
0 |
0 |
0 |
T210 |
525824 |
0 |
0 |
0 |
T211 |
9269 |
0 |
0 |
0 |
T212 |
66143 |
0 |
0 |
0 |
T213 |
122396 |
0 |
0 |
0 |
T214 |
52006 |
0 |
0 |
0 |
T215 |
16764 |
0 |
0 |
0 |
T216 |
15362 |
0 |
0 |
0 |
T217 |
16608 |
0 |
0 |
0 |
ErrorKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
138730 |
136185 |
0 |
0 |
T2 |
42475 |
41080 |
0 |
0 |
T3 |
55005 |
53900 |
0 |
0 |
T4 |
197665 |
195245 |
0 |
0 |
T9 |
69855 |
68555 |
0 |
0 |
T10 |
24265 |
23885 |
0 |
0 |
T11 |
52145 |
51760 |
0 |
0 |
T12 |
82215 |
80940 |
0 |
0 |
T13 |
52865 |
51800 |
0 |
0 |
T14 |
23670 |
23330 |
0 |
0 |
FsmStateKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
138730 |
136185 |
0 |
0 |
T2 |
42475 |
41080 |
0 |
0 |
T3 |
55005 |
53900 |
0 |
0 |
T4 |
197665 |
195245 |
0 |
0 |
T9 |
69855 |
68555 |
0 |
0 |
T10 |
24265 |
23885 |
0 |
0 |
T11 |
52145 |
51760 |
0 |
0 |
T12 |
82215 |
80940 |
0 |
0 |
T13 |
52865 |
51800 |
0 |
0 |
T14 |
23670 |
23330 |
0 |
0 |
InitDoneKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
138730 |
136185 |
0 |
0 |
T2 |
42475 |
41080 |
0 |
0 |
T3 |
55005 |
53900 |
0 |
0 |
T4 |
197665 |
195245 |
0 |
0 |
T9 |
69855 |
68555 |
0 |
0 |
T10 |
24265 |
23885 |
0 |
0 |
T11 |
52145 |
51760 |
0 |
0 |
T12 |
82215 |
80940 |
0 |
0 |
T13 |
52865 |
51800 |
0 |
0 |
T14 |
23670 |
23330 |
0 |
0 |
InitReadLocksPartition_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
344997390 |
0 |
0 |
T1 |
138730 |
9905 |
0 |
0 |
T2 |
42475 |
21315 |
0 |
0 |
T3 |
55005 |
22530 |
0 |
0 |
T4 |
197665 |
2060 |
0 |
0 |
T9 |
69855 |
23810 |
0 |
0 |
T10 |
24265 |
415 |
0 |
0 |
T11 |
52145 |
2095 |
0 |
0 |
T12 |
82215 |
19565 |
0 |
0 |
T13 |
52865 |
16908 |
0 |
0 |
T14 |
23670 |
2955 |
0 |
0 |
InitWriteLocksPartition_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
344997390 |
0 |
0 |
T1 |
138730 |
9905 |
0 |
0 |
T2 |
42475 |
21315 |
0 |
0 |
T3 |
55005 |
22530 |
0 |
0 |
T4 |
197665 |
2060 |
0 |
0 |
T9 |
69855 |
23810 |
0 |
0 |
T10 |
24265 |
415 |
0 |
0 |
T11 |
52145 |
2095 |
0 |
0 |
T12 |
82215 |
19565 |
0 |
0 |
T13 |
52865 |
16908 |
0 |
0 |
T14 |
23670 |
2955 |
0 |
0 |
OffsetMustBeBlockAligned_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
5765 |
5765 |
0 |
0 |
T1 |
5 |
5 |
0 |
0 |
T2 |
5 |
5 |
0 |
0 |
T3 |
5 |
5 |
0 |
0 |
T4 |
5 |
5 |
0 |
0 |
T9 |
5 |
5 |
0 |
0 |
T10 |
5 |
5 |
0 |
0 |
T11 |
5 |
5 |
0 |
0 |
T12 |
5 |
5 |
0 |
0 |
T13 |
5 |
5 |
0 |
0 |
T14 |
5 |
5 |
0 |
0 |
OtpAddrKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
138730 |
136185 |
0 |
0 |
T2 |
42475 |
41080 |
0 |
0 |
T3 |
55005 |
53900 |
0 |
0 |
T4 |
197665 |
195245 |
0 |
0 |
T9 |
69855 |
68555 |
0 |
0 |
T10 |
24265 |
23885 |
0 |
0 |
T11 |
52145 |
51760 |
0 |
0 |
T12 |
82215 |
80940 |
0 |
0 |
T13 |
52865 |
51800 |
0 |
0 |
T14 |
23670 |
23330 |
0 |
0 |
OtpCmdKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
138730 |
136185 |
0 |
0 |
T2 |
42475 |
41080 |
0 |
0 |
T3 |
55005 |
53900 |
0 |
0 |
T4 |
197665 |
195245 |
0 |
0 |
T9 |
69855 |
68555 |
0 |
0 |
T10 |
24265 |
23885 |
0 |
0 |
T11 |
52145 |
51760 |
0 |
0 |
T12 |
82215 |
80940 |
0 |
0 |
T13 |
52865 |
51800 |
0 |
0 |
T14 |
23670 |
23330 |
0 |
0 |
OtpErrorState_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
194 |
0 |
0 |
T5 |
18478 |
0 |
0 |
0 |
T6 |
235026 |
0 |
0 |
0 |
T7 |
400968 |
0 |
0 |
0 |
T13 |
10573 |
1 |
0 |
0 |
T14 |
4734 |
0 |
0 |
0 |
T18 |
135070 |
0 |
0 |
0 |
T19 |
89614 |
0 |
0 |
0 |
T45 |
20422 |
0 |
0 |
0 |
T48 |
63072 |
0 |
0 |
0 |
T51 |
11783 |
0 |
0 |
0 |
T73 |
154514 |
0 |
0 |
0 |
T93 |
13105 |
0 |
0 |
0 |
T94 |
70657 |
0 |
0 |
0 |
T109 |
0 |
1 |
0 |
0 |
T110 |
30122 |
0 |
0 |
0 |
T112 |
27480 |
1 |
0 |
0 |
T113 |
7552 |
0 |
0 |
0 |
T114 |
59432 |
0 |
0 |
0 |
T115 |
94924 |
0 |
0 |
0 |
T118 |
21410 |
1 |
0 |
0 |
T123 |
25426 |
1 |
0 |
0 |
T183 |
0 |
2 |
0 |
0 |
T184 |
12955 |
1 |
0 |
0 |
T190 |
0 |
1 |
0 |
0 |
T218 |
0 |
1 |
0 |
0 |
T219 |
0 |
1 |
0 |
0 |
T220 |
0 |
1 |
0 |
0 |
T221 |
0 |
1 |
0 |
0 |
T222 |
0 |
1 |
0 |
0 |
T223 |
0 |
1 |
0 |
0 |
T224 |
0 |
1 |
0 |
0 |
T225 |
0 |
1 |
0 |
0 |
T226 |
0 |
1 |
0 |
0 |
T227 |
0 |
1 |
0 |
0 |
T228 |
0 |
1 |
0 |
0 |
T229 |
0 |
1 |
0 |
0 |
T230 |
0 |
1 |
0 |
0 |
OtpReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
138730 |
136185 |
0 |
0 |
T2 |
42475 |
41080 |
0 |
0 |
T3 |
55005 |
53900 |
0 |
0 |
T4 |
197665 |
195245 |
0 |
0 |
T9 |
69855 |
68555 |
0 |
0 |
T10 |
24265 |
23885 |
0 |
0 |
T11 |
52145 |
51760 |
0 |
0 |
T12 |
82215 |
80940 |
0 |
0 |
T13 |
52865 |
51800 |
0 |
0 |
T14 |
23670 |
23330 |
0 |
0 |
OtpSizeKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
138730 |
136185 |
0 |
0 |
T2 |
42475 |
41080 |
0 |
0 |
T3 |
55005 |
53900 |
0 |
0 |
T4 |
197665 |
195245 |
0 |
0 |
T9 |
69855 |
68555 |
0 |
0 |
T10 |
24265 |
23885 |
0 |
0 |
T11 |
52145 |
51760 |
0 |
0 |
T12 |
82215 |
80940 |
0 |
0 |
T13 |
52865 |
51800 |
0 |
0 |
T14 |
23670 |
23330 |
0 |
0 |
OtpWdataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
138730 |
136185 |
0 |
0 |
T2 |
42475 |
41080 |
0 |
0 |
T3 |
55005 |
53900 |
0 |
0 |
T4 |
197665 |
195245 |
0 |
0 |
T9 |
69855 |
68555 |
0 |
0 |
T10 |
24265 |
23885 |
0 |
0 |
T11 |
52145 |
51760 |
0 |
0 |
T12 |
82215 |
80940 |
0 |
0 |
T13 |
52865 |
51800 |
0 |
0 |
T14 |
23670 |
23330 |
0 |
0 |
ReadLockPropagation_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
935928941 |
0 |
0 |
T1 |
138730 |
9387 |
0 |
0 |
T2 |
42475 |
0 |
0 |
0 |
T3 |
55005 |
0 |
0 |
0 |
T4 |
197665 |
0 |
0 |
0 |
T5 |
0 |
2520 |
0 |
0 |
T7 |
0 |
564378 |
0 |
0 |
T9 |
69855 |
0 |
0 |
0 |
T10 |
24265 |
0 |
0 |
0 |
T11 |
52145 |
0 |
0 |
0 |
T12 |
82215 |
0 |
0 |
0 |
T13 |
52865 |
0 |
0 |
0 |
T14 |
23670 |
0 |
0 |
0 |
T18 |
0 |
174321 |
0 |
0 |
T19 |
0 |
37847 |
0 |
0 |
T48 |
0 |
22126 |
0 |
0 |
T55 |
0 |
34680 |
0 |
0 |
T104 |
0 |
30817 |
0 |
0 |
T110 |
0 |
12392 |
0 |
0 |
T114 |
0 |
12130 |
0 |
0 |
T115 |
0 |
415083 |
0 |
0 |
T116 |
0 |
74681 |
0 |
0 |
SizeMustBeBlockAligned_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
5765 |
5765 |
0 |
0 |
T1 |
5 |
5 |
0 |
0 |
T2 |
5 |
5 |
0 |
0 |
T3 |
5 |
5 |
0 |
0 |
T4 |
5 |
5 |
0 |
0 |
T9 |
5 |
5 |
0 |
0 |
T10 |
5 |
5 |
0 |
0 |
T11 |
5 |
5 |
0 |
0 |
T12 |
5 |
5 |
0 |
0 |
T13 |
5 |
5 |
0 |
0 |
T14 |
5 |
5 |
0 |
0 |
TlulGntKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
138730 |
136185 |
0 |
0 |
T2 |
42475 |
41080 |
0 |
0 |
T3 |
55005 |
53900 |
0 |
0 |
T4 |
197665 |
195245 |
0 |
0 |
T9 |
69855 |
68555 |
0 |
0 |
T10 |
24265 |
23885 |
0 |
0 |
T11 |
52145 |
51760 |
0 |
0 |
T12 |
82215 |
80940 |
0 |
0 |
T13 |
52865 |
51800 |
0 |
0 |
T14 |
23670 |
23330 |
0 |
0 |
TlulRdataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
138730 |
136185 |
0 |
0 |
T2 |
42475 |
41080 |
0 |
0 |
T3 |
55005 |
53900 |
0 |
0 |
T4 |
197665 |
195245 |
0 |
0 |
T9 |
69855 |
68555 |
0 |
0 |
T10 |
24265 |
23885 |
0 |
0 |
T11 |
52145 |
51760 |
0 |
0 |
T12 |
82215 |
80940 |
0 |
0 |
T13 |
52865 |
51800 |
0 |
0 |
T14 |
23670 |
23330 |
0 |
0 |
TlulReadOnReadLock_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
37213 |
0 |
0 |
T1 |
83238 |
3 |
0 |
0 |
T2 |
25485 |
0 |
0 |
0 |
T3 |
33003 |
0 |
0 |
0 |
T4 |
118599 |
0 |
0 |
0 |
T6 |
235026 |
92 |
0 |
0 |
T7 |
0 |
140 |
0 |
0 |
T9 |
41913 |
0 |
0 |
0 |
T10 |
14559 |
0 |
0 |
0 |
T11 |
31287 |
0 |
0 |
0 |
T12 |
49329 |
0 |
0 |
0 |
T13 |
31719 |
0 |
0 |
0 |
T14 |
14202 |
0 |
0 |
0 |
T18 |
270140 |
41 |
0 |
0 |
T19 |
89614 |
7 |
0 |
0 |
T45 |
40844 |
0 |
0 |
0 |
T48 |
63072 |
23 |
0 |
0 |
T51 |
23566 |
0 |
0 |
0 |
T55 |
0 |
22 |
0 |
0 |
T73 |
154514 |
48 |
0 |
0 |
T110 |
0 |
18 |
0 |
0 |
T112 |
18320 |
0 |
0 |
0 |
T114 |
0 |
30 |
0 |
0 |
T115 |
0 |
100 |
0 |
0 |
T116 |
0 |
2 |
0 |
0 |
T118 |
21410 |
0 |
0 |
0 |
T123 |
25426 |
0 |
0 |
0 |
TlulRerrorKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
138730 |
136185 |
0 |
0 |
T2 |
42475 |
41080 |
0 |
0 |
T3 |
55005 |
53900 |
0 |
0 |
T4 |
197665 |
195245 |
0 |
0 |
T9 |
69855 |
68555 |
0 |
0 |
T10 |
24265 |
23885 |
0 |
0 |
T11 |
52145 |
51760 |
0 |
0 |
T12 |
82215 |
80940 |
0 |
0 |
T13 |
52865 |
51800 |
0 |
0 |
T14 |
23670 |
23330 |
0 |
0 |
TlulRvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
138730 |
136185 |
0 |
0 |
T2 |
42475 |
41080 |
0 |
0 |
T3 |
55005 |
53900 |
0 |
0 |
T4 |
197665 |
195245 |
0 |
0 |
T9 |
69855 |
68555 |
0 |
0 |
T10 |
24265 |
23885 |
0 |
0 |
T11 |
52145 |
51760 |
0 |
0 |
T12 |
82215 |
80940 |
0 |
0 |
T13 |
52865 |
51800 |
0 |
0 |
T14 |
23670 |
23330 |
0 |
0 |
WriteLockPropagation_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
8414759 |
0 |
0 |
T1 |
27746 |
3718 |
0 |
0 |
T2 |
8495 |
0 |
0 |
0 |
T3 |
11001 |
0 |
0 |
0 |
T4 |
39533 |
0 |
0 |
0 |
T6 |
117513 |
0 |
0 |
0 |
T7 |
400968 |
0 |
0 |
0 |
T9 |
13971 |
0 |
0 |
0 |
T10 |
4853 |
0 |
0 |
0 |
T11 |
10429 |
0 |
0 |
0 |
T12 |
16443 |
0 |
0 |
0 |
T13 |
10573 |
0 |
0 |
0 |
T14 |
4734 |
0 |
0 |
0 |
T18 |
0 |
44056 |
0 |
0 |
T19 |
44807 |
15086 |
0 |
0 |
T41 |
0 |
35417 |
0 |
0 |
T48 |
63072 |
6151 |
0 |
0 |
T55 |
0 |
18393 |
0 |
0 |
T73 |
77257 |
0 |
0 |
0 |
T74 |
0 |
227521 |
0 |
0 |
T91 |
0 |
10754 |
0 |
0 |
T92 |
0 |
14236 |
0 |
0 |
T99 |
0 |
97496 |
0 |
0 |
T100 |
0 |
212247 |
0 |
0 |
T101 |
0 |
35022 |
0 |
0 |
T102 |
0 |
5017 |
0 |
0 |
T106 |
0 |
36562 |
0 |
0 |
T110 |
60244 |
1158 |
0 |
0 |
T112 |
9160 |
0 |
0 |
0 |
T113 |
7552 |
0 |
0 |
0 |
T114 |
59432 |
0 |
0 |
0 |
T115 |
189848 |
0 |
0 |
0 |
T135 |
0 |
6061 |
0 |
0 |
T149 |
0 |
1198 |
0 |
0 |
T184 |
12955 |
0 |
0 |
0 |
T231 |
0 |
8359 |
0 |
0 |
T232 |
0 |
12619 |
0 |
0 |
T233 |
0 |
3593 |
0 |
0 |
gen_digest_write_lock.DigestWriteLocksPartition_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
99498927 |
0 |
0 |
T1 |
110984 |
61384 |
0 |
0 |
T2 |
33980 |
0 |
0 |
0 |
T3 |
44004 |
3659 |
0 |
0 |
T4 |
158132 |
0 |
0 |
0 |
T5 |
18478 |
28743 |
0 |
0 |
T6 |
117513 |
0 |
0 |
0 |
T9 |
55884 |
0 |
0 |
0 |
T10 |
19412 |
0 |
0 |
0 |
T11 |
41716 |
0 |
0 |
0 |
T12 |
65772 |
0 |
0 |
0 |
T13 |
42292 |
4817 |
0 |
0 |
T14 |
18936 |
0 |
0 |
0 |
T18 |
135070 |
436154 |
0 |
0 |
T19 |
44807 |
139426 |
0 |
0 |
T41 |
0 |
166832 |
0 |
0 |
T45 |
20422 |
0 |
0 |
0 |
T48 |
0 |
87308 |
0 |
0 |
T51 |
11783 |
0 |
0 |
0 |
T55 |
0 |
108899 |
0 |
0 |
T73 |
77257 |
0 |
0 |
0 |
T99 |
0 |
91628 |
0 |
0 |
T106 |
0 |
91620 |
0 |
0 |
T109 |
0 |
2792 |
0 |
0 |
T110 |
0 |
82476 |
0 |
0 |
T112 |
9160 |
5353 |
0 |
0 |
T114 |
0 |
5376 |
0 |
0 |
T115 |
0 |
6370 |
0 |
0 |
T116 |
0 |
196342 |
0 |
0 |
T118 |
10705 |
3541 |
0 |
0 |
T123 |
12713 |
3069 |
0 |
0 |
T184 |
0 |
2146 |
0 |
0 |
T190 |
0 |
3521 |
0 |
0 |
u_state_regs_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
138730 |
136185 |
0 |
0 |
T2 |
42475 |
41080 |
0 |
0 |
T3 |
55005 |
53900 |
0 |
0 |
T4 |
197665 |
195245 |
0 |
0 |
T9 |
69855 |
68555 |
0 |
0 |
T10 |
24265 |
23885 |
0 |
0 |
T11 |
52145 |
51760 |
0 |
0 |
T12 |
82215 |
80940 |
0 |
0 |
T13 |
52865 |
51800 |
0 |
0 |
T14 |
23670 |
23330 |
0 |
0 |