Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.20	94.16	96.15	97.08		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.20	94.16	96.15	97.08		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T93,T39,T75

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T183,T72,T185

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T26,T27,T28

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T186,T187,T188
1	Covered	T186,T187,T188

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T2,T3,T9

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T18,T19
1	1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b10001111000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T18,T19

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T18,T19

---

FSM Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T3,T9
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T2,T3
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T3,T9,T12
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T13,T123,T114
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T118,T112,T103
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T1,T18,T19
ReadSt->ReadWaitSt	252	Covered	T1,T2,T3
ReadWaitSt->ErrorSt	276	Covered	T213,T241,T242
ReadWaitSt->IdleSt	270	Covered	T1,T2,T3
ResetSt->ErrorSt	315	Covered	T2,T79,T80
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T1,T18,T19
CheckFailError	317	Covered	T186,T187,T188
FsmStateError	289	Covered	T2,T3,T9
MacroEccCorrError	221	Covered	T183,T93,T72
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T7,T104,T8
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T1,T18,T19
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T186,T187,T188
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T2,T3,T9
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T183,T93,T39
MacroEccCorrError->NoError	235	Covered	T72,T185,T33
NoError->AccessError	256	Covered	T1,T18,T19
NoError->CheckFailError	317	Covered	T186,T187,T188
NoError->FsmStateError	289	Covered	T2,T3,T9
NoError->MacroEccCorrError	221	Covered	T183,T93,T72

---

Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T18,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T93,T39,T75
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T112,T103,T194
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T48,T7,T110
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T18,T19
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T183,T72,T185
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T213,T241,T242
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T26,T27,T28
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T9
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T6,T73,T114
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T6,T73,T114
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T26,T27,T28

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T186,T187,T188
1	0	Covered	T186,T187,T188
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T9
1	0	Covered	T2,T3,T9
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	442410951	441597661	0	0
DigestKnown_A	442410951	441597661	0	0
DigestOffsetMustBeRepresentable_A	1153	1153	0	0
EccErrorState_A	442410951	8578	0	0
ErrorKnown_A	442410951	441597661	0	0
FsmStateKnown_A	442410951	441597661	0	0
InitDoneKnown_A	442410951	441597661	0	0
InitReadLocksPartition_A	442410951	69172438	0	0
InitWriteLocksPartition_A	442410951	69172438	0	0
OffsetMustBeBlockAligned_A	1153	1153	0	0
OtpAddrKnown_A	442410951	441597661	0	0
OtpCmdKnown_A	442410951	441597661	0	0
OtpErrorState_A	442410951	32	0	0
OtpReqKnown_A	442410951	441597661	0	0
OtpSizeKnown_A	442410951	441597661	0	0
OtpWdataKnown_A	442410951	441597661	0	0
ReadLockPropagation_A	442410951	186912994	0	0
SizeMustBeBlockAligned_A	1153	1153	0	0
TlulGntKnown_A	442410951	441597661	0	0
TlulRdataKnown_A	442410951	441597661	0	0
TlulReadOnReadLock_A	442410951	7522	0	0
TlulRerrorKnown_A	442410951	441597661	0	0
TlulRvalidKnown_A	442410951	441597661	0	0
WriteLockPropagation_A	442410951	2211773	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	442410951	24024996	0	0
u_state_regs_A	442410951	441597661	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442410951	441597661	0	0
T1	27746	27237	0	0
T2	8495	8216	0	0
T3	11001	10780	0	0
T4	39533	39049	0	0
T9	13971	13711	0	0
T10	4853	4777	0	0
T11	10429	10352	0	0
T12	16443	16188	0	0
T13	10573	10360	0	0
T14	4734	4666	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442410951	441597661	0	0
T1	27746	27237	0	0
T2	8495	8216	0	0
T3	11001	10780	0	0
T4	39533	39049	0	0
T9	13971	13711	0	0
T10	4853	4777	0	0
T11	10429	10352	0	0
T12	16443	16188	0	0
T13	10573	10360	0	0
T14	4734	4666	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1153	1153	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442410951	8578	0	0
T186	11617	3651	0	0
T187	0	2247	0	0
T188	0	2680	0	0
T209	27974	0	0	0
T210	525824	0	0	0
T211	9269	0	0	0
T212	66143	0	0	0
T213	122396	0	0	0
T214	52006	0	0	0
T215	16764	0	0	0
T216	15362	0	0	0
T217	16608	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442410951	441597661	0	0
T1	27746	27237	0	0
T2	8495	8216	0	0
T3	11001	10780	0	0
T4	39533	39049	0	0
T9	13971	13711	0	0
T10	4853	4777	0	0
T11	10429	10352	0	0
T12	16443	16188	0	0
T13	10573	10360	0	0
T14	4734	4666	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442410951	441597661	0	0
T1	27746	27237	0	0
T2	8495	8216	0	0
T3	11001	10780	0	0
T4	39533	39049	0	0
T9	13971	13711	0	0
T10	4853	4777	0	0
T11	10429	10352	0	0
T12	16443	16188	0	0
T13	10573	10360	0	0
T14	4734	4666	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442410951	441597661	0	0
T1	27746	27237	0	0
T2	8495	8216	0	0
T3	11001	10780	0	0
T4	39533	39049	0	0
T9	13971	13711	0	0
T10	4853	4777	0	0
T11	10429	10352	0	0
T12	16443	16188	0	0
T13	10573	10360	0	0
T14	4734	4666	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442410951	69172438	0	0
T1	27746	2049	0	0
T2	8495	4280	0	0
T3	11001	4540	0	0
T4	39533	497	0	0
T9	13971	4813	0	0
T10	4853	100	0	0
T11	10429	436	0	0
T12	16443	3947	0	0
T13	10573	3400	0	0
T14	4734	608	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442410951	69172438	0	0
T1	27746	2049	0	0
T2	8495	4280	0	0
T3	11001	4540	0	0
T4	39533	497	0	0
T9	13971	4813	0	0
T10	4853	100	0	0
T11	10429	436	0	0
T12	16443	3947	0	0
T13	10573	3400	0	0
T14	4734	608	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1153	1153	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442410951	441597661	0	0
T1	27746	27237	0	0
T2	8495	8216	0	0
T3	11001	10780	0	0
T4	39533	39049	0	0
T9	13971	13711	0	0
T10	4853	4777	0	0
T11	10429	10352	0	0
T12	16443	16188	0	0
T13	10573	10360	0	0
T14	4734	4666	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442410951	441597661	0	0
T1	27746	27237	0	0
T2	8495	8216	0	0
T3	11001	10780	0	0
T4	39533	39049	0	0
T9	13971	13711	0	0
T10	4853	4777	0	0
T11	10429	10352	0	0
T12	16443	16188	0	0
T13	10573	10360	0	0
T14	4734	4666	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442410951	32	0	0
T6	117513	0	0	0
T7	200484	0	0	0
T48	31536	0	0	0
T73	77257	0	0	0
T103	0	1	0	0
T110	30122	0	0	0
T112	9160	1	0	0
T113	3776	0	0	0
T114	29716	0	0	0
T115	94924	0	0	0
T184	12955	0	0	0
T194	0	1	0	0
T213	0	1	0	0
T241	0	1	0	0
T243	0	1	0	0
T244	0	1	0	0
T245	0	1	0	0
T246	0	1	0	0
T247	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442410951	441597661	0	0
T1	27746	27237	0	0
T2	8495	8216	0	0
T3	11001	10780	0	0
T4	39533	39049	0	0
T9	13971	13711	0	0
T10	4853	4777	0	0
T11	10429	10352	0	0
T12	16443	16188	0	0
T13	10573	10360	0	0
T14	4734	4666	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442410951	441597661	0	0
T1	27746	27237	0	0
T2	8495	8216	0	0
T3	11001	10780	0	0
T4	39533	39049	0	0
T9	13971	13711	0	0
T10	4853	4777	0	0
T11	10429	10352	0	0
T12	16443	16188	0	0
T13	10573	10360	0	0
T14	4734	4666	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442410951	441597661	0	0
T1	27746	27237	0	0
T2	8495	8216	0	0
T3	11001	10780	0	0
T4	39533	39049	0	0
T9	13971	13711	0	0
T10	4853	4777	0	0
T11	10429	10352	0	0
T12	16443	16188	0	0
T13	10573	10360	0	0
T14	4734	4666	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442410951	186912994	0	0
T1	27746	2957	0	0
T2	8495	0	0	0
T3	11001	0	0	0
T4	39533	0	0	0
T7	0	113002	0	0
T9	13971	0	0	0
T10	4853	0	0	0
T11	10429	0	0	0
T12	16443	0	0	0
T13	10573	0	0	0
T14	4734	0	0	0
T18	0	40151	0	0
T19	0	5012	0	0
T48	0	4492	0	0
T55	0	12384	0	0
T104	0	26105	0	0
T110	0	866	0	0
T115	0	82573	0	0
T116	0	2314	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1153	1153	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442410951	441597661	0	0
T1	27746	27237	0	0
T2	8495	8216	0	0
T3	11001	10780	0	0
T4	39533	39049	0	0
T9	13971	13711	0	0
T10	4853	4777	0	0
T11	10429	10352	0	0
T12	16443	16188	0	0
T13	10573	10360	0	0
T14	4734	4666	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442410951	441597661	0	0
T1	27746	27237	0	0
T2	8495	8216	0	0
T3	11001	10780	0	0
T4	39533	39049	0	0
T9	13971	13711	0	0
T10	4853	4777	0	0
T11	10429	10352	0	0
T12	16443	16188	0	0
T13	10573	10360	0	0
T14	4734	4666	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442410951	7522	0	0
T1	27746	1	0	0
T2	8495	0	0	0
T3	11001	0	0	0
T4	39533	0	0	0
T6	0	21	0	0
T7	0	21	0	0
T9	13971	0	0	0
T10	4853	0	0	0
T11	10429	0	0	0
T12	16443	0	0	0
T13	10573	0	0	0
T14	4734	0	0	0
T18	0	10	0	0
T19	0	1	0	0
T48	0	5	0	0
T73	0	7	0	0
T110	0	2	0	0
T114	0	10	0	0
T115	0	26	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442410951	441597661	0	0
T1	27746	27237	0	0
T2	8495	8216	0	0
T3	11001	10780	0	0
T4	39533	39049	0	0
T9	13971	13711	0	0
T10	4853	4777	0	0
T11	10429	10352	0	0
T12	16443	16188	0	0
T13	10573	10360	0	0
T14	4734	4666	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442410951	441597661	0	0
T1	27746	27237	0	0
T2	8495	8216	0	0
T3	11001	10780	0	0
T4	39533	39049	0	0
T9	13971	13711	0	0
T10	4853	4777	0	0
T11	10429	10352	0	0
T12	16443	16188	0	0
T13	10573	10360	0	0
T14	4734	4666	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442410951	2211773	0	0
T6	117513	0	0	0
T18	135070	19240	0	0
T19	44807	3748	0	0
T41	0	3284	0	0
T45	20422	0	0	0
T48	31536	0	0	0
T51	11783	0	0	0
T73	77257	0	0	0
T74	0	19512	0	0
T91	0	5377	0	0
T92	0	4826	0	0
T99	0	22832	0	0
T100	0	80911	0	0
T101	0	12266	0	0
T106	0	8396	0	0
T112	9160	0	0	0
T118	10705	0	0	0
T123	12713	0	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442410951	24024996	0	0
T1	27746	6160	0	0
T2	8495	0	0	0
T3	11001	0	0	0
T4	39533	0	0	0
T9	13971	0	0	0
T10	4853	0	0	0
T11	10429	0	0	0
T12	16443	0	0	0
T13	10573	0	0	0
T14	4734	0	0	0
T18	0	98926	0	0
T19	0	34729	0	0
T48	0	21725	0	0
T55	0	54543	0	0
T106	0	45776	0	0
T110	0	20517	0	0
T112	0	2657	0	0
T115	0	3151	0	0
T116	0	98154	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442410951	441597661	0	0
T1	27746	27237	0	0
T2	8495	8216	0	0
T3	11001	10780	0	0
T4	39533	39049	0	0
T9	13971	13711	0	0
T10	4853	4777	0	0
T11	10429	10352	0	0
T12	16443	16188	0	0
T13	10573	10360	0	0
T14	4734	4666	0	0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T46,T192

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T106,T56,T193

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T26,T27,T28

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T191,T187
1	Covered	T2,T191,T187

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T3,T9,T12

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T18,T6,T73
1	1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b11001010000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T18,T55

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T18,T55

---

FSM Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T3,T9
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T2,T3
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T3,T9,T12
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T13,T118,T123
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T112,T103,T93
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T18,T48,T7
ReadSt->ReadWaitSt	252	Covered	T1,T2,T3
ReadWaitSt->ErrorSt	276	Covered	T213,T180,T181
ReadWaitSt->IdleSt	270	Covered	T1,T2,T3
ResetSt->ErrorSt	315	Covered	T2,T79,T80
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T18,T48,T7
CheckFailError	317	Covered	T2,T191,T187
FsmStateError	289	Covered	T3,T9,T12
MacroEccCorrError	221	Covered	T3,T106,T56
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T7,T115,T8
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T18,T48,T7
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T2,T191,T187
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T3,T9,T12
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T3,T46,T248
MacroEccCorrError->NoError	235	Covered	T106,T56,T193
NoError->AccessError	256	Covered	T18,T48,T7
NoError->CheckFailError	317	Covered	T2,T191,T187
NoError->FsmStateError	289	Covered	T9,T12,T13
NoError->MacroEccCorrError	221	Covered	T3,T106,T56

---

Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T18,T55
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T3,T46,T192
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T93,T249,T250
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T48,T7,T110
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T18,T48,T7
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T106,T56,T193
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T213,T180,T181
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T26,T27,T28
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T9
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T6,T73,T114
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T6,T73,T114
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T26,T27,T28

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T191,T187
1	0	Covered	T2,T191,T187
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T3,T9,T12
1	0	Covered	T2,T3,T9
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	442410951	441597661	0	0
DigestKnown_A	442410951	441597661	0	0
DigestOffsetMustBeRepresentable_A	1153	1153	0	0
EccErrorState_A	442410951	17225	0	0
ErrorKnown_A	442410951	441597661	0	0
FsmStateKnown_A	442410951	441597661	0	0
InitDoneKnown_A	442410951	441597661	0	0
InitReadLocksPartition_A	442410951	69343768	0	0
InitWriteLocksPartition_A	442410951	69343768	0	0
OffsetMustBeBlockAligned_A	1153	1153	0	0
OtpAddrKnown_A	442410951	441597661	0	0
OtpCmdKnown_A	442410951	441597661	0	0
OtpErrorState_A	442410951	32	0	0
OtpReqKnown_A	442410951	441597661	0	0
OtpSizeKnown_A	442410951	441597661	0	0
OtpWdataKnown_A	442410951	441597661	0	0
ReadLockPropagation_A	442410951	187712363	0	0
SizeMustBeBlockAligned_A	1153	1153	0	0
TlulGntKnown_A	442410951	441597661	0	0
TlulRdataKnown_A	442410951	441597661	0	0
TlulReadOnReadLock_A	442410951	7183	0	0
TlulRerrorKnown_A	442410951	441597661	0	0
TlulRvalidKnown_A	442410951	441597661	0	0
WriteLockPropagation_A	442410951	761141	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	442410951	10376945	0	0
u_state_regs_A	442410951	441597661	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442410951	441597661	0	0
T1	27746	27237	0	0
T2	8495	8216	0	0
T3	11001	10780	0	0
T4	39533	39049	0	0
T9	13971	13711	0	0
T10	4853	4777	0	0
T11	10429	10352	0	0
T12	16443	16188	0	0
T13	10573	10360	0	0
T14	4734	4666	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442410951	441597661	0	0
T1	27746	27237	0	0
T2	8495	8216	0	0
T3	11001	10780	0	0
T4	39533	39049	0	0
T9	13971	13711	0	0
T10	4853	4777	0	0
T11	10429	10352	0	0
T12	16443	16188	0	0
T13	10573	10360	0	0
T14	4734	4666	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1153	1153	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442410951	17225	0	0
T2	8495	3375	0	0
T3	11001	0	0	0
T4	39533	0	0	0
T5	18478	0	0	0
T9	13971	0	0	0
T10	4853	0	0	0
T11	10429	0	0	0
T12	16443	0	0	0
T13	10573	0	0	0
T14	4734	0	0	0
T187	0	2247	0	0
T188	0	2680	0	0
T191	0	2637	0	0
T199	0	2576	0	0
T200	0	3710	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442410951	441597661	0	0
T1	27746	27237	0	0
T2	8495	8216	0	0
T3	11001	10780	0	0
T4	39533	39049	0	0
T9	13971	13711	0	0
T10	4853	4777	0	0
T11	10429	10352	0	0
T12	16443	16188	0	0
T13	10573	10360	0	0
T14	4734	4666	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442410951	441597661	0	0
T1	27746	27237	0	0
T2	8495	8216	0	0
T3	11001	10780	0	0
T4	39533	39049	0	0
T9	13971	13711	0	0
T10	4853	4777	0	0
T11	10429	10352	0	0
T12	16443	16188	0	0
T13	10573	10360	0	0
T14	4734	4666	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442410951	441597661	0	0
T1	27746	27237	0	0
T2	8495	8216	0	0
T3	11001	10780	0	0
T4	39533	39049	0	0
T9	13971	13711	0	0
T10	4853	4777	0	0
T11	10429	10352	0	0
T12	16443	16188	0	0
T13	10573	10360	0	0
T14	4734	4666	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442410951	69343768	0	0
T1	27746	2117	0	0
T2	8495	4297	0	0
T3	11001	4574	0	0
T4	39533	582	0	0
T9	13971	4864	0	0
T10	4853	117	0	0
T11	10429	453	0	0
T12	16443	3981	0	0
T13	10573	3417	0	0
T14	4734	625	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442410951	69343768	0	0
T1	27746	2117	0	0
T2	8495	4297	0	0
T3	11001	4574	0	0
T4	39533	582	0	0
T9	13971	4864	0	0
T10	4853	117	0	0
T11	10429	453	0	0
T12	16443	3981	0	0
T13	10573	3417	0	0
T14	4734	625	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1153	1153	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442410951	441597661	0	0
T1	27746	27237	0	0
T2	8495	8216	0	0
T3	11001	10780	0	0
T4	39533	39049	0	0
T9	13971	13711	0	0
T10	4853	4777	0	0
T11	10429	10352	0	0
T12	16443	16188	0	0
T13	10573	10360	0	0
T14	4734	4666	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442410951	441597661	0	0
T1	27746	27237	0	0
T2	8495	8216	0	0
T3	11001	10780	0	0
T4	39533	39049	0	0
T9	13971	13711	0	0
T10	4853	4777	0	0
T11	10429	10352	0	0
T12	16443	16188	0	0
T13	10573	10360	0	0
T14	4734	4666	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442410951	32	0	0
T84	13003	0	0	0
T93	13105	1	0	0
T94	70657	0	0	0
T95	12664	0	0	0
T96	28313	0	0	0
T97	53324	0	0	0
T98	21144	0	0	0
T135	72408	0	0	0
T149	35677	0	0	0
T180	0	1	0	0
T213	0	1	0	0
T249	0	1	0	0
T250	0	1	0	0
T251	0	1	0	0
T252	0	1	0	0
T253	0	1	0	0
T254	0	1	0	0
T255	0	1	0	0
T256	25887	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442410951	441597661	0	0
T1	27746	27237	0	0
T2	8495	8216	0	0
T3	11001	10780	0	0
T4	39533	39049	0	0
T9	13971	13711	0	0
T10	4853	4777	0	0
T11	10429	10352	0	0
T12	16443	16188	0	0
T13	10573	10360	0	0
T14	4734	4666	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442410951	441597661	0	0
T1	27746	27237	0	0
T2	8495	8216	0	0
T3	11001	10780	0	0
T4	39533	39049	0	0
T9	13971	13711	0	0
T10	4853	4777	0	0
T11	10429	10352	0	0
T12	16443	16188	0	0
T13	10573	10360	0	0
T14	4734	4666	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442410951	441597661	0	0
T1	27746	27237	0	0
T2	8495	8216	0	0
T3	11001	10780	0	0
T4	39533	39049	0	0
T9	13971	13711	0	0
T10	4853	4777	0	0
T11	10429	10352	0	0
T12	16443	16188	0	0
T13	10573	10360	0	0
T14	4734	4666	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442410951	187712363	0	0
T1	27746	1650	0	0
T2	8495	0	0	0
T3	11001	0	0	0
T4	39533	0	0	0
T7	0	113245	0	0
T9	13971	0	0	0
T10	4853	0	0	0
T11	10429	0	0	0
T12	16443	0	0	0
T13	10573	0	0	0
T14	4734	0	0	0
T18	0	30941	0	0
T19	0	8133	0	0
T48	0	4122	0	0
T55	0	12516	0	0
T104	0	4712	0	0
T110	0	1250	0	0
T115	0	83113	0	0
T116	0	23334	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1153	1153	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442410951	441597661	0	0
T1	27746	27237	0	0
T2	8495	8216	0	0
T3	11001	10780	0	0
T4	39533	39049	0	0
T9	13971	13711	0	0
T10	4853	4777	0	0
T11	10429	10352	0	0
T12	16443	16188	0	0
T13	10573	10360	0	0
T14	4734	4666	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442410951	441597661	0	0
T1	27746	27237	0	0
T2	8495	8216	0	0
T3	11001	10780	0	0
T4	39533	39049	0	0
T9	13971	13711	0	0
T10	4853	4777	0	0
T11	10429	10352	0	0
T12	16443	16188	0	0
T13	10573	10360	0	0
T14	4734	4666	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442410951	7183	0	0
T6	117513	16	0	0
T7	0	31	0	0
T18	135070	10	0	0
T19	44807	0	0	0
T45	20422	0	0	0
T48	31536	5	0	0
T51	11783	0	0	0
T55	0	14	0	0
T73	77257	11	0	0
T110	0	4	0	0
T112	9160	0	0	0
T114	0	7	0	0
T115	0	23	0	0
T116	0	1	0	0
T118	10705	0	0	0
T123	12713	0	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442410951	441597661	0	0
T1	27746	27237	0	0
T2	8495	8216	0	0
T3	11001	10780	0	0
T4	39533	39049	0	0
T9	13971	13711	0	0
T10	4853	4777	0	0
T11	10429	10352	0	0
T12	16443	16188	0	0
T13	10573	10360	0	0
T14	4734	4666	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442410951	441597661	0	0
T1	27746	27237	0	0
T2	8495	8216	0	0
T3	11001	10780	0	0
T4	39533	39049	0	0
T9	13971	13711	0	0
T10	4853	4777	0	0
T11	10429	10352	0	0
T12	16443	16188	0	0
T13	10573	10360	0	0
T14	4734	4666	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442410951	761141	0	0
T1	27746	1780	0	0
T2	8495	0	0	0
T3	11001	0	0	0
T4	39533	0	0	0
T9	13971	0	0	0
T10	4853	0	0	0
T11	10429	0	0	0
T12	16443	0	0	0
T13	10573	0	0	0
T14	4734	0	0	0
T18	0	17288	0	0
T41	0	12224	0	0
T55	0	3237	0	0
T74	0	38537	0	0
T92	0	4705	0	0
T99	0	11886	0	0
T100	0	14785	0	0
T135	0	6061	0	0
T149	0	1198	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442410951	10376945	0	0
T1	27746	18289	0	0
T2	8495	0	0	0
T3	11001	0	0	0
T4	39533	0	0	0
T9	13971	0	0	0
T10	4853	0	0	0
T11	10429	0	0	0
T12	16443	0	0	0
T13	10573	0	0	0
T14	4734	0	0	0
T18	0	111854	0	0
T41	0	166832	0	0
T55	0	54356	0	0
T74	0	328306	0	0
T91	0	22852	0	0
T92	0	73636	0	0
T93	0	3552	0	0
T99	0	91628	0	0
T100	0	455919	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442410951	441597661	0	0
T1	27746	27237	0	0
T2	8495	8216	0	0
T3	11001	10780	0	0
T4	39533	39049	0	0
T9	13971	13711	0	0
T10	4853	4777	0	0
T11	10429	10352	0	0
T12	16443	16188	0	0
T13	10573	10360	0	0
T14	4734	4666	0	0