SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync_escalate_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_owner_seed_sw_rw_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_seed_hw_rd_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_dft_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_check_byp_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.20 | 94.16 | 96.15 | 97.08 | 96.43 | 97.18 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.20 | 94.16 | 96.15 | 97.08 | 96.43 | 97.18 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.20 | 94.16 | 96.15 | 97.08 | 96.43 | 97.18 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.20 | 94.16 | 96.15 | 97.08 | 96.43 | 97.18 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.20 | 94.16 | 96.15 | 97.08 | 96.43 | 97.18 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.20 | 94.16 | 96.15 | 97.08 | 96.43 | 97.18 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
83.66 | 98.04 | 88.89 | 85.71 | 95.65 | 50.00 | u_tlul_lc_gate |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 17 | 17 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 16 | 16 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 8071 | 8071 | 0 | 0 |
OutputsKnown_A | 2147483647 | 2147483647 | 0 | 0 |
gen_flops.OutputDelay_A | 2147483647 | 2147483647 | 0 | 20754 |
gen_no_flops.OutputDelay_A | 442410951 | 441597661 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 8071 | 8071 | 0 | 0 |
T1 | 7 | 7 | 0 | 0 |
T2 | 7 | 7 | 0 | 0 |
T3 | 7 | 7 | 0 | 0 |
T4 | 7 | 7 | 0 | 0 |
T9 | 7 | 7 | 0 | 0 |
T10 | 7 | 7 | 0 | 0 |
T11 | 7 | 7 | 0 | 0 |
T12 | 7 | 7 | 0 | 0 |
T13 | 7 | 7 | 0 | 0 |
T14 | 7 | 7 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 0 |
T1 | 194222 | 190659 | 0 | 0 |
T2 | 59465 | 57512 | 0 | 0 |
T3 | 77007 | 75460 | 0 | 0 |
T4 | 276731 | 273343 | 0 | 0 |
T9 | 97797 | 95977 | 0 | 0 |
T10 | 33971 | 33439 | 0 | 0 |
T11 | 73003 | 72464 | 0 | 0 |
T12 | 115101 | 113316 | 0 | 0 |
T13 | 74011 | 72520 | 0 | 0 |
T14 | 33138 | 32662 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 20754 |
T1 | 166476 | 163278 | 0 | 18 |
T2 | 50970 | 49224 | 0 | 18 |
T3 | 66006 | 64608 | 0 | 18 |
T4 | 237198 | 234168 | 0 | 18 |
T9 | 83826 | 82194 | 0 | 18 |
T10 | 29118 | 28644 | 0 | 18 |
T11 | 62574 | 62094 | 0 | 18 |
T12 | 98658 | 97056 | 0 | 18 |
T13 | 63438 | 62106 | 0 | 18 |
T14 | 28404 | 27978 | 0 | 18 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 442410951 | 441597661 | 0 | 0 |
T1 | 27746 | 27237 | 0 | 0 |
T2 | 8495 | 8216 | 0 | 0 |
T3 | 11001 | 10780 | 0 | 0 |
T4 | 39533 | 39049 | 0 | 0 |
T9 | 13971 | 13711 | 0 | 0 |
T10 | 4853 | 4777 | 0 | 0 |
T11 | 10429 | 10352 | 0 | 0 |
T12 | 16443 | 16188 | 0 | 0 |
T13 | 10573 | 10360 | 0 | 0 |
T14 | 4734 | 4666 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 17 | 17 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 16 | 16 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1153 | 1153 | 0 | 0 |
OutputsKnown_A | 442410951 | 441597661 | 0 | 0 |
gen_flops.OutputDelay_A | 442410951 | 441559460 | 0 | 3459 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1153 | 1153 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 442410951 | 441597661 | 0 | 0 |
T1 | 27746 | 27237 | 0 | 0 |
T2 | 8495 | 8216 | 0 | 0 |
T3 | 11001 | 10780 | 0 | 0 |
T4 | 39533 | 39049 | 0 | 0 |
T9 | 13971 | 13711 | 0 | 0 |
T10 | 4853 | 4777 | 0 | 0 |
T11 | 10429 | 10352 | 0 | 0 |
T12 | 16443 | 16188 | 0 | 0 |
T13 | 10573 | 10360 | 0 | 0 |
T14 | 4734 | 4666 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 442410951 | 441559460 | 0 | 3459 |
T1 | 27746 | 27213 | 0 | 3 |
T2 | 8495 | 8204 | 0 | 3 |
T3 | 11001 | 10768 | 0 | 3 |
T4 | 39533 | 39028 | 0 | 3 |
T9 | 13971 | 13699 | 0 | 3 |
T10 | 4853 | 4774 | 0 | 3 |
T11 | 10429 | 10349 | 0 | 3 |
T12 | 16443 | 16176 | 0 | 3 |
T13 | 10573 | 10351 | 0 | 3 |
T14 | 4734 | 4663 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1153 | 1153 | 0 | 0 |
OutputsKnown_A | 442410951 | 441597661 | 0 | 0 |
gen_flops.OutputDelay_A | 442410951 | 441559460 | 0 | 3459 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1153 | 1153 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 442410951 | 441597661 | 0 | 0 |
T1 | 27746 | 27237 | 0 | 0 |
T2 | 8495 | 8216 | 0 | 0 |
T3 | 11001 | 10780 | 0 | 0 |
T4 | 39533 | 39049 | 0 | 0 |
T9 | 13971 | 13711 | 0 | 0 |
T10 | 4853 | 4777 | 0 | 0 |
T11 | 10429 | 10352 | 0 | 0 |
T12 | 16443 | 16188 | 0 | 0 |
T13 | 10573 | 10360 | 0 | 0 |
T14 | 4734 | 4666 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 442410951 | 441559460 | 0 | 3459 |
T1 | 27746 | 27213 | 0 | 3 |
T2 | 8495 | 8204 | 0 | 3 |
T3 | 11001 | 10768 | 0 | 3 |
T4 | 39533 | 39028 | 0 | 3 |
T9 | 13971 | 13699 | 0 | 3 |
T10 | 4853 | 4774 | 0 | 3 |
T11 | 10429 | 10349 | 0 | 3 |
T12 | 16443 | 16176 | 0 | 3 |
T13 | 10573 | 10351 | 0 | 3 |
T14 | 4734 | 4663 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1153 | 1153 | 0 | 0 |
OutputsKnown_A | 442410951 | 441597661 | 0 | 0 |
gen_flops.OutputDelay_A | 442410951 | 441559460 | 0 | 3459 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1153 | 1153 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 442410951 | 441597661 | 0 | 0 |
T1 | 27746 | 27237 | 0 | 0 |
T2 | 8495 | 8216 | 0 | 0 |
T3 | 11001 | 10780 | 0 | 0 |
T4 | 39533 | 39049 | 0 | 0 |
T9 | 13971 | 13711 | 0 | 0 |
T10 | 4853 | 4777 | 0 | 0 |
T11 | 10429 | 10352 | 0 | 0 |
T12 | 16443 | 16188 | 0 | 0 |
T13 | 10573 | 10360 | 0 | 0 |
T14 | 4734 | 4666 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 442410951 | 441559460 | 0 | 3459 |
T1 | 27746 | 27213 | 0 | 3 |
T2 | 8495 | 8204 | 0 | 3 |
T3 | 11001 | 10768 | 0 | 3 |
T4 | 39533 | 39028 | 0 | 3 |
T9 | 13971 | 13699 | 0 | 3 |
T10 | 4853 | 4774 | 0 | 3 |
T11 | 10429 | 10349 | 0 | 3 |
T12 | 16443 | 16176 | 0 | 3 |
T13 | 10573 | 10351 | 0 | 3 |
T14 | 4734 | 4663 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1153 | 1153 | 0 | 0 |
OutputsKnown_A | 442410951 | 441597661 | 0 | 0 |
gen_flops.OutputDelay_A | 442410951 | 441559460 | 0 | 3459 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1153 | 1153 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 442410951 | 441597661 | 0 | 0 |
T1 | 27746 | 27237 | 0 | 0 |
T2 | 8495 | 8216 | 0 | 0 |
T3 | 11001 | 10780 | 0 | 0 |
T4 | 39533 | 39049 | 0 | 0 |
T9 | 13971 | 13711 | 0 | 0 |
T10 | 4853 | 4777 | 0 | 0 |
T11 | 10429 | 10352 | 0 | 0 |
T12 | 16443 | 16188 | 0 | 0 |
T13 | 10573 | 10360 | 0 | 0 |
T14 | 4734 | 4666 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 442410951 | 441559460 | 0 | 3459 |
T1 | 27746 | 27213 | 0 | 3 |
T2 | 8495 | 8204 | 0 | 3 |
T3 | 11001 | 10768 | 0 | 3 |
T4 | 39533 | 39028 | 0 | 3 |
T9 | 13971 | 13699 | 0 | 3 |
T10 | 4853 | 4774 | 0 | 3 |
T11 | 10429 | 10349 | 0 | 3 |
T12 | 16443 | 16176 | 0 | 3 |
T13 | 10573 | 10351 | 0 | 3 |
T14 | 4734 | 4663 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1153 | 1153 | 0 | 0 |
OutputsKnown_A | 442410951 | 441597661 | 0 | 0 |
gen_flops.OutputDelay_A | 442410951 | 441559460 | 0 | 3459 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1153 | 1153 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 442410951 | 441597661 | 0 | 0 |
T1 | 27746 | 27237 | 0 | 0 |
T2 | 8495 | 8216 | 0 | 0 |
T3 | 11001 | 10780 | 0 | 0 |
T4 | 39533 | 39049 | 0 | 0 |
T9 | 13971 | 13711 | 0 | 0 |
T10 | 4853 | 4777 | 0 | 0 |
T11 | 10429 | 10352 | 0 | 0 |
T12 | 16443 | 16188 | 0 | 0 |
T13 | 10573 | 10360 | 0 | 0 |
T14 | 4734 | 4666 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 442410951 | 441559460 | 0 | 3459 |
T1 | 27746 | 27213 | 0 | 3 |
T2 | 8495 | 8204 | 0 | 3 |
T3 | 11001 | 10768 | 0 | 3 |
T4 | 39533 | 39028 | 0 | 3 |
T9 | 13971 | 13699 | 0 | 3 |
T10 | 4853 | 4774 | 0 | 3 |
T11 | 10429 | 10349 | 0 | 3 |
T12 | 16443 | 16176 | 0 | 3 |
T13 | 10573 | 10351 | 0 | 3 |
T14 | 4734 | 4663 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1153 | 1153 | 0 | 0 |
OutputsKnown_A | 442410951 | 441597661 | 0 | 0 |
gen_flops.OutputDelay_A | 442410951 | 441559460 | 0 | 3459 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1153 | 1153 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 442410951 | 441597661 | 0 | 0 |
T1 | 27746 | 27237 | 0 | 0 |
T2 | 8495 | 8216 | 0 | 0 |
T3 | 11001 | 10780 | 0 | 0 |
T4 | 39533 | 39049 | 0 | 0 |
T9 | 13971 | 13711 | 0 | 0 |
T10 | 4853 | 4777 | 0 | 0 |
T11 | 10429 | 10352 | 0 | 0 |
T12 | 16443 | 16188 | 0 | 0 |
T13 | 10573 | 10360 | 0 | 0 |
T14 | 4734 | 4666 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 442410951 | 441559460 | 0 | 3459 |
T1 | 27746 | 27213 | 0 | 3 |
T2 | 8495 | 8204 | 0 | 3 |
T3 | 11001 | 10768 | 0 | 3 |
T4 | 39533 | 39028 | 0 | 3 |
T9 | 13971 | 13699 | 0 | 3 |
T10 | 4853 | 4774 | 0 | 3 |
T11 | 10429 | 10349 | 0 | 3 |
T12 | 16443 | 16176 | 0 | 3 |
T13 | 10573 | 10351 | 0 | 3 |
T14 | 4734 | 4663 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1153 | 1153 | 0 | 0 |
OutputsKnown_A | 442410951 | 441597661 | 0 | 0 |
gen_no_flops.OutputDelay_A | 442410951 | 441597661 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1153 | 1153 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 442410951 | 441597661 | 0 | 0 |
T1 | 27746 | 27237 | 0 | 0 |
T2 | 8495 | 8216 | 0 | 0 |
T3 | 11001 | 10780 | 0 | 0 |
T4 | 39533 | 39049 | 0 | 0 |
T9 | 13971 | 13711 | 0 | 0 |
T10 | 4853 | 4777 | 0 | 0 |
T11 | 10429 | 10352 | 0 | 0 |
T12 | 16443 | 16188 | 0 | 0 |
T13 | 10573 | 10360 | 0 | 0 |
T14 | 4734 | 4666 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 442410951 | 441597661 | 0 | 0 |
T1 | 27746 | 27237 | 0 | 0 |
T2 | 8495 | 8216 | 0 | 0 |
T3 | 11001 | 10780 | 0 | 0 |
T4 | 39533 | 39049 | 0 | 0 |
T9 | 13971 | 13711 | 0 | 0 |
T10 | 4853 | 4777 | 0 | 0 |
T11 | 10429 | 10352 | 0 | 0 |
T12 | 16443 | 16188 | 0 | 0 |
T13 | 10573 | 10360 | 0 | 0 |
T14 | 4734 | 4666 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |