Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.21	94.16	96.15	97.14		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.21	94.16	96.15	97.14		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T176,T83,T53

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T8,T10
1	Covered	T44,T175,T76

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T8,T9
1	Covered	T24,T25,T26

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T177,T178
1	Covered	T177,T178

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T8,T9
1	Covered	T2,T9,T10

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T10

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T9,T12
1	1	Covered	T2,T8,T10

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b10001111000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T2,T3,T8

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T8,T10
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T8,T10
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T17,T32

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T17,T32

---

FSM Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T8,T9
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T2,T3,T8
ReadWaitSt	252	Covered	T2,T8,T10
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T9,T10,T11
IdleSt->ReadSt	236	Covered	T2,T3,T8
InitSt->ErrorSt	315	Covered	T2,T121,T185
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T8,T99,T111
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T3,T5,T6
ReadSt->ReadWaitSt	252	Covered	T2,T8,T10
ReadWaitSt->ErrorSt	276	Covered	T175,T222,T221
ReadWaitSt->IdleSt	270	Covered	T2,T8,T10
ResetSt->ErrorSt	315	Covered	T79,T80,T81
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T3,T5,T6
CheckFailError	317	Covered	T177,T178
FsmStateError	289	Covered	T2,T9,T10
MacroEccCorrError	221	Covered	T44,T175,T76
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T5,T6,T7
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T3,T5,T6
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T177,T178
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T2,T9,T10
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T175,T176,T83
MacroEccCorrError->NoError	235	Covered	T44,T175,T76
NoError->AccessError	256	Covered	T3,T5,T6
NoError->CheckFailError	317	Covered	T177,T178
NoError->FsmStateError	289	Covered	T2,T9,T10
NoError->MacroEccCorrError	221	Covered	T44,T175,T76

---

Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T8,T10

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T8,T10

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T17,T32
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T176,T83,T53
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T8,T115,T182
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T8
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T8,T10
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T7,T102,T21
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T3,T5,T6
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T44,T175,T76
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T8,T10
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T175,T222,T221
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T8,T10
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T24,T25,T26
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T8,T9
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T9,T12,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T9,T12,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T24,T25,T26

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T177,T178
1	0	Covered	T177,T178
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T9,T10
1	0	Covered	T2,T8,T9
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	449862962	448988665	0	0
DigestKnown_A	449862962	448988665	0	0
DigestOffsetMustBeRepresentable_A	1146	1146	0	0
EccErrorState_A	449862962	6083	0	0
ErrorKnown_A	449862962	448988665	0	0
FsmStateKnown_A	449862962	448988665	0	0
InitDoneKnown_A	449862962	448988665	0	0
InitReadLocksPartition_A	449862962	77182877	0	0
InitWriteLocksPartition_A	449862962	77182877	0	0
OffsetMustBeBlockAligned_A	1146	1146	0	0
OtpAddrKnown_A	449862962	448988665	0	0
OtpCmdKnown_A	449862962	448988665	0	0
OtpErrorState_A	449862962	42	0	0
OtpReqKnown_A	449862962	448988665	0	0
OtpSizeKnown_A	449862962	448988665	0	0
OtpWdataKnown_A	449862962	448988665	0	0
ReadLockPropagation_A	449862962	179477766	0	0
SizeMustBeBlockAligned_A	1146	1146	0	0
TlulGntKnown_A	449862962	448988665	0	0
TlulRdataKnown_A	449862962	448988665	0	0
TlulReadOnReadLock_A	449862962	7838	0	0
TlulRerrorKnown_A	449862962	448988665	0	0
TlulRvalidKnown_A	449862962	448988665	0	0
WriteLockPropagation_A	449862962	1970741	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	449862962	27823288	0	0
u_state_regs_A	449862962	448988665	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449862962	448988665	0	0
T1	24042	23541	0	0
T2	9637	9387	0	0
T3	20939	20714	0	0
T5	15417	15221	0	0
T8	11937	11675	0	0
T9	23647	23380	0	0
T10	11375	11077	0	0
T11	18983	18714	0	0
T12	5982	5760	0	0
T13	16807	16535	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449862962	448988665	0	0
T1	24042	23541	0	0
T2	9637	9387	0	0
T3	20939	20714	0	0
T5	15417	15221	0	0
T8	11937	11675	0	0
T9	23647	23380	0	0
T10	11375	11077	0	0
T11	18983	18714	0	0
T12	5982	5760	0	0
T13	16807	16535	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1146	1146	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449862962	6083	0	0
T68	28493	0	0	0
T92	46572	0	0	0
T144	122206	0	0	0
T164	37200	0	0	0
T177	11127	3043	0	0
T178	0	3040	0	0
T223	9951	0	0	0
T224	67388	0	0	0
T225	12572	0	0	0
T226	27529	0	0	0
T227	815952	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449862962	448988665	0	0
T1	24042	23541	0	0
T2	9637	9387	0	0
T3	20939	20714	0	0
T5	15417	15221	0	0
T8	11937	11675	0	0
T9	23647	23380	0	0
T10	11375	11077	0	0
T11	18983	18714	0	0
T12	5982	5760	0	0
T13	16807	16535	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449862962	448988665	0	0
T1	24042	23541	0	0
T2	9637	9387	0	0
T3	20939	20714	0	0
T5	15417	15221	0	0
T8	11937	11675	0	0
T9	23647	23380	0	0
T10	11375	11077	0	0
T11	18983	18714	0	0
T12	5982	5760	0	0
T13	16807	16535	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449862962	448988665	0	0
T1	24042	23541	0	0
T2	9637	9387	0	0
T3	20939	20714	0	0
T5	15417	15221	0	0
T8	11937	11675	0	0
T9	23647	23380	0	0
T10	11375	11077	0	0
T11	18983	18714	0	0
T12	5982	5760	0	0
T13	16807	16535	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449862962	77182877	0	0
T1	24042	1823	0	0
T2	9637	4306	0	0
T3	20939	247	0	0
T5	15417	4667	0	0
T8	11937	4593	0	0
T9	23647	14811	0	0
T10	11375	4560	0	0
T11	18983	4070	0	0
T12	5982	862	0	0
T13	16807	6158	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449862962	77182877	0	0
T1	24042	1823	0	0
T2	9637	4306	0	0
T3	20939	247	0	0
T5	15417	4667	0	0
T8	11937	4593	0	0
T9	23647	14811	0	0
T10	11375	4560	0	0
T11	18983	4070	0	0
T12	5982	862	0	0
T13	16807	6158	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1146	1146	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449862962	448988665	0	0
T1	24042	23541	0	0
T2	9637	9387	0	0
T3	20939	20714	0	0
T5	15417	15221	0	0
T8	11937	11675	0	0
T9	23647	23380	0	0
T10	11375	11077	0	0
T11	18983	18714	0	0
T12	5982	5760	0	0
T13	16807	16535	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449862962	448988665	0	0
T1	24042	23541	0	0
T2	9637	9387	0	0
T3	20939	20714	0	0
T5	15417	15221	0	0
T8	11937	11675	0	0
T9	23647	23380	0	0
T10	11375	11077	0	0
T11	18983	18714	0	0
T12	5982	5760	0	0
T13	16807	16535	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449862962	42	0	0
T4	647820	0	0	0
T5	15417	0	0	0
T6	975364	0	0	0
T8	11937	1	0	0
T9	23647	0	0	0
T10	11375	0	0	0
T11	18983	0	0	0
T12	5982	0	0	0
T13	16807	0	0	0
T48	10844	0	0	0
T115	0	1	0	0
T175	0	1	0	0
T182	0	1	0	0
T222	0	2	0	0
T228	0	1	0	0
T229	0	1	0	0
T230	0	1	0	0
T231	0	1	0	0
T232	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449862962	448988665	0	0
T1	24042	23541	0	0
T2	9637	9387	0	0
T3	20939	20714	0	0
T5	15417	15221	0	0
T8	11937	11675	0	0
T9	23647	23380	0	0
T10	11375	11077	0	0
T11	18983	18714	0	0
T12	5982	5760	0	0
T13	16807	16535	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449862962	448988665	0	0
T1	24042	23541	0	0
T2	9637	9387	0	0
T3	20939	20714	0	0
T5	15417	15221	0	0
T8	11937	11675	0	0
T9	23647	23380	0	0
T10	11375	11077	0	0
T11	18983	18714	0	0
T12	5982	5760	0	0
T13	16807	16535	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449862962	448988665	0	0
T1	24042	23541	0	0
T2	9637	9387	0	0
T3	20939	20714	0	0
T5	15417	15221	0	0
T8	11937	11675	0	0
T9	23647	23380	0	0
T10	11375	11077	0	0
T11	18983	18714	0	0
T12	5982	5760	0	0
T13	16807	16535	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449862962	179477766	0	0
T3	20939	5380	0	0
T4	647820	0	0	0
T5	15417	8049	0	0
T6	975364	848006	0	0
T7	0	250711	0	0
T8	11937	0	0	0
T9	23647	0	0	0
T10	11375	0	0	0
T11	18983	0	0	0
T12	5982	0	0	0
T13	16807	0	0	0
T17	0	36407	0	0
T19	0	15504	0	0
T32	0	19074	0	0
T98	0	6557	0	0
T119	0	4982	0	0
T121	0	3249	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1146	1146	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449862962	448988665	0	0
T1	24042	23541	0	0
T2	9637	9387	0	0
T3	20939	20714	0	0
T5	15417	15221	0	0
T8	11937	11675	0	0
T9	23647	23380	0	0
T10	11375	11077	0	0
T11	18983	18714	0	0
T12	5982	5760	0	0
T13	16807	16535	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449862962	448988665	0	0
T1	24042	23541	0	0
T2	9637	9387	0	0
T3	20939	20714	0	0
T5	15417	15221	0	0
T8	11937	11675	0	0
T9	23647	23380	0	0
T10	11375	11077	0	0
T11	18983	18714	0	0
T12	5982	5760	0	0
T13	16807	16535	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449862962	7838	0	0
T3	20939	2	0	0
T4	647820	11	0	0
T5	15417	9	0	0
T6	975364	71	0	0
T8	11937	0	0	0
T9	23647	2	0	0
T10	11375	0	0	0
T11	18983	0	0	0
T12	5982	2	0	0
T13	16807	0	0	0
T32	0	3	0	0
T98	0	6	0	0
T100	0	2	0	0
T101	0	1	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449862962	448988665	0	0
T1	24042	23541	0	0
T2	9637	9387	0	0
T3	20939	20714	0	0
T5	15417	15221	0	0
T8	11937	11675	0	0
T9	23647	23380	0	0
T10	11375	11077	0	0
T11	18983	18714	0	0
T12	5982	5760	0	0
T13	16807	16535	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449862962	448988665	0	0
T1	24042	23541	0	0
T2	9637	9387	0	0
T3	20939	20714	0	0
T5	15417	15221	0	0
T8	11937	11675	0	0
T9	23647	23380	0	0
T10	11375	11077	0	0
T11	18983	18714	0	0
T12	5982	5760	0	0
T13	16807	16535	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449862962	1970741	0	0
T7	801656	31700	0	0
T19	90898	5128	0	0
T43	0	3876	0	0
T46	15975	0	0	0
T51	13411	0	0	0
T73	34646	0	0	0
T102	0	54274	0	0
T104	0	11509	0	0
T105	0	1825	0	0
T107	0	2854	0	0
T110	36712	0	0	0
T111	15490	0	0	0
T112	9934	0	0	0
T113	79111	0	0	0
T114	10991	0	0	0
T116	0	2678	0	0
T117	0	2896	0	0
T127	0	5537	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449862962	27823288	0	0
T4	647820	0	0	0
T5	15417	0	0	0
T6	975364	0	0	0
T7	0	384873	0	0
T8	11937	3190	0	0
T9	23647	0	0	0
T10	11375	0	0	0
T11	18983	0	0	0
T12	5982	0	0	0
T13	16807	0	0	0
T17	0	59521	0	0
T19	0	79668	0	0
T32	0	31677	0	0
T43	0	33063	0	0
T48	10844	0	0	0
T113	0	16128	0	0
T119	0	34049	0	0
T121	0	4065	0	0
T182	0	2914	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449862962	448988665	0	0
T1	24042	23541	0	0
T2	9637	9387	0	0
T3	20939	20714	0	0
T5	15417	15221	0	0
T8	11937	11675	0	0
T9	23647	23380	0	0
T10	11375	11077	0	0
T11	18983	18714	0	0
T12	5982	5760	0	0
T13	16807	16535	0	0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T60,T39,T93

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T8,T10
1	Covered	T3,T98,T75

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T8,T9
1	Covered	T24,T25,T26

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T179,T177,T184
1	Covered	T179,T177,T184

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T8,T9
1	Covered	T2,T8,T9

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T5,T4
1	1	Covered	T2,T3,T8

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b11001010000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T2,T3,T8

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T8
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T3,T8
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T32

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T32

---

FSM Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T8,T9
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T2,T3,T8
ReadWaitSt	252	Covered	T2,T3,T8
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T9,T10,T11
IdleSt->ReadSt	236	Covered	T2,T3,T8
InitSt->ErrorSt	315	Covered	T2,T99,T121
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T8,T115,T182
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T5,T6,T17
ReadSt->ReadWaitSt	252	Covered	T2,T3,T8
ReadWaitSt->ErrorSt	276	Covered	T209,T222,T233
ReadWaitSt->IdleSt	270	Covered	T2,T3,T8
ResetSt->ErrorSt	315	Covered	T79,T80,T81
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T5,T6,T17
CheckFailError	317	Covered	T179,T177,T184
FsmStateError	289	Covered	T2,T8,T9
MacroEccCorrError	221	Covered	T3,T98,T60
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T5,T6,T7
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T5,T6,T17
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T179,T177,T184
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T2,T8,T9
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T98,T60,T39
MacroEccCorrError->NoError	235	Covered	T3,T75,T44
NoError->AccessError	256	Covered	T5,T6,T17
NoError->CheckFailError	317	Covered	T179,T177,T184
NoError->FsmStateError	289	Covered	T2,T8,T9
NoError->MacroEccCorrError	221	Covered	T3,T98,T60

---

Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T8

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T8

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T32
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T60,T39,T93
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T180,T234,T235
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T8
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T8
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T6,T7,T102
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T5,T6,T17
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T3,T98,T75
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T8,T10
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T209,T222,T233
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T24,T25,T26
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T8,T9
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T9,T5,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T9,T5,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T24,T25,T26

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T179,T177,T184
1	0	Covered	T179,T177,T184
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T8,T9
1	0	Covered	T2,T8,T9
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	449862962	448988665	0	0
DigestKnown_A	449862962	448988665	0	0
DigestOffsetMustBeRepresentable_A	1146	1146	0	0
EccErrorState_A	449862962	9580	0	0
ErrorKnown_A	449862962	448988665	0	0
FsmStateKnown_A	449862962	448988665	0	0
InitDoneKnown_A	449862962	448988665	0	0
InitReadLocksPartition_A	449862962	77362908	0	0
InitWriteLocksPartition_A	449862962	77362908	0	0
OffsetMustBeBlockAligned_A	1146	1146	0	0
OtpAddrKnown_A	449862962	448988665	0	0
OtpCmdKnown_A	449862962	448988665	0	0
OtpErrorState_A	449862962	43	0	0
OtpReqKnown_A	449862962	448988665	0	0
OtpSizeKnown_A	449862962	448988665	0	0
OtpWdataKnown_A	449862962	448988665	0	0
ReadLockPropagation_A	449862962	185312699	0	0
SizeMustBeBlockAligned_A	1146	1146	0	0
TlulGntKnown_A	449862962	448988665	0	0
TlulRdataKnown_A	449862962	448988665	0	0
TlulReadOnReadLock_A	449862962	7541	0	0
TlulRerrorKnown_A	449862962	448988665	0	0
TlulRvalidKnown_A	449862962	448988665	0	0
WriteLockPropagation_A	449862962	1295877	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	449862962	12045881	0	0
u_state_regs_A	449862962	448988665	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449862962	448988665	0	0
T1	24042	23541	0	0
T2	9637	9387	0	0
T3	20939	20714	0	0
T5	15417	15221	0	0
T8	11937	11675	0	0
T9	23647	23380	0	0
T10	11375	11077	0	0
T11	18983	18714	0	0
T12	5982	5760	0	0
T13	16807	16535	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449862962	448988665	0	0
T1	24042	23541	0	0
T2	9637	9387	0	0
T3	20939	20714	0	0
T5	15417	15221	0	0
T8	11937	11675	0	0
T9	23647	23380	0	0
T10	11375	11077	0	0
T11	18983	18714	0	0
T12	5982	5760	0	0
T13	16807	16535	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1146	1146	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449862962	9580	0	0
T27	17650	0	0	0
T63	125742	0	0	0
T177	0	3043	0	0
T179	10082	3360	0	0
T184	0	3177	0	0
T236	13172	0	0	0
T237	689039	0	0	0
T238	12308	0	0	0
T239	12856	0	0	0
T240	46290	0	0	0
T241	61579	0	0	0
T242	175013	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449862962	448988665	0	0
T1	24042	23541	0	0
T2	9637	9387	0	0
T3	20939	20714	0	0
T5	15417	15221	0	0
T8	11937	11675	0	0
T9	23647	23380	0	0
T10	11375	11077	0	0
T11	18983	18714	0	0
T12	5982	5760	0	0
T13	16807	16535	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449862962	448988665	0	0
T1	24042	23541	0	0
T2	9637	9387	0	0
T3	20939	20714	0	0
T5	15417	15221	0	0
T8	11937	11675	0	0
T9	23647	23380	0	0
T10	11375	11077	0	0
T11	18983	18714	0	0
T12	5982	5760	0	0
T13	16807	16535	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449862962	448988665	0	0
T1	24042	23541	0	0
T2	9637	9387	0	0
T3	20939	20714	0	0
T5	15417	15221	0	0
T8	11937	11675	0	0
T9	23647	23380	0	0
T10	11375	11077	0	0
T11	18983	18714	0	0
T12	5982	5760	0	0
T13	16807	16535	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449862962	77362908	0	0
T1	24042	1906	0	0
T2	9637	4323	0	0
T3	20939	281	0	0
T5	15417	4701	0	0
T8	11937	4627	0	0
T9	23647	14862	0	0
T10	11375	4594	0	0
T11	18983	4121	0	0
T12	5982	896	0	0
T13	16807	6192	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449862962	77362908	0	0
T1	24042	1906	0	0
T2	9637	4323	0	0
T3	20939	281	0	0
T5	15417	4701	0	0
T8	11937	4627	0	0
T9	23647	14862	0	0
T10	11375	4594	0	0
T11	18983	4121	0	0
T12	5982	896	0	0
T13	16807	6192	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1146	1146	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449862962	448988665	0	0
T1	24042	23541	0	0
T2	9637	9387	0	0
T3	20939	20714	0	0
T5	15417	15221	0	0
T8	11937	11675	0	0
T9	23647	23380	0	0
T10	11375	11077	0	0
T11	18983	18714	0	0
T12	5982	5760	0	0
T13	16807	16535	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449862962	448988665	0	0
T1	24042	23541	0	0
T2	9637	9387	0	0
T3	20939	20714	0	0
T5	15417	15221	0	0
T8	11937	11675	0	0
T9	23647	23380	0	0
T10	11375	11077	0	0
T11	18983	18714	0	0
T12	5982	5760	0	0
T13	16807	16535	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449862962	43	0	0
T39	9552	0	0	0
T44	122425	0	0	0
T75	40033	0	0	0
T116	48806	0	0	0
T176	0	1	0	0
T180	13163	1	0	0
T185	12511	0	0	0
T204	12879	0	0	0
T209	0	1	0	0
T222	0	1	0	0
T228	12995	0	0	0
T234	0	1	0	0
T235	0	1	0	0
T243	0	1	0	0
T244	0	1	0	0
T245	0	1	0	0
T246	0	1	0	0
T247	4714	0	0	0
T248	29351	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449862962	448988665	0	0
T1	24042	23541	0	0
T2	9637	9387	0	0
T3	20939	20714	0	0
T5	15417	15221	0	0
T8	11937	11675	0	0
T9	23647	23380	0	0
T10	11375	11077	0	0
T11	18983	18714	0	0
T12	5982	5760	0	0
T13	16807	16535	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449862962	448988665	0	0
T1	24042	23541	0	0
T2	9637	9387	0	0
T3	20939	20714	0	0
T5	15417	15221	0	0
T8	11937	11675	0	0
T9	23647	23380	0	0
T10	11375	11077	0	0
T11	18983	18714	0	0
T12	5982	5760	0	0
T13	16807	16535	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449862962	448988665	0	0
T1	24042	23541	0	0
T2	9637	9387	0	0
T3	20939	20714	0	0
T5	15417	15221	0	0
T8	11937	11675	0	0
T9	23647	23380	0	0
T10	11375	11077	0	0
T11	18983	18714	0	0
T12	5982	5760	0	0
T13	16807	16535	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449862962	185312699	0	0
T4	647820	8528	0	0
T5	15417	8047	0	0
T6	975364	124748	0	0
T7	0	136141	0	0
T13	16807	0	0	0
T17	97371	30102	0	0
T19	0	15448	0	0
T32	0	19058	0	0
T48	10844	0	0	0
T60	15231	0	0	0
T98	160026	5274	0	0
T99	10210	0	0	0
T100	23290	0	0	0
T119	0	4423	0	0
T121	0	3247	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1146	1146	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449862962	448988665	0	0
T1	24042	23541	0	0
T2	9637	9387	0	0
T3	20939	20714	0	0
T5	15417	15221	0	0
T8	11937	11675	0	0
T9	23647	23380	0	0
T10	11375	11077	0	0
T11	18983	18714	0	0
T12	5982	5760	0	0
T13	16807	16535	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449862962	448988665	0	0
T1	24042	23541	0	0
T2	9637	9387	0	0
T3	20939	20714	0	0
T5	15417	15221	0	0
T8	11937	11675	0	0
T9	23647	23380	0	0
T10	11375	11077	0	0
T11	18983	18714	0	0
T12	5982	5760	0	0
T13	16807	16535	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449862962	7541	0	0
T4	647820	21	0	0
T5	15417	9	0	0
T6	975364	68	0	0
T9	23647	2	0	0
T10	11375	0	0	0
T11	18983	0	0	0
T12	5982	0	0	0
T13	16807	0	0	0
T17	0	8	0	0
T32	0	4	0	0
T48	10844	0	0	0
T98	160026	6	0	0
T100	0	4	0	0
T101	0	3	0	0
T119	0	1	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449862962	448988665	0	0
T1	24042	23541	0	0
T2	9637	9387	0	0
T3	20939	20714	0	0
T5	15417	15221	0	0
T8	11937	11675	0	0
T9	23647	23380	0	0
T10	11375	11077	0	0
T11	18983	18714	0	0
T12	5982	5760	0	0
T13	16807	16535	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449862962	448988665	0	0
T1	24042	23541	0	0
T2	9637	9387	0	0
T3	20939	20714	0	0
T5	15417	15221	0	0
T8	11937	11675	0	0
T9	23647	23380	0	0
T10	11375	11077	0	0
T11	18983	18714	0	0
T12	5982	5760	0	0
T13	16807	16535	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449862962	1295877	0	0
T7	801656	35127	0	0
T19	90898	5128	0	0
T32	51825	17080	0	0
T44	0	7999	0	0
T51	13411	0	0	0
T73	34646	0	0	0
T102	0	15019	0	0
T107	0	3391	0	0
T109	0	8320	0	0
T110	36712	0	0	0
T118	0	12456	0	0
T119	41718	0	0	0
T120	32562	0	0	0
T121	22974	0	0	0
T137	27639	0	0	0
T215	0	6844	0	0
T216	0	34547	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449862962	12045881	0	0
T3	20939	6808	0	0
T4	647820	5502	0	0
T5	15417	0	0	0
T6	975364	0	0	0
T7	0	124659	0	0
T8	11937	0	0	0
T9	23647	0	0	0
T10	11375	0	0	0
T11	18983	0	0	0
T12	5982	0	0	0
T13	16807	0	0	0
T19	0	79447	0	0
T32	0	31609	0	0
T44	0	110193	0	0
T102	0	130393	0	0
T113	0	2382	0	0
T119	0	23588	0	0
T180	0	3100	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449862962	448988665	0	0
T1	24042	23541	0	0
T2	9637	9387	0	0
T3	20939	20714	0	0
T5	15417	15221	0	0
T8	11937	11675	0	0
T9	23647	23380	0	0
T10	11375	11077	0	0
T11	18983	18714	0	0
T12	5982	5760	0	0
T13	16807	16535	0	0