Unified Coverage Report

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ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.EccKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.RDataOutKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.WidthMustBe64bit_A	0	0	1155	1155	0	0
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre.OutputsKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre.OutputsKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_state_regs.AssertConnected_A	0	0	1155	1155	0	0
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_state_regs_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[5].gen_buffered.FpvSecCmCntPartBufCheck_A	0	0	462772914	50	0	0
tb.dut.gen_partitions[5].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	0	0	462772914	50	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.AccessKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.BypassEnable1_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.CnstyChkAckKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.DataKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.DigestKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.DigestOffsetMustBeRepresentable_A	0	0	1155	1155	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.ErrorKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.InitDoneKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.InitReadLocksPartition_A	0	0	462772914	133714539	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.InitWriteLocksPartition_A	0	0	462772914	133714539	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.IntegChkAckKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.OffsetMustBeBlockAligned_A	0	0	1155	1155	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.OtpAddrKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.OtpCmdKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.OtpPartBufSize_A	0	0	1155	1155	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.OtpReqKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.OtpSizeKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.OtpWdataKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.ReadLockImpliesDigest_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.ScrmblCmdKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.ScrmblDataKnown_A	0	0	460923596	460024231	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.ScrmblModeKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.ScrmblMtxReqKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.ScrmblSelKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.ScrmblValidKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.SizeMustBeBlockAligned_A	0	0	1155	1155	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.WriteLockPropagation_A	0	0	462772914	2814986	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.gen_digest_write_lock.DigestWriteLocksPartition_A	0	0	462772914	26924098	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock.OutputsKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.DataKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.DataOutKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.EccErrKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.EccKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.RDataOutKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.WidthMustBe64bit_A	0	0	1155	1155	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre.OutputsKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre.OutputsKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_state_regs.AssertConnected_A	0	0	1155	1155	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_state_regs_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[6].gen_buffered.FpvSecCmCntPartBufCheck_A	0	0	462772914	50	0	0
tb.dut.gen_partitions[6].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	0	0	462772914	50	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.AccessKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.BypassEnable1_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.CnstyChkAckKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.DataKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.DigestKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.DigestOffsetMustBeRepresentable_A	0	0	1155	1155	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.ErrorKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.InitDoneKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.InitReadLocksPartition_A	0	0	462772914	125535031	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.InitWriteLocksPartition_A	0	0	462772914	125535031	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.IntegChkAckKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.OffsetMustBeBlockAligned_A	0	0	1155	1155	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.OtpAddrKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.OtpCmdKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.OtpPartBufSize_A	0	0	1155	1155	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.OtpReqKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.OtpSizeKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.OtpWdataKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.ReadLockImpliesDigest_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.ScrmblCmdKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.ScrmblDataKnown_A	0	0	460923596	460024231	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.ScrmblModeKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.ScrmblMtxReqKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.ScrmblSelKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.ScrmblValidKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.SizeMustBeBlockAligned_A	0	0	1155	1155	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.WriteLockPropagation_A	0	0	462772914	2980256	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.gen_digest_write_lock.DigestWriteLocksPartition_A	0	0	462772914	30173918	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock.OutputsKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.DataKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.DataOutKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.EccErrKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.EccKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.RDataOutKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.WidthMustBe64bit_A	0	0	1155	1155	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre.OutputsKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre.OutputsKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_state_regs.AssertConnected_A	0	0	1155	1155	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_state_regs_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[7].gen_buffered.FpvSecCmCntPartBufCheck_A	0	0	462772914	50	0	0
tb.dut.gen_partitions[7].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	0	0	462772914	50	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.AccessKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.BypassEnable0_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.BypassEnable1_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.CnstyChkAckKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.DataKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.DigestKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.DigestOffsetMustBeRepresentable_A	0	0	1155	1155	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.ErrorKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.InitDoneKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.InitReadLocksPartition_A	0	0	462772914	131334155	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.InitWriteLocksPartition_A	0	0	462772914	131334155	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.IntegChkAckKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.OffsetMustBeBlockAligned_A	0	0	1155	1155	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.OtpAddrKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.OtpCmdKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.OtpPartBufSize_A	0	0	1155	1155	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.OtpReqKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.OtpSizeKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.OtpWdataKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.ReadLockImpliesDigest_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.ReadLockPropagation_A	0	0	462772914	2437663	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.ScrambledImpliesDigest_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.ScrmblCmdKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.ScrmblDataKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.ScrmblModeKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.ScrmblMtxReqKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.ScrmblSelKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.ScrmblValidKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.SizeMustBeBlockAligned_A	0	0	1155	1155	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.WriteLockImpliesDigest_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.WriteLockPropagation_A	0	0	462772914	2693566	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_read_lock.DigestReadLocksPartition_A	0	0	462772914	28520338	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock.OutputsKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_write_lock.DigestWriteLocksPartition_A	0	0	462772914	28520338	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock.OutputsKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.DataKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.DataOutKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.EccErrKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.EccKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.RDataOutKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.WidthMustBe64bit_A	0	0	1155	1155	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre.OutputsKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre.OutputsKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_state_regs.AssertConnected_A	0	0	1155	1155	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_state_regs_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[8].gen_buffered.FpvSecCmCntPartBufCheck_A	0	0	462772914	50	0	0
tb.dut.gen_partitions[8].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	0	0	462772914	50	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.AccessKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.BypassEnable0_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.BypassEnable1_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.CnstyChkAckKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.DataKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.DigestKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.DigestOffsetMustBeRepresentable_A	0	0	1155	1155	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.ErrorKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.InitDoneKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.InitReadLocksPartition_A	0	0	462772914	141975287	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.InitWriteLocksPartition_A	0	0	462772914	141975287	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.IntegChkAckKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.OffsetMustBeBlockAligned_A	0	0	1155	1155	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.OtpAddrKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.OtpCmdKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.OtpPartBufSize_A	0	0	1155	1155	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.OtpReqKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.OtpSizeKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.OtpWdataKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.ReadLockImpliesDigest_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.ReadLockPropagation_A	0	0	462772914	2195400	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.ScrambledImpliesDigest_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.ScrmblCmdKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.ScrmblDataKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.ScrmblModeKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.ScrmblMtxReqKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.ScrmblSelKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.ScrmblValidKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.SizeMustBeBlockAligned_A	0	0	1155	1155	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.WriteLockImpliesDigest_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.WriteLockPropagation_A	0	0	462772914	2565775	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_read_lock.DigestReadLocksPartition_A	0	0	462772914	24793588	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock.OutputsKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_write_lock.DigestWriteLocksPartition_A	0	0	462772914	24793588	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock.OutputsKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.DataKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.DataOutKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.EccErrKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.EccKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.RDataOutKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.WidthMustBe64bit_A	0	0	1155	1155	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre.OutputsKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre.OutputsKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_state_regs.AssertConnected_A	0	0	1155	1155	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_state_regs_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[9].gen_buffered.FpvSecCmCntPartBufCheck_A	0	0	462772914	50	0	0
tb.dut.gen_partitions[9].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	0	0	462772914	50	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.AccessKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.BypassEnable0_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.BypassEnable1_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.CnstyChkAckKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.DataKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.DigestKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.DigestOffsetMustBeRepresentable_A	0	0	1155	1155	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.ErrorKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.InitDoneKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.InitReadLocksPartition_A	0	0	462772914	146685552	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.InitWriteLocksPartition_A	0	0	462772914	146685552	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.IntegChkAckKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.OffsetMustBeBlockAligned_A	0	0	1155	1155	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.OtpAddrKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.OtpCmdKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.OtpPartBufSize_A	0	0	1155	1155	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.OtpReqKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.OtpSizeKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.OtpWdataKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.ReadLockImpliesDigest_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.ReadLockPropagation_A	0	0	462772914	259626206	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.ScrambledImpliesDigest_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.ScrmblCmdKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.ScrmblDataKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.ScrmblModeKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.ScrmblMtxReqKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.ScrmblSelKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.ScrmblValidKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.SizeMustBeBlockAligned_A	0	0	1155	1155	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.WriteLockImpliesDigest_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.WriteLockPropagation_A	0	0	462772914	259663361	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_read_lock.DigestReadLocksPartition_A	0	0	462772914	16649699	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock.OutputsKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_write_lock.DigestWriteLocksPartition_A	0	0	462772914	16649699	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock.OutputsKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.DataKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.DataOutKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.EccErrKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.EccKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.RDataOutKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.WidthMustBe64bit_A	0	0	1155	1155	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre.OutputsKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre.OutputsKnown_A	0	0	462772914	461830240	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_state_regs.AssertConnected_A	0	0	1155	1155	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_state_regs_A	0	0	462772914	461830240	0	0
tb.dut.gen_reg_we_assert_generic.FpvSecCmPrimFsmCheck_A	0	0	462772914	50	0	0
tb.dut.gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A	0	0	462772914	50	0	0
tb.dut.otp_ctrl_core_csr_assert.TlulOOBAddrErr_A	0	0	465736056	7508119	0	0
tb.dut.otp_ctrl_core_csr_assert.check_regwen_rd_A	0	0	465736056	3108	0	0
tb.dut.otp_ctrl_core_csr_assert.check_timeout_rd_A	0	0	465736056	2634	0	0
tb.dut.otp_ctrl_core_csr_assert.check_trigger_regwen_rd_A	0	0	465736056	3184	0	0
tb.dut.otp_ctrl_core_csr_assert.consistency_check_period_rd_A	0	0	465736056	3164	0	0
tb.dut.otp_ctrl_core_csr_assert.creator_sw_cfg_read_lock_rd_A	0	0	465736056	2454	0	0
tb.dut.otp_ctrl_core_csr_assert.direct_access_address_rd_A	0	0	465736056	2092	0	0
tb.dut.otp_ctrl_core_csr_assert.direct_access_wdata_0_rd_A	0	0	465736056	1419	0	0
tb.dut.otp_ctrl_core_csr_assert.direct_access_wdata_1_rd_A	0	0	465736056	1402	0	0
tb.dut.otp_ctrl_core_csr_assert.integrity_check_period_rd_A	0	0	465736056	3230	0	0
tb.dut.otp_ctrl_core_csr_assert.intr_enable_rd_A	0	0	465736056	4379	0	0
tb.dut.otp_ctrl_core_csr_assert.owner_sw_cfg_read_lock_rd_A	0	0	465736056	2343	0	0
tb.dut.otp_ctrl_core_csr_assert.rot_creator_auth_codesign_read_lock_rd_A	0	0	465736056	2425	0	0
tb.dut.otp_ctrl_core_csr_assert.rot_creator_auth_state_read_lock_rd_A	0	0	465736056	2432	0	0
tb.dut.otp_ctrl_core_csr_assert.vendor_test_read_lock_rd_A	0	0	465736056	2280	0	0
tb.dut.prim_tlul_assert_device.aKnown_A	0	0	465736056	31322844	0	0
tb.dut.prim_tlul_assert_device.aKnown_AKnownEnable	0	0	465736056	464743785	0	0
tb.dut.prim_tlul_assert_device.aReadyKnown_A	0	0	465736056	464743785	0	0
tb.dut.prim_tlul_assert_device.dKnown_A	0	0	465736056	32445214	0	0
tb.dut.prim_tlul_assert_device.dKnown_AKnownEnable	0	0	465736056	464743785	0	0
tb.dut.prim_tlul_assert_device.dReadyKnown_A	0	0	465736056	464743785	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	1329	1329	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	1329	1329	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	1329	1329	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	1329	1329	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	1329	1329	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	1329	1329	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	1329	1329	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	1329	1329	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	1329	1329	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	1329	1329	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	1329	1329	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	1329	1329	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	1329	1329	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	1329	1329	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	1329	1329	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	1329	1329	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A	0	0	1329	1329	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A	0	0	1329	1329	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A	0	0	1329	1329	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A	0	0	1329	1329	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A	0	0	1329	1329	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A	0	0	1329	1329	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A	0	0	1329	1329	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A	0	0	1329	1329	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A	0	0	1329	1329	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A	0	0	1329	1329	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A	0	0	1329	1329	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A	0	0	1329	1329	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A	0	0	1329	1329	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A	0	0	1329	1329	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A	0	0	1329	1329	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A	0	0	1329	1329	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A	0	0	1329	1329	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A	0	0	1329	1329	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A	0	0	1329	1329	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A	0	0	1329	1329	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A	0	0	1329	1329	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A	0	0	1329	1329	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A	0	0	1329	1329	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A	0	0	1329	1329	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A	0	0	1329	1329	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A	0	0	1329	1329	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A	0	0	1329	1329	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A	0	0	1329	1329	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A	0	0	1329	1329	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A	0	0	1329	1329	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A	0	0	1329	1329	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A	0	0	1329	1329	0	0
tb.dut.prim_tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A	0	0	1329	1329	0	0

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	ASSERT	PROPERTIES	SEQUENCES
Total	1457	0	20
Category 0	1457	0	20

	ASSERT	PROPERTIES	SEQUENCES
Total	1457	0	20
Severity 0	1457	0	20

	NUMBER	PERCENT
Total Number	1457	100.00
Uncovered	54	3.71
Success	1403	96.29
Failure	0	0.00
Incomplete	11	0.75
Without Attempts	5	0.34

	NUMBER	PERCENT
Total Number	20	100.00
Uncovered	0	0.00
All Matches	20	100.00
First Matches	20	100.00