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Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.23 100.00 100.00 85.00 100.00 96.15


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.73 100.00 100.00 100.00 85.00 98.15 97.22


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.18 94.16 96.15 96.96 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock 100.00 100.00 100.00 100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg 95.00 100.00 100.00 80.00 100.00
u_prim_mubi8_sender_read_lock_pre 100.00 100.00 100.00 100.00
u_prim_mubi8_sender_write_lock_pre 100.00 100.00 100.00 100.00
u_state_regs 100.00 100.00 100.00 100.00


Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 100.00 91.67 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.32 100.00 100.00 100.00 91.67 98.25 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.18 94.16 96.15 96.96 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock 100.00 100.00 100.00 100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg 95.00 100.00 100.00 80.00 100.00
u_prim_mubi8_sender_read_lock_pre 100.00 100.00 100.00 100.00
u_prim_mubi8_sender_write_lock_pre 100.00 100.00 100.00 100.00
u_state_regs 100.00 100.00 100.00 100.00


Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.75 100.00 97.06 91.67 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.83 100.00 97.06 100.00 91.67 98.25 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.18 94.16 96.15 96.96 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock 100.00 100.00 100.00 100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg 95.00 100.00 100.00 80.00 100.00
u_prim_mubi8_sender_read_lock_pre 100.00 100.00 100.00 100.00
u_prim_mubi8_sender_write_lock_pre 100.00 100.00 100.00 100.00
u_state_regs 100.00 100.00 100.00 100.00

Go back
Module Instances:
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf
Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf
Line No.TotalCoveredPercent
TOTAL8686100.00
CONT_ASSIGN13811100.00
ALWAYS15333100.00
ALWAYS1646161100.00
CONT_ASSIGN33411100.00
CONT_ASSIGN33611100.00
CONT_ASSIGN33911100.00
CONT_ASSIGN34911100.00
CONT_ASSIGN35011100.00
CONT_ASSIGN35411100.00
CONT_ASSIGN35811100.00
CONT_ASSIGN39511100.00
CONT_ASSIGN42011100.00
CONT_ASSIGN45411100.00
ALWAYS46133100.00
ALWAYS46488100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
138 1 1
153 1 1
154 1 1
156 1 1
164 1 1
167 1 1
170 1 1
171 1 1
174 1 1
175 1 1
176 1 1
179 1 1
182 1 1
183 1 1
184 1 1
186 1 1
191 1 1
193 1 1
194 1 1
196 unreachable
MISSING_ELSE
205 1 1
206 1 1
207 1 1
==> MISSING_ELSE
215 1 1
216 1 1
217 1 1
218 1 1
220 1 1
221 excluded
Exclude Annotation: VC_COV_UNR
MISSING_ELSE
224 excluded
Exclude Annotation: VC_COV_UNR
225 excluded
Exclude Annotation: VC_COV_UNR
MISSING_ELSE
233 1 1
234 1 1
235 1 1
236 1 1
237 1 1
MISSING_ELSE
246 1 1
248 1 1
249 1 1
250 1 1
251 1 1
252 1 1
MISSING_ELSE
255 1 1
256 1 1
257 1 1
258 1 1
266 1 1
267 1 1
268 1 1
269 1 1
270 1 1
272 1 1
273 excluded
Exclude Annotation: VC_COV_UNR
MISSING_ELSE
276 excluded
Exclude Annotation: VC_COV_UNR
277 excluded
Exclude Annotation: VC_COV_UNR
279 excluded
Exclude Annotation: VC_COV_UNR
MISSING_ELSE
288 1 1
289 1 1
MISSING_ELSE
293 1 1
294 1 1
295 1 1
296 1 1
297 1 1
298 1 1
MISSING_ELSE
314 1 1
315 1 1
316 1 1
317 1 1
MISSING_ELSE
MISSING_ELSE
321 1 1
322 1 1
323 1 1
324 1 1
325 1 1
MISSING_ELSE
MISSING_ELSE
334 1 1
336 1 1
339 1 1
349 1 1
350 1 1
354 1 1
358 1 1
395 1 1
420 1 1
454 1 1
461 3 3
464 1 1
465 1 1
466 1 1
467 1 1
469 1 1
470 1 1
471 1 1
472 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf
TotalCoveredPercent
Conditions2929100.00
Logical2929100.00
Non-Logical00
Event00

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------
-1-StatusTestsExclude Annotation
0CoveredT1,T2,T3
1Excluded VC_COV_UNR

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------
-1-StatusTestsExclude Annotation
0CoveredT2,T3,T4
1Excluded VC_COV_UNR

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T25,T26

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------
-1-StatusTests
0CoveredT73,T145,T161
1CoveredT73,T145,T161

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T5,T7
11CoveredT2,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

FSM Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf
Summary for FSM :: state_q
TotalCoveredPercent
States 7 7 100.00 (Not included in score)
Transitions 13 10 76.92
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
ErrorSt 224 Covered T1,T2,T3
IdleSt 196 Covered T1,T2,T3
InitSt 194 Covered T1,T2,T3
InitWaitSt 207 Covered T1,T2,T3
ReadSt 236 Covered T1,T2,T3
ReadWaitSt 252 Covered T2,T3,T4
ResetSt 190 Covered T1,T2,T3


transitionsLine No.CoveredTestsExclude Annotation
IdleSt->ErrorSt 315 Covered T2,T3,T5
IdleSt->ReadSt 236 Covered T1,T2,T3
InitSt->ErrorSt 315 Not Covered
InitSt->InitWaitSt 207 Covered T1,T2,T3
InitWaitSt->ErrorSt 224 Covered T171,T203,T204
InitWaitSt->IdleSt 218 Covered T1,T2,T3
ReadSt->ErrorSt 315 Not Covered
ReadSt->IdleSt 255 Covered T1,T5,T7
ReadSt->ReadWaitSt 252 Covered T2,T3,T4
ReadWaitSt->ErrorSt 276 Not Covered
ReadWaitSt->IdleSt 270 Covered T2,T3,T4
ResetSt->ErrorSt 315 Covered T1,T73,T74
ResetSt->IdleSt 196 Excluded VC_COV_UNR
ResetSt->InitSt 194 Covered T1,T2,T3


Summary for FSM :: error_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 7 7 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: error_q
statesLine No.CoveredTestsExclude Annotation
AccessError 256 Covered T1,T5,T7
CheckFailError 317 Covered T73,T145,T161
FsmStateError 289 Covered T1,T2,T3
MacroEccCorrError 221 Excluded VC_COV_UNR
NoError 235 Covered T1,T2,T3


transitionsLine No.CoveredTestsExclude Annotation
AccessError->CheckFailError 317 Excluded
AccessError->FsmStateError 325 Covered T8,T14,T170
AccessError->MacroEccCorrError 221 Excluded
AccessError->NoError 235 Covered T1,T5,T7
CheckFailError->AccessError 256 Excluded VC_COV_UNR
CheckFailError->FsmStateError 325 Excluded VC_COV_UNR
CheckFailError->MacroEccCorrError 221 Excluded
CheckFailError->NoError 235 Covered T73,T145,T161
FsmStateError->AccessError 256 Excluded VC_COV_UNR
FsmStateError->CheckFailError 317 Excluded VC_COV_UNR
FsmStateError->MacroEccCorrError 221 Excluded
FsmStateError->NoError 235 Covered T1,T2,T3
MacroEccCorrError->AccessError 256 Excluded
MacroEccCorrError->CheckFailError 317 Excluded
MacroEccCorrError->FsmStateError 325 Excluded
MacroEccCorrError->NoError 235 Excluded
NoError->AccessError 256 Covered T1,T5,T7
NoError->CheckFailError 317 Covered T73,T145,T161
NoError->FsmStateError 289 Covered T1,T2,T3
NoError->MacroEccCorrError 221 Excluded



Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf
Line No.TotalCoveredPercent
Branches 41 41 100.00
TERNARY 336 2 2 100.00
TERNARY 349 2 2 100.00
TERNARY 358 2 2 100.00
TERNARY 395 2 2 100.00
TERNARY 420 2 2 100.00
CASE 186 18 18 100.00
IF 314 3 3 100.00
IF 321 3 3 100.00
IF 461 2 2 100.00
IF 464 3 3 100.00
IF 153 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 336 ((tlul_rvalid_o && (tlul_rerror_o == '0))) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 349 ((otp_addr_sel == DigestAddrSel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T3,T4


LineNo. Expression -1-: 358 ((otp_addr_sel == DigestAddrSel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T3,T4


LineNo. Expression -1-: 395 ((~init_done_o)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 420 ((digest_o != '0)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 186 case (state_q) -2-: 191 if (init_req_i) -3-: 193 if (1'b1) -4-: 206 if (otp_gnt_i) -5-: 215 if (otp_rvalid_i) -6-: 217 if ((otp_err inside {NoError, MacroEccCorrError})) -7-: 220 if ((otp_err != NoError)) -8-: 234 if (tlul_req_i) -9-: 248 if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock))) -10-: 251 if (otp_gnt_i) -11-: 267 if (otp_rvalid_i) -12-: 269 if ((otp_err inside {NoError, MacroEccCorrError})) -13-: 272 if ((otp_err != NoError)) -14-: 288 if ((error_q == NoError)) -15-: 293 if (pending_tlul_error_q) -16-: 296 if (tlul_req_i)

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15--16-StatusTestsExclude Annotation
ResetSt 1 1 - - - - - - - - - - - - - Covered T1,T2,T3
ResetSt 1 0 - - - - - - - - - - - - - Unreachable
ResetSt 0 - - - - - - - - - - - - - - Covered T1,T2,T3
InitSt - - 1 - - - - - - - - - - - - Covered T1,T2,T3
InitSt - - 0 - - - - - - - - - - - - Excluded VC_COV_UNR
InitWaitSt - - - 1 1 1 - - - - - - - - - Excluded VC_COV_UNR
InitWaitSt - - - 1 1 0 - - - - - - - - - Covered T1,T2,T3
InitWaitSt - - - 1 0 - - - - - - - - - - Excluded VC_COV_UNR
InitWaitSt - - - 0 - - - - - - - - - - - Covered T1,T2,T3
IdleSt - - - - - - 1 - - - - - - - - Covered T1,T2,T3
IdleSt - - - - - - 0 - - - - - - - - Covered T1,T2,T3
ReadSt - - - - - - - 1 1 - - - - - - Covered T2,T3,T4
ReadSt - - - - - - - 1 0 - - - - - - Covered T7,T8,T153
ReadSt - - - - - - - 0 - - - - - - - Covered T1,T5,T7
ReadWaitSt - - - - - - - - - 1 1 1 - - - Excluded VC_COV_UNR
ReadWaitSt - - - - - - - - - 1 1 0 - - - Covered T2,T3,T4
ReadWaitSt - - - - - - - - - 1 0 - - - - Excluded VC_COV_UNR
ReadWaitSt - - - - - - - - - 0 - - - - - Covered T2,T3,T4
ErrorSt - - - - - - - - - - - - 1 - - Covered T24,T25,T26
ErrorSt - - - - - - - - - - - - 0 - - Covered T1,T2,T3
ErrorSt - - - - - - - - - - - - - 1 - Covered T1,T5,T7
ErrorSt - - - - - - - - - - - - - 0 1 Covered T1,T5,T7
ErrorSt - - - - - - - - - - - - - 0 0 Covered T1,T2,T3
default - - - - - - - - - - - - - - - Covered T24,T25,T26


LineNo. Expression -1-: 314 if (ecc_err) -2-: 316 if ((state_q != ErrorSt))

Branches:
-1--2-StatusTests
1 1 Covered T73,T145,T161
1 0 Covered T73,T145,T161
0 - Covered T1,T2,T3


LineNo. Expression -1-: 321 if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)) -2-: 324 if ((state_q != ErrorSt))

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T3
1 0 Covered T1,T2,T3
0 - Covered T1,T2,T3


LineNo. Expression -1-: 461 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 464 if ((!rst_ni)) -2-: 471 if (tlul_gnt_o)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 153 if ((otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}))

Branches:
-1-StatusTests
1 Covered T2,T3,T5
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 26 26 100.00 25 96.15
Cover properties 0 0 0
Cover sequences 0 0 0
Total 26 26 100.00 25 96.15




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AccessKnown_A 459100430 458229571 0 0
DigestKnown_A 459100430 458229571 0 0
DigestOffsetMustBeRepresentable_A 1147 1147 0 0
EccErrorState_A 459100430 15146 0 0
ErrorKnown_A 459100430 458229571 0 0
FsmStateKnown_A 459100430 458229571 0 0
InitDoneKnown_A 459100430 458229571 0 0
InitReadLocksPartition_A 459100430 91639263 0 0
InitWriteLocksPartition_A 459100430 91639263 0 0
OffsetMustBeBlockAligned_A 1147 1147 0 0
OtpAddrKnown_A 459100430 458229571 0 0
OtpCmdKnown_A 459100430 458229571 0 0
OtpErrorState_A 459100430 0 0 0
OtpReqKnown_A 459100430 458229571 0 0
OtpSizeKnown_A 459100430 458229571 0 0
OtpWdataKnown_A 459100430 458229571 0 0
ReadLockPropagation_A 459100430 193094427 0 0
SizeMustBeBlockAligned_A 1147 1147 0 0
TlulGntKnown_A 459100430 458229571 0 0
TlulRdataKnown_A 459100430 458229571 0 0
TlulReadOnReadLock_A 459100430 8234 0 0
TlulRerrorKnown_A 459100430 458229571 0 0
TlulRvalidKnown_A 459100430 458229571 0 0
WriteLockPropagation_A 459100430 1958101 0 0
gen_digest_write_lock.DigestWriteLocksPartition_A 459100430 23532371 0 0
u_state_regs_A 459100430 458229571 0 0


AccessKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

DigestKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

DigestOffsetMustBeRepresentable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1147 1147 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

EccErrorState_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 15146 0 0
T15 152455 0 0 0
T73 8078 2798 0 0
T93 44020 0 0 0
T94 50790 0 0 0
T122 55794 0 0 0
T145 0 2364 0 0
T153 19139 0 0 0
T155 29110 0 0 0
T161 0 3922 0 0
T168 0 3086 0 0
T169 0 2976 0 0
T170 98448 0 0 0
T171 61990 0 0 0
T172 10862 0 0 0

ErrorKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

FsmStateKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

InitDoneKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

InitReadLocksPartition_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 91639263 0 0
T1 15038 5872 0 0
T2 13130 4148 0 0
T3 13472 3873 0 0
T4 21452 171 0 0
T5 117845 7010 0 0
T6 28214 1161 0 0
T7 213200 19903 0 0
T10 14657 4134 0 0
T11 9610 4112 0 0
T12 92555 499 0 0

InitWriteLocksPartition_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 91639263 0 0
T1 15038 5872 0 0
T2 13130 4148 0 0
T3 13472 3873 0 0
T4 21452 171 0 0
T5 117845 7010 0 0
T6 28214 1161 0 0
T7 213200 19903 0 0
T10 14657 4134 0 0
T11 9610 4112 0 0
T12 92555 499 0 0

OffsetMustBeBlockAligned_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1147 1147 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

OtpAddrKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

OtpCmdKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

OtpErrorState_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 0 0 0

OtpReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

OtpSizeKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

OtpWdataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

ReadLockPropagation_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 193094427 0 0
T1 15038 1233 0 0
T2 13130 0 0 0
T3 13472 0 0 0
T4 21452 0 0 0
T5 117845 10270 0 0
T6 28214 0 0 0
T7 213200 7421 0 0
T8 0 369961 0 0
T10 14657 0 0 0
T11 9610 0 0 0
T12 92555 27446 0 0
T16 0 251835 0 0
T17 0 1252 0 0
T91 0 4794 0 0
T106 0 6113 0 0
T198 0 17580 0 0

SizeMustBeBlockAligned_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1147 1147 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

TlulGntKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

TlulRdataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

TlulReadOnReadLock_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 8234 0 0
T1 15038 7 0 0
T2 13130 0 0 0
T3 13472 0 0 0
T4 21452 0 0 0
T5 117845 2 0 0
T6 28214 0 0 0
T7 213200 20 0 0
T8 0 33 0 0
T10 14657 0 0 0
T11 9610 0 0 0
T12 92555 4 0 0
T16 0 50 0 0
T89 0 19 0 0
T90 0 14 0 0
T91 0 1 0 0
T198 0 3 0 0

TlulRerrorKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

TlulRvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

WriteLockPropagation_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 1958101 0 0
T5 117845 9448 0 0
T6 28214 0 0 0
T7 213200 4153 0 0
T10 14657 0 0 0
T11 9610 0 0 0
T12 92555 11025 0 0
T16 110040 15752 0 0
T88 98941 0 0 0
T89 40728 0 0 0
T90 23742 0 0 0
T91 0 1318 0 0
T93 0 3406 0 0
T96 0 2896 0 0
T101 0 4368 0 0
T102 0 612 0 0
T103 0 7286 0 0

gen_digest_write_lock.DigestWriteLocksPartition_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 23532371 0 0
T1 15038 2479 0 0
T2 13130 2310 0 0
T3 13472 2994 0 0
T4 21452 0 0 0
T5 117845 59797 0 0
T6 28214 0 0 0
T7 213200 67768 0 0
T10 14657 0 0 0
T11 9610 0 0 0
T12 92555 74975 0 0
T16 0 445566 0 0
T17 0 25073 0 0
T91 0 39997 0 0
T106 0 3649 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf
Line No.TotalCoveredPercent
TOTAL9191100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN14911100.00
ALWAYS1646868100.00
CONT_ASSIGN33411100.00
CONT_ASSIGN33611100.00
CONT_ASSIGN34211100.00
CONT_ASSIGN34911100.00
CONT_ASSIGN35011100.00
CONT_ASSIGN35411100.00
CONT_ASSIGN35811100.00
CONT_ASSIGN39511100.00
CONT_ASSIGN42011100.00
CONT_ASSIGN45411100.00
ALWAYS46133100.00
ALWAYS46488100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
138 1 1
149 1 1
164 1 1
167 1 1
170 1 1
171 1 1
174 1 1
175 1 1
176 1 1
179 1 1
182 1 1
183 1 1
184 1 1
186 1 1
191 1 1
193 1 1
194 1 1
196 unreachable
MISSING_ELSE
205 1 1
206 1 1
207 1 1
MISSING_ELSE
215 1 1
216 1 1
217 1 1
218 1 1
220 1 1
221 1 1
MISSING_ELSE
224 1 1
225 1 1
MISSING_ELSE
233 1 1
234 1 1
235 1 1
236 1 1
237 1 1
MISSING_ELSE
246 1 1
248 1 1
249 1 1
250 1 1
251 1 1
252 1 1
MISSING_ELSE
255 1 1
256 1 1
257 1 1
258 1 1
266 1 1
267 1 1
268 1 1
269 1 1
270 1 1
272 1 1
273 1 1
MISSING_ELSE
276 1 1
277 1 1
279 1 1
MISSING_ELSE
288 1 1
289 1 1
MISSING_ELSE
293 1 1
294 1 1
295 1 1
296 1 1
297 1 1
298 1 1
MISSING_ELSE
314 1 1
315 1 1
316 1 1
317 1 1
MISSING_ELSE
MISSING_ELSE
321 1 1
322 1 1
323 1 1
324 1 1
325 1 1
MISSING_ELSE
MISSING_ELSE
334 1 1
336 1 1
342 1 1
349 1 1
350 1 1
354 1 1
358 1 1
395 1 1
420 1 1
454 1 1
461 3 3
464 1 1
465 1 1
466 1 1
467 1 1
469 1 1
470 1 1
471 1 1
472 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT11,T162,T158

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT5,T71,T163

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T25,T26

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------
-1-StatusTests
0CoveredT73,T164,T161
1CoveredT73,T164,T161

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T5

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T5,T7
11CoveredT2,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11CoveredT1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5

FSM Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf
Summary for FSM :: state_q
TotalCoveredPercent
States 7 7 100.00 (Not included in score)
Transitions 13 12 92.31
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
ErrorSt 224 Covered T1,T2,T3
IdleSt 196 Covered T1,T2,T3
InitSt 194 Covered T1,T2,T3
InitWaitSt 207 Covered T1,T2,T3
ReadSt 236 Covered T1,T2,T3
ReadWaitSt 252 Covered T2,T3,T4
ResetSt 190 Covered T1,T2,T3


transitionsLine No.CoveredTestsExclude Annotation
IdleSt->ErrorSt 315 Covered T3,T5,T7
IdleSt->ReadSt 236 Covered T1,T2,T3
InitSt->ErrorSt 315 Covered T171,T203,T204
InitSt->InitWaitSt 207 Covered T1,T2,T3
InitWaitSt->ErrorSt 224 Covered T2,T10,T100
InitWaitSt->IdleSt 218 Covered T1,T2,T3
ReadSt->ErrorSt 315 Not Covered
ReadSt->IdleSt 255 Covered T1,T5,T7
ReadSt->ReadWaitSt 252 Covered T2,T3,T4
ReadWaitSt->ErrorSt 276 Covered T151,T205,T206
ReadWaitSt->IdleSt 270 Covered T2,T3,T4
ResetSt->ErrorSt 315 Covered T1,T73,T74
ResetSt->IdleSt 196 Excluded VC_COV_UNR
ResetSt->InitSt 194 Covered T1,T2,T3


Summary for FSM :: error_q
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 11 10 90.91
Sequences 0 0

State, Transition and Sequence Details for FSM :: error_q
statesLine No.CoveredTests
AccessError 256 Covered T1,T5,T7
CheckFailError 317 Covered T73,T164,T161
FsmStateError 289 Covered T1,T3,T5
MacroEccCorrError 221 Covered T5,T11,T162
NoError 235 Covered T1,T2,T3


transitionsLine No.CoveredTestsExclude Annotation
AccessError->CheckFailError 317 Excluded VC_COV_UNR
AccessError->FsmStateError 325 Covered T16,T8,T127
AccessError->MacroEccCorrError 221 Excluded VC_COV_UNR
AccessError->NoError 235 Covered T1,T5,T7
CheckFailError->AccessError 256 Excluded VC_COV_UNR
CheckFailError->FsmStateError 325 Excluded VC_COV_UNR
CheckFailError->MacroEccCorrError 221 Excluded VC_COV_UNR
CheckFailError->NoError 235 Covered T73,T164,T161
FsmStateError->AccessError 256 Excluded VC_COV_UNR
FsmStateError->CheckFailError 317 Excluded VC_COV_UNR
FsmStateError->MacroEccCorrError 221 Excluded VC_COV_UNR
FsmStateError->NoError 235 Covered T1,T3,T5
MacroEccCorrError->AccessError 256 Excluded VC_COV_UNR
MacroEccCorrError->CheckFailError 317 Not Covered
MacroEccCorrError->FsmStateError 325 Covered T11,T162,T158
MacroEccCorrError->NoError 235 Covered T5,T71,T110
NoError->AccessError 256 Covered T1,T5,T7
NoError->CheckFailError 317 Covered T73,T164,T161
NoError->FsmStateError 289 Covered T1,T3,T5
NoError->MacroEccCorrError 221 Covered T5,T11,T162



Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf
Line No.TotalCoveredPercent
Branches 44 44 100.00
TERNARY 336 2 2 100.00
TERNARY 349 2 2 100.00
TERNARY 358 2 2 100.00
TERNARY 395 2 2 100.00
TERNARY 420 2 2 100.00
CASE 186 23 23 100.00
IF 314 3 3 100.00
IF 321 3 3 100.00
IF 461 2 2 100.00
IF 464 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 336 ((tlul_rvalid_o && (tlul_rerror_o == '0))) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 349 ((otp_addr_sel == DigestAddrSel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T3,T4


LineNo. Expression -1-: 358 ((otp_addr_sel == DigestAddrSel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T3,T4


LineNo. Expression -1-: 395 ((~init_done_o)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 420 ((digest_o != '0)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 186 case (state_q) -2-: 191 if (init_req_i) -3-: 193 if (1'b1) -4-: 206 if (otp_gnt_i) -5-: 215 if (otp_rvalid_i) -6-: 217 if ((otp_err inside {NoError, MacroEccCorrError})) -7-: 220 if ((otp_err != NoError)) -8-: 234 if (tlul_req_i) -9-: 248 if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock))) -10-: 251 if (otp_gnt_i) -11-: 267 if (otp_rvalid_i) -12-: 269 if ((otp_err inside {NoError, MacroEccCorrError})) -13-: 272 if ((otp_err != NoError)) -14-: 288 if ((error_q == NoError)) -15-: 293 if (pending_tlul_error_q) -16-: 296 if (tlul_req_i)

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15--16-StatusTests
ResetSt 1 1 - - - - - - - - - - - - - Covered T1,T2,T3
ResetSt 1 0 - - - - - - - - - - - - - Unreachable
ResetSt 0 - - - - - - - - - - - - - - Covered T1,T2,T3
InitSt - - 1 - - - - - - - - - - - - Covered T1,T2,T3
InitSt - - 0 - - - - - - - - - - - - Covered T1,T2,T3
InitWaitSt - - - 1 1 1 - - - - - - - - - Covered T11,T162,T158
InitWaitSt - - - 1 1 0 - - - - - - - - - Covered T1,T2,T3
InitWaitSt - - - 1 0 - - - - - - - - - - Covered T2,T10,T100
InitWaitSt - - - 0 - - - - - - - - - - - Covered T1,T2,T3
IdleSt - - - - - - 1 - - - - - - - - Covered T1,T2,T3
IdleSt - - - - - - 0 - - - - - - - - Covered T1,T2,T3
ReadSt - - - - - - - 1 1 - - - - - - Covered T2,T3,T4
ReadSt - - - - - - - 1 0 - - - - - - Covered T7,T8,T96
ReadSt - - - - - - - 0 - - - - - - - Covered T1,T5,T7
ReadWaitSt - - - - - - - - - 1 1 1 - - - Covered T5,T71,T163
ReadWaitSt - - - - - - - - - 1 1 0 - - - Covered T2,T3,T4
ReadWaitSt - - - - - - - - - 1 0 - - - - Covered T151,T205,T206
ReadWaitSt - - - - - - - - - 0 - - - - - Covered T2,T3,T4
ErrorSt - - - - - - - - - - - - 1 - - Covered T24,T25,T26
ErrorSt - - - - - - - - - - - - 0 - - Covered T1,T2,T3
ErrorSt - - - - - - - - - - - - - 1 - Covered T1,T5,T7
ErrorSt - - - - - - - - - - - - - 0 1 Covered T1,T5,T7
ErrorSt - - - - - - - - - - - - - 0 0 Covered T1,T2,T3
default - - - - - - - - - - - - - - - Covered T24,T25,T26


LineNo. Expression -1-: 314 if (ecc_err) -2-: 316 if ((state_q != ErrorSt))

Branches:
-1--2-StatusTests
1 1 Covered T73,T164,T161
1 0 Covered T73,T164,T161
0 - Covered T1,T2,T3


LineNo. Expression -1-: 321 if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)) -2-: 324 if ((state_q != ErrorSt))

Branches:
-1--2-StatusTests
1 1 Covered T1,T3,T5
1 0 Covered T1,T2,T3
0 - Covered T1,T2,T3


LineNo. Expression -1-: 461 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 464 if ((!rst_ni)) -2-: 471 if (tlul_gnt_o)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 26 26 100.00 26 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 26 26 100.00 26 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AccessKnown_A 459100430 458229571 0 0
DigestKnown_A 459100430 458229571 0 0
DigestOffsetMustBeRepresentable_A 1147 1147 0 0
EccErrorState_A 459100430 9837 0 0
ErrorKnown_A 459100430 458229571 0 0
FsmStateKnown_A 459100430 458229571 0 0
InitDoneKnown_A 459100430 458229571 0 0
InitReadLocksPartition_A 459100430 91823357 0 0
InitWriteLocksPartition_A 459100430 91823357 0 0
OffsetMustBeBlockAligned_A 1147 1147 0 0
OtpAddrKnown_A 459100430 458229571 0 0
OtpCmdKnown_A 459100430 458229571 0 0
OtpErrorState_A 459100430 78 0 0
OtpReqKnown_A 459100430 458229571 0 0
OtpSizeKnown_A 459100430 458229571 0 0
OtpWdataKnown_A 459100430 458229571 0 0
ReadLockPropagation_A 459100430 202041287 0 0
SizeMustBeBlockAligned_A 1147 1147 0 0
TlulGntKnown_A 459100430 458229571 0 0
TlulRdataKnown_A 459100430 458229571 0 0
TlulReadOnReadLock_A 459100430 8157 0 0
TlulRerrorKnown_A 459100430 458229571 0 0
TlulRvalidKnown_A 459100430 458229571 0 0
WriteLockPropagation_A 459100430 1631731 0 0
gen_digest_write_lock.DigestWriteLocksPartition_A 459100430 23213129 0 0
u_state_regs_A 459100430 458229571 0 0


AccessKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

DigestKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

DigestOffsetMustBeRepresentable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1147 1147 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

EccErrorState_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 9837 0 0
T15 152455 0 0 0
T73 8078 2798 0 0
T93 44020 0 0 0
T94 50790 0 0 0
T122 55794 0 0 0
T153 19139 0 0 0
T155 29110 0 0 0
T161 0 3922 0 0
T164 0 3117 0 0
T170 98448 0 0 0
T171 61990 0 0 0
T172 10862 0 0 0

ErrorKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

FsmStateKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

InitDoneKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

InitReadLocksPartition_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 91823357 0 0
T1 15038 5923 0 0
T2 13130 4172 0 0
T3 13472 3907 0 0
T4 21452 222 0 0
T5 117845 7265 0 0
T6 28214 1280 0 0
T7 213200 20668 0 0
T10 14657 4158 0 0
T11 9610 4146 0 0
T12 92555 652 0 0

InitWriteLocksPartition_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 91823357 0 0
T1 15038 5923 0 0
T2 13130 4172 0 0
T3 13472 3907 0 0
T4 21452 222 0 0
T5 117845 7265 0 0
T6 28214 1280 0 0
T7 213200 20668 0 0
T10 14657 4158 0 0
T11 9610 4146 0 0
T12 92555 652 0 0

OffsetMustBeBlockAligned_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1147 1147 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

OtpAddrKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

OtpCmdKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

OtpErrorState_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 78 0 0
T2 13130 1 0 0
T3 13472 0 0 0
T4 21452 0 0 0
T5 117845 0 0 0
T6 28214 0 0 0
T7 213200 0 0 0
T10 14657 1 0 0
T11 9610 0 0 0
T12 92555 0 0 0
T16 110040 0 0 0
T100 0 1 0 0
T172 0 1 0 0
T183 0 1 0 0
T188 0 1 0 0
T189 0 1 0 0
T190 0 1 0 0
T191 0 1 0 0
T192 0 1 0 0

OtpReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

OtpSizeKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

OtpWdataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

ReadLockPropagation_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 202041287 0 0
T1 15038 1673 0 0
T2 13130 0 0 0
T3 13472 0 0 0
T4 21452 0 0 0
T5 117845 11723 0 0
T6 28214 0 0 0
T7 213200 5194 0 0
T8 0 370685 0 0
T9 0 575309 0 0
T10 14657 0 0 0
T11 9610 0 0 0
T12 92555 27190 0 0
T16 0 281196 0 0
T17 0 1250 0 0
T91 0 7298 0 0
T106 0 6106 0 0

SizeMustBeBlockAligned_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1147 1147 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

TlulGntKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

TlulRdataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

TlulReadOnReadLock_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 8157 0 0
T1 15038 9 0 0
T2 13130 0 0 0
T3 13472 0 0 0
T4 21452 0 0 0
T5 117845 4 0 0
T6 28214 0 0 0
T7 213200 16 0 0
T8 0 31 0 0
T10 14657 0 0 0
T11 9610 0 0 0
T12 92555 3 0 0
T16 0 43 0 0
T89 0 23 0 0
T90 0 21 0 0
T91 0 1 0 0
T198 0 11 0 0

TlulRerrorKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

TlulRvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

WriteLockPropagation_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 1631731 0 0
T7 213200 4268 0 0
T8 391932 0 0 0
T11 9610 0 0 0
T12 92555 11212 0 0
T16 110040 27369 0 0
T48 11150 0 0 0
T88 98941 0 0 0
T89 40728 0 0 0
T90 23742 0 0 0
T92 0 9573 0 0
T93 0 3132 0 0
T98 0 22890 0 0
T100 12039 0 0 0
T103 0 3493 0 0
T104 0 3091 0 0
T199 0 525 0 0
T200 0 9678 0 0

gen_digest_write_lock.DigestWriteLocksPartition_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 23213129 0 0
T1 15038 2462 0 0
T2 13130 2305 0 0
T3 13472 0 0 0
T4 21452 0 0 0
T5 117845 85894 0 0
T6 28214 0 0 0
T7 213200 67462 0 0
T10 14657 3210 0 0
T11 9610 0 0 0
T12 92555 74839 0 0
T16 0 384260 0 0
T91 0 39810 0 0
T100 0 2195 0 0
T106 0 3632 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf
Line No.TotalCoveredPercent
TOTAL9191100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN14911100.00
ALWAYS1646868100.00
CONT_ASSIGN33411100.00
CONT_ASSIGN33611100.00
CONT_ASSIGN34211100.00
CONT_ASSIGN34911100.00
CONT_ASSIGN35011100.00
CONT_ASSIGN35411100.00
CONT_ASSIGN35811100.00
CONT_ASSIGN39511100.00
CONT_ASSIGN42011100.00
CONT_ASSIGN45411100.00
ALWAYS46133100.00
ALWAYS46488100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
138 1 1
149 1 1
164 1 1
167 1 1
170 1 1
171 1 1
174 1 1
175 1 1
176 1 1
179 1 1
182 1 1
183 1 1
184 1 1
186 1 1
191 1 1
193 1 1
194 1 1
196 unreachable
MISSING_ELSE
205 1 1
206 1 1
207 1 1
MISSING_ELSE
215 1 1
216 1 1
217 1 1
218 1 1
220 1 1
221 1 1
MISSING_ELSE
224 1 1
225 1 1
MISSING_ELSE
233 1 1
234 1 1
235 1 1
236 1 1
237 1 1
MISSING_ELSE
246 1 1
248 1 1
249 1 1
250 1 1
251 1 1
252 1 1
MISSING_ELSE
255 1 1
256 1 1
257 1 1
258 1 1
266 1 1
267 1 1
268 1 1
269 1 1
270 1 1
272 1 1
273 1 1
MISSING_ELSE
276 1 1
277 1 1
279 1 1
MISSING_ELSE
288 1 1
289 1 1
MISSING_ELSE
293 1 1
294 1 1
295 1 1
296 1 1
297 1 1
298 1 1
MISSING_ELSE
314 1 1
315 1 1
316 1 1
317 1 1
MISSING_ELSE
MISSING_ELSE
321 1 1
322 1 1
323 1 1
324 1 1
325 1 1
MISSING_ELSE
MISSING_ELSE
334 1 1
336 1 1
342 1 1
349 1 1
350 1 1
354 1 1
358 1 1
395 1 1
420 1 1
454 1 1
461 3 3
464 1 1
465 1 1
466 1 1
467 1 1
469 1 1
470 1 1
471 1 1
472 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf
TotalCoveredPercent
Conditions343397.06
Logical343397.06
Non-Logical00
Event00

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT158,T75,T76

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T66,T70

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T25,T26

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------
-1-StatusTests
0CoveredT73,T145,T159
1CoveredT73,T145,T159

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T5,T7
11CoveredT1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00110110000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T5

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T5

FSM Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf
Summary for FSM :: state_q
TotalCoveredPercent
States 7 7 100.00 (Not included in score)
Transitions 13 12 92.31
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
ErrorSt 224 Covered T1,T2,T3
IdleSt 196 Covered T1,T2,T3
InitSt 194 Covered T1,T2,T3
InitWaitSt 207 Covered T1,T2,T3
ReadSt 236 Covered T1,T2,T3
ReadWaitSt 252 Covered T1,T2,T3
ResetSt 190 Covered T1,T2,T3


transitionsLine No.CoveredTestsExclude Annotation
IdleSt->ErrorSt 315 Covered T5,T7,T11
IdleSt->ReadSt 236 Covered T1,T2,T3
InitSt->ErrorSt 315 Covered T171,T203,T204
InitSt->InitWaitSt 207 Covered T1,T2,T3
InitWaitSt->ErrorSt 224 Covered T2,T3,T10
InitWaitSt->IdleSt 218 Covered T1,T2,T3
ReadSt->ErrorSt 315 Not Covered
ReadSt->IdleSt 255 Covered T1,T5,T7
ReadSt->ReadWaitSt 252 Covered T1,T2,T3
ReadWaitSt->ErrorSt 276 Covered T166,T207,T206
ReadWaitSt->IdleSt 270 Covered T1,T2,T3
ResetSt->ErrorSt 315 Covered T1,T73,T74
ResetSt->IdleSt 196 Excluded VC_COV_UNR
ResetSt->InitSt 194 Covered T1,T2,T3


Summary for FSM :: error_q
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 11 10 90.91
Sequences 0 0

State, Transition and Sequence Details for FSM :: error_q
statesLine No.CoveredTests
AccessError 256 Covered T1,T5,T7
CheckFailError 317 Covered T73,T145,T159
FsmStateError 289 Covered T1,T2,T5
MacroEccCorrError 221 Covered T5,T66,T158
NoError 235 Covered T1,T2,T3


transitionsLine No.CoveredTestsExclude Annotation
AccessError->CheckFailError 317 Excluded VC_COV_UNR
AccessError->FsmStateError 325 Covered T16,T8,T14
AccessError->MacroEccCorrError 221 Excluded VC_COV_UNR
AccessError->NoError 235 Covered T1,T5,T7
CheckFailError->AccessError 256 Excluded VC_COV_UNR
CheckFailError->FsmStateError 325 Excluded VC_COV_UNR
CheckFailError->MacroEccCorrError 221 Excluded VC_COV_UNR
CheckFailError->NoError 235 Covered T73,T145,T159
FsmStateError->AccessError 256 Excluded VC_COV_UNR
FsmStateError->CheckFailError 317 Excluded VC_COV_UNR
FsmStateError->MacroEccCorrError 221 Excluded VC_COV_UNR
FsmStateError->NoError 235 Covered T1,T2,T5
MacroEccCorrError->AccessError 256 Excluded VC_COV_UNR
MacroEccCorrError->CheckFailError 317 Not Covered
MacroEccCorrError->FsmStateError 325 Covered T158,T75,T76
MacroEccCorrError->NoError 235 Covered T5,T66,T70
NoError->AccessError 256 Covered T1,T5,T7
NoError->CheckFailError 317 Covered T73,T145,T159
NoError->FsmStateError 289 Covered T1,T2,T5
NoError->MacroEccCorrError 221 Covered T5,T66,T158



Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf
Line No.TotalCoveredPercent
Branches 44 44 100.00
TERNARY 336 2 2 100.00
TERNARY 349 2 2 100.00
TERNARY 358 2 2 100.00
TERNARY 395 2 2 100.00
TERNARY 420 2 2 100.00
CASE 186 23 23 100.00
IF 314 3 3 100.00
IF 321 3 3 100.00
IF 461 2 2 100.00
IF 464 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 336 ((tlul_rvalid_o && (tlul_rerror_o == '0))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 349 ((otp_addr_sel == DigestAddrSel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 358 ((otp_addr_sel == DigestAddrSel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 395 ((~init_done_o)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 420 ((digest_o != '0)) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 186 case (state_q) -2-: 191 if (init_req_i) -3-: 193 if (1'b1) -4-: 206 if (otp_gnt_i) -5-: 215 if (otp_rvalid_i) -6-: 217 if ((otp_err inside {NoError, MacroEccCorrError})) -7-: 220 if ((otp_err != NoError)) -8-: 234 if (tlul_req_i) -9-: 248 if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock))) -10-: 251 if (otp_gnt_i) -11-: 267 if (otp_rvalid_i) -12-: 269 if ((otp_err inside {NoError, MacroEccCorrError})) -13-: 272 if ((otp_err != NoError)) -14-: 288 if ((error_q == NoError)) -15-: 293 if (pending_tlul_error_q) -16-: 296 if (tlul_req_i)

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15--16-StatusTests
ResetSt 1 1 - - - - - - - - - - - - - Covered T1,T2,T3
ResetSt 1 0 - - - - - - - - - - - - - Unreachable
ResetSt 0 - - - - - - - - - - - - - - Covered T1,T2,T3
InitSt - - 1 - - - - - - - - - - - - Covered T1,T2,T3
InitSt - - 0 - - - - - - - - - - - - Covered T1,T2,T3
InitWaitSt - - - 1 1 1 - - - - - - - - - Covered T158,T75,T76
InitWaitSt - - - 1 1 0 - - - - - - - - - Covered T1,T2,T3
InitWaitSt - - - 1 0 - - - - - - - - - - Covered T3,T162,T184
InitWaitSt - - - 0 - - - - - - - - - - - Covered T1,T2,T3
IdleSt - - - - - - 1 - - - - - - - - Covered T1,T2,T3
IdleSt - - - - - - 0 - - - - - - - - Covered T1,T2,T3
ReadSt - - - - - - - 1 1 - - - - - - Covered T1,T2,T3
ReadSt - - - - - - - 1 0 - - - - - - Covered T7,T8,T153
ReadSt - - - - - - - 0 - - - - - - - Covered T1,T5,T7
ReadWaitSt - - - - - - - - - 1 1 1 - - - Covered T5,T66,T70
ReadWaitSt - - - - - - - - - 1 1 0 - - - Covered T1,T2,T3
ReadWaitSt - - - - - - - - - 1 0 - - - - Covered T166,T207,T206
ReadWaitSt - - - - - - - - - 0 - - - - - Covered T1,T2,T3
ErrorSt - - - - - - - - - - - - 1 - - Covered T24,T25,T26
ErrorSt - - - - - - - - - - - - 0 - - Covered T1,T2,T3
ErrorSt - - - - - - - - - - - - - 1 - Covered T1,T7,T16
ErrorSt - - - - - - - - - - - - - 0 1 Covered T1,T7,T16
ErrorSt - - - - - - - - - - - - - 0 0 Covered T1,T2,T3
default - - - - - - - - - - - - - - - Covered T24,T25,T26


LineNo. Expression -1-: 314 if (ecc_err) -2-: 316 if ((state_q != ErrorSt))

Branches:
-1--2-StatusTests
1 1 Covered T73,T145,T159
1 0 Covered T73,T145,T159
0 - Covered T1,T2,T3


LineNo. Expression -1-: 321 if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)) -2-: 324 if ((state_q != ErrorSt))

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T5
1 0 Covered T1,T2,T3
0 - Covered T1,T2,T3


LineNo. Expression -1-: 461 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 464 if ((!rst_ni)) -2-: 471 if (tlul_gnt_o)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 26 26 100.00 26 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 26 26 100.00 26 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AccessKnown_A 459100430 458229571 0 0
DigestKnown_A 459100430 458229571 0 0
DigestOffsetMustBeRepresentable_A 1147 1147 0 0
EccErrorState_A 459100430 15926 0 0
ErrorKnown_A 459100430 458229571 0 0
FsmStateKnown_A 459100430 458229571 0 0
InitDoneKnown_A 459100430 458229571 0 0
InitReadLocksPartition_A 459100430 92006134 0 0
InitWriteLocksPartition_A 459100430 92006134 0 0
OffsetMustBeBlockAligned_A 1147 1147 0 0
OtpAddrKnown_A 459100430 458229571 0 0
OtpCmdKnown_A 459100430 458229571 0 0
OtpErrorState_A 459100430 57 0 0
OtpReqKnown_A 459100430 458229571 0 0
OtpSizeKnown_A 459100430 458229571 0 0
OtpWdataKnown_A 459100430 458229571 0 0
ReadLockPropagation_A 459100430 196992600 0 0
SizeMustBeBlockAligned_A 1147 1147 0 0
TlulGntKnown_A 459100430 458229571 0 0
TlulRdataKnown_A 459100430 458229571 0 0
TlulReadOnReadLock_A 459100430 8388 0 0
TlulRerrorKnown_A 459100430 458229571 0 0
TlulRvalidKnown_A 459100430 458229571 0 0
WriteLockPropagation_A 459100430 1368200 0 0
gen_digest_write_lock.DigestWriteLocksPartition_A 459100430 15660170 0 0
u_state_regs_A 459100430 458229571 0 0


AccessKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

DigestKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

DigestOffsetMustBeRepresentable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1147 1147 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

EccErrorState_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 15926 0 0
T15 152455 0 0 0
T73 8078 2798 0 0
T93 44020 0 0 0
T94 50790 0 0 0
T122 55794 0 0 0
T145 0 2364 0 0
T153 19139 0 0 0
T155 29110 0 0 0
T159 0 3866 0 0
T161 0 3922 0 0
T169 0 2976 0 0
T170 98448 0 0 0
T171 61990 0 0 0
T172 10862 0 0 0

ErrorKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

FsmStateKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

InitDoneKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

InitReadLocksPartition_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 92006134 0 0
T1 15038 5974 0 0
T2 13130 4189 0 0
T3 13472 3931 0 0
T4 21452 273 0 0
T5 117845 7520 0 0
T6 28214 1399 0 0
T7 213200 21433 0 0
T10 14657 4175 0 0
T11 9610 4180 0 0
T12 92555 805 0 0

InitWriteLocksPartition_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 92006134 0 0
T1 15038 5974 0 0
T2 13130 4189 0 0
T3 13472 3931 0 0
T4 21452 273 0 0
T5 117845 7520 0 0
T6 28214 1399 0 0
T7 213200 21433 0 0
T10 14657 4175 0 0
T11 9610 4180 0 0
T12 92555 805 0 0

OffsetMustBeBlockAligned_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1147 1147 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

OtpAddrKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

OtpCmdKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

OtpErrorState_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 57 0 0
T3 13472 1 0 0
T4 21452 0 0 0
T5 117845 0 0 0
T6 28214 0 0 0
T7 213200 0 0 0
T10 14657 0 0 0
T11 9610 0 0 0
T12 92555 0 0 0
T16 110040 0 0 0
T88 98941 0 0 0
T162 0 1 0 0
T166 0 1 0 0
T184 0 1 0 0
T185 0 1 0 0
T186 0 1 0 0
T187 0 1 0 0
T193 0 1 0 0
T194 0 1 0 0
T195 0 1 0 0

OtpReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

OtpSizeKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

OtpWdataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

ReadLockPropagation_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 196992600 0 0
T1 15038 1671 0 0
T2 13130 0 0 0
T3 13472 0 0 0
T4 21452 0 0 0
T5 117845 10026 0 0
T6 28214 0 0 0
T7 213200 5054 0 0
T8 0 369697 0 0
T10 14657 0 0 0
T11 9610 0 0 0
T12 92555 39975 0 0
T16 0 297018 0 0
T17 0 1247 0 0
T88 0 1431 0 0
T91 0 8390 0 0
T106 0 6099 0 0

SizeMustBeBlockAligned_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1147 1147 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

TlulGntKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

TlulRdataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

TlulReadOnReadLock_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 8388 0 0
T1 15038 12 0 0
T2 13130 0 0 0
T3 13472 0 0 0
T4 21452 0 0 0
T5 117845 1 0 0
T6 28214 0 0 0
T7 213200 20 0 0
T8 0 32 0 0
T10 14657 0 0 0
T11 9610 0 0 0
T12 92555 1 0 0
T16 0 53 0 0
T89 0 20 0 0
T90 0 9 0 0
T91 0 3 0 0
T198 0 6 0 0

TlulRerrorKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

TlulRvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

WriteLockPropagation_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 1368200 0 0
T8 391932 0 0 0
T16 110040 17656 0 0
T48 11150 0 0 0
T88 98941 0 0 0
T89 40728 0 0 0
T90 23742 0 0 0
T91 48165 0 0 0
T93 0 5905 0 0
T94 0 3549 0 0
T96 0 992 0 0
T97 0 23388 0 0
T98 0 40740 0 0
T100 12039 0 0 0
T101 0 4053 0 0
T105 17106 0 0 0
T198 26490 0 0 0
T200 0 21424 0 0
T201 0 5299 0 0
T202 0 7039 0 0

gen_digest_write_lock.DigestWriteLocksPartition_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 15660170 0 0
T1 15038 2445 0 0
T2 13130 0 0 0
T3 13472 2972 0 0
T4 21452 0 0 0
T5 117845 85707 0 0
T6 28214 0 0 0
T7 213200 0 0 0
T10 14657 0 0 0
T11 9610 0 0 0
T12 92555 0 0 0
T16 0 362911 0 0
T17 0 25005 0 0
T66 0 35086 0 0
T91 0 39623 0 0
T106 0 3615 0 0
T162 0 3180 0 0
T170 0 2683 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%