Unified Coverage Report :: Module :: otp_ctrl_lfsr_timer

Module : otp_ctrl_lfsr_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.93	100.00	88.46		100.00	91.18	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lfsr_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_otp_ctrl_lfsr_timer	96.16	100.00	89.61		100.00	91.18	100.00

---

Module Instance : tb.dut.u_otp_ctrl_lfsr_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.16	100.00	89.61		100.00	91.18	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.08	100.00	89.87	76.92	100.00	91.67	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.17	94.16	96.15	96.92		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count_cnsty	93.60			93.60
u_prim_count_integ	93.60			93.60
u_prim_double_lfsr	87.95	100.00	100.00	51.81			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : otp_ctrl_lfsr_timer

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	114	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	135	1	1	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	189	1	1	100.00
CONT_ASSIGN	190	1	1	100.00
CONT_ASSIGN	191	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	201	1	1	100.00
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
ALWAYS	246	52	52	100.00
ALWAYS	367	3	3	100.00
ALWAYS	370	13	13	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lfsr_timer.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lfsr_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
72	1	1
77	1	1
78	1	1
87	1	1
114	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
139	1	1
141	1	1
142	1	1
143	1	1
144	1	1
189	1	1
190	1	1
191	1	1
193	1	1
201	1	1
202	1	1
243	1	1
246	1	1
249	1	1
250	1	1
251	1	1
252	1	1
253	1	1
254	1	1
257	1	1
258	1	1
261	1	1
262	1	1
263	1	1
266	1	1
267	1	1
269	1	1
274	1	1
275	1	1
276	1	1
			MISSING_ELSE
283	1	1
284	1	1
285	1	1
286	1	1
287	1	1
288	1	1
289	1	1
290	1	1
291	1	1
292	1	1
			MISSING_ELSE
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
307	1	1
308	1	1
			MISSING_ELSE
316	1	1
322	1	1
323	1	1
324	1	1
325	1	1
326	1	1
327	1	1
329	1	1
330	1	1
			MISSING_ELSE
337	1	1
338	1	1
339	1	1
340	1	1
			MISSING_ELSE
356	1	1
358	1	1
359	1	1
			MISSING_ELSE
367	3	3
370	1	1
371	1	1
372	1	1
373	1	1
374	1	1
375	1	1
376	1	1
378	1	1
379	1	1
380	1	1
381	1	1
382	1	1
383	1	1

---

Cond Coverage for Module : otp_ctrl_lfsr_timer

	Total	Covered	Percent
Conditions	78	69	88.46
Logical	78	69	88.46
Non-Logical	0	0
Event	0	0

 LINE       72
 EXPRESSION (reseed_en ? '0 : (edn_req_o ? reseed_cnt_q : (lfsr_en ? ((reseed_cnt_q + 1'b1)) : reseed_cnt_q)))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       72
 SUB-EXPRESSION (edn_req_o ? reseed_cnt_q : (lfsr_en ? ((reseed_cnt_q + 1'b1)) : reseed_cnt_q))
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       72
 SUB-EXPRESSION (lfsr_en ? ((reseed_cnt_q + 1'b1)) : reseed_cnt_q)
                 ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (edn_req_o & edn_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       87
 EXPRESSION (reseed_en ? edn_data_i[(otp_ctrl_pkg::LfsrWidth - 1):0] : '0)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       101
 EXPRESSION (reseed_en || lfsr_en)
             ----1----    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       132
 EXPRESSION (timeout_i == '0)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       133
 EXPRESSION (integ_period_msk_i == '0)
            -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       134
 EXPRESSION (cnsty_period_msk_i == '0)
            -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       135
 EXPRESSION (integ_cnt == '0)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       136
 EXPRESSION (cnsty_cnt == '0)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (integ_set_period || integ_set_timeout)
             --------1-------    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T9
1	0	Covered	T1,T2,T9

 LINE       139
 EXPRESSION (cnsty_set_period || cnsty_set_timeout)
             --------1-------    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5

 LINE       143
 EXPRESSION (integ_set_period ? ((lfsr_state & integ_mask)) : (40'(timeout_i)))
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T9

 LINE       144
 EXPRESSION (cnsty_set_period ? ((lfsr_state & cnsty_mask)) : (40'(timeout_i)))
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       167
 EXPRESSION (((!cnsty_cnt_zero)) && ((!cnsty_cnt_pause)))
             ---------1---------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T8,T14
1	1	Covered	T1,T4,T5

 LINE       191
 EXPRESSION (set_all_integ_reqs ? ({otp_ctrl_reg_pkg::NumPart {1'b1}}) : ((integ_chk_req_q & (~integ_chk_ack_i))))
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T9

 LINE       193
 EXPRESSION (set_all_cnsty_reqs ? ({otp_ctrl_reg_pkg::NumPart {1'b1}}) : ((cnsty_chk_req_q & (~cnsty_chk_ack_i))))
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       201
 EXPRESSION ((integ_chk_trig_q & ((~clr_integ_chk_trig))) | integ_chk_trig_i)
             ----------------------1---------------------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T9
1	0	Not Covered

 LINE       201
 SUB-EXPRESSION (integ_chk_trig_q & ((~clr_integ_chk_trig)))
                 --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Not Covered

 LINE       202
 EXPRESSION ((cnsty_chk_trig_q & ((~clr_cnsty_chk_trig))) | cnsty_chk_trig_i)
             ----------------------1---------------------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T5,T11,T28

 LINE       202
 SUB-EXPRESSION (cnsty_chk_trig_q & ((~clr_cnsty_chk_trig)))
                 --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T5,T11,T28

 LINE       262
 EXPRESSION (cnsty_chk_trig_q || integ_chk_trig_q)
             --------1-------    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T9
1	0	Covered	T1,T4,T5

 LINE       283
 EXPRESSION ((((!integ_msk_zero)) && integ_cnt_zero) || integ_chk_trig_q)
             -------------------1-------------------    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T9
1	0	Covered	T6,T7,T8

 LINE       283
 SUB-EXPRESSION (((!integ_msk_zero)) && integ_cnt_zero)
                 ---------1---------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

 LINE       288
 EXPRESSION ((((!cnsty_msk_zero)) && cnsty_cnt_zero) || cnsty_chk_trig_q)
             -------------------1-------------------    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T6,T8,T19

 LINE       288
 SUB-EXPRESSION (((!cnsty_msk_zero)) && cnsty_cnt_zero)
                 ---------1---------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T8,T19
1	1	Covered	T6,T8,T19

 LINE       301
 EXPRESSION (((!timeout_zero)) && integ_cnt_zero)
             --------1--------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T12,T28,T103
1	0	Covered	T1,T2,T9
1	1	Covered	T5,T11,T52

 LINE       304
 EXPRESSION (integ_chk_req_q == '0)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T9
1	Covered	T1,T2,T9

 LINE       323
 EXPRESSION (((!timeout_zero)) && cnsty_cnt_zero)
             --------1--------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T36,T107
1	0	Covered	T1,T4,T5
1	1	Covered	T5,T11,T6

 LINE       326
 EXPRESSION (cnsty_chk_req_q == '0)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

---

FSM Coverage for Module : otp_ctrl_lfsr_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	9	9	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
CnstyWaitSt	289	Covered	T1,T4,T5
ErrorSt	302	Covered	T2,T5,T11
IdleSt	275	Covered	T1,T2,T3
IntegWaitSt	284	Covered	T1,T2,T9
ResetSt	273	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
CnstyWaitSt->ErrorSt	324	Covered	T5,T11,T6
CnstyWaitSt->IdleSt	327	Covered	T1,T4,T5
IdleSt->CnstyWaitSt	289	Covered	T1,T4,T5
IdleSt->ErrorSt	358	Covered	T63,T103,T105
IdleSt->IntegWaitSt	284	Covered	T1,T2,T9
IntegWaitSt->ErrorSt	302	Covered	T5,T11,T52
IntegWaitSt->IdleSt	305	Covered	T1,T2,T9
ResetSt->ErrorSt	358	Covered	T2,T169,T95
ResetSt->IdleSt	275	Covered	T1,T2,T3

---

Branch Coverage for Module : otp_ctrl_lfsr_timer

	Line No.	Total	Covered	Percent
Branches		34	31	91.18
TERNARY	72	4	2	50.00
TERNARY	87	2	1	50.00
TERNARY	143	2	2	100.00
TERNARY	144	2	2	100.00
TERNARY	191	2	2	100.00
TERNARY	193	2	2	100.00
CASE	269	14	14	100.00
IF	356	2	2	100.00
IF	367	2	2	100.00
IF	370	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lfsr_timer.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lfsr_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	72	(reseed_en) ? 
-2-:	72	(edn_req_o) ? 
-3-:	72	(lfsr_en) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	87	(reseed_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	143	(integ_set_period) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	144	(cnsty_set_period) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	(set_all_integ_reqs) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	193	(set_all_cnsty_reqs) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	269	case (state_q)
-2-:	274	if (timer_en_i)
-3-:	283	if ((((!integ_msk_zero) && integ_cnt_zero) || integ_chk_trig_q))
-4-:	288	if ((((!cnsty_msk_zero) && cnsty_cnt_zero) || cnsty_chk_trig_q))
-5-:	301	if (((!timeout_zero) && integ_cnt_zero))
-6-:	304	if ((integ_chk_req_q == '0))
-7-:	323	if (((!timeout_zero) && cnsty_cnt_zero))
-8-:	326	if ((cnsty_chk_req_q == '0))
-9-:	339	if ((!chk_timeout_q))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	1	-	-	-	-	-	-	Covered	T1,T2,T9
IdleSt	-	0	1	-	-	-	-	-	Covered	T1,T4,T5
IdleSt	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
IntegWaitSt	-	-	-	1	-	-	-	-	Covered	T5,T11,T52
IntegWaitSt	-	-	-	0	1	-	-	-	Covered	T1,T2,T9
IntegWaitSt	-	-	-	0	0	-	-	-	Covered	T1,T2,T9
CnstyWaitSt	-	-	-	-	-	1	-	-	Covered	T5,T11,T6
CnstyWaitSt	-	-	-	-	-	0	1	-	Covered	T1,T4,T5
CnstyWaitSt	-	-	-	-	-	0	0	-	Covered	T1,T4,T5
ErrorSt	-	-	-	-	-	-	-	1	Covered	T2,T63,T103
ErrorSt	-	-	-	-	-	-	-	0	Covered	T5,T11,T6
default	-	-	-	-	-	-	-	-	Covered	T22,T23,T24

	LineNo.	Expression
-1-:	356	if ((((lfsr_err || integ_cnt_err) || cnsty_cnt_err) || lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)))

Branches:

-1-	Status	Tests
1	Covered	T2,T63,T103
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	367	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	370	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : otp_ctrl_lfsr_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ChkPendingKnown_A	464535028	463675205	0	0
ChkTimeoutKnown_A	464535028	463675205	0	0
CnstyChkReqKnown_A	464535028	463675205	0	0
EdnIsWideEnough_A	1143	1143	0	0
EdnReqKnown_A	464535028	463675205	0	0
IntegChkReqKnown_A	464535028	463675205	0	0
u_state_regs_A	464535028	463675205	0	0

ChkPendingKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464535028	463675205	0	0
T1	121959	120684	0	0
T2	13718	13483	0	0
T3	10752	10697	0	0
T4	22136	21994	0	0
T5	52662	51765	0	0
T9	13364	12973	0	0
T10	11684	11498	0	0
T11	61570	60480	0	0
T12	42988	42125	0	0
T13	12013	11845	0	0

ChkTimeoutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464535028	463675205	0	0
T1	121959	120684	0	0
T2	13718	13483	0	0
T3	10752	10697	0	0
T4	22136	21994	0	0
T5	52662	51765	0	0
T9	13364	12973	0	0
T10	11684	11498	0	0
T11	61570	60480	0	0
T12	42988	42125	0	0
T13	12013	11845	0	0

CnstyChkReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464535028	463675205	0	0
T1	121959	120684	0	0
T2	13718	13483	0	0
T3	10752	10697	0	0
T4	22136	21994	0	0
T5	52662	51765	0	0
T9	13364	12973	0	0
T10	11684	11498	0	0
T11	61570	60480	0	0
T12	42988	42125	0	0
T13	12013	11845	0	0

EdnIsWideEnough_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143	1143	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EdnReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464535028	463675205	0	0
T1	121959	120684	0	0
T2	13718	13483	0	0
T3	10752	10697	0	0
T4	22136	21994	0	0
T5	52662	51765	0	0
T9	13364	12973	0	0
T10	11684	11498	0	0
T11	61570	60480	0	0
T12	42988	42125	0	0
T13	12013	11845	0	0

IntegChkReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464535028	463675205	0	0
T1	121959	120684	0	0
T2	13718	13483	0	0
T3	10752	10697	0	0
T4	22136	21994	0	0
T5	52662	51765	0	0
T9	13364	12973	0	0
T10	11684	11498	0	0
T11	61570	60480	0	0
T12	42988	42125	0	0
T13	12013	11845	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464535028	463675205	0	0
T1	121959	120684	0	0
T2	13718	13483	0	0
T3	10752	10697	0	0
T4	22136	21994	0	0
T5	52662	51765	0	0
T9	13364	12973	0	0
T10	11684	11498	0	0
T11	61570	60480	0	0
T12	42988	42125	0	0
T13	12013	11845	0	0

Line Coverage for Instance : tb.dut.u_otp_ctrl_lfsr_timer

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	114	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	135	1	1	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	189	1	1	100.00
CONT_ASSIGN	190	1	1	100.00
CONT_ASSIGN	191	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	201	1	1	100.00
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
ALWAYS	246	52	52	100.00
ALWAYS	367	3	3	100.00
ALWAYS	370	13	13	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lfsr_timer.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lfsr_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
72	1	1
77	1	1
78	1	1
87	1	1
114	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
139	1	1
141	1	1
142	1	1
143	1	1
144	1	1
189	1	1
190	1	1
191	1	1
193	1	1
201	1	1
202	1	1
243	1	1
246	1	1
249	1	1
250	1	1
251	1	1
252	1	1
253	1	1
254	1	1
257	1	1
258	1	1
261	1	1
262	1	1
263	1	1
266	1	1
267	1	1
269	1	1
274	1	1
275	1	1
276	1	1
			MISSING_ELSE
283	1	1
284	1	1
285	1	1
286	1	1
287	1	1
288	1	1
289	1	1
290	1	1
291	1	1
292	1	1
			MISSING_ELSE
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
307	1	1
308	1	1
			MISSING_ELSE
316	1	1
322	1	1
323	1	1
324	1	1
325	1	1
326	1	1
327	1	1
329	1	1
330	1	1
			MISSING_ELSE
337	1	1
338	1	1
339	1	1
340	1	1
			MISSING_ELSE
356	1	1
358	1	1
359	1	1
			MISSING_ELSE
367	3	3
370	1	1
371	1	1
372	1	1
373	1	1
374	1	1
375	1	1
376	1	1
378	1	1
379	1	1
380	1	1
381	1	1
382	1	1
383	1	1

---

Cond Coverage for Instance : tb.dut.u_otp_ctrl_lfsr_timer

	Total	Covered	Percent
Conditions	77	69	89.61
Logical	77	69	89.61
Non-Logical	0	0
Event	0	0

 LINE       72
 EXPRESSION (reseed_en ? '0 : (edn_req_o ? reseed_cnt_q : (lfsr_en ? ((reseed_cnt_q + 1'b1)) : reseed_cnt_q)))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       72
 SUB-EXPRESSION (edn_req_o ? reseed_cnt_q : (lfsr_en ? ((reseed_cnt_q + 1'b1)) : reseed_cnt_q))
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       72
 SUB-EXPRESSION (lfsr_en ? ((reseed_cnt_q + 1'b1)) : reseed_cnt_q)
                 ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (edn_req_o & edn_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Not Covered
1	1	Not Covered

 LINE       87
 EXPRESSION (reseed_en ? edn_data_i[(otp_ctrl_pkg::LfsrWidth - 1):0] : '0)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       101
 EXPRESSION (reseed_en || lfsr_en)
             ----1----    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       132
 EXPRESSION (timeout_i == '0)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       133
 EXPRESSION (integ_period_msk_i == '0)
            -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       134
 EXPRESSION (cnsty_period_msk_i == '0)
            -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       135
 EXPRESSION (integ_cnt == '0)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       136
 EXPRESSION (cnsty_cnt == '0)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (integ_set_period || integ_set_timeout)
             --------1-------    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T9
1	0	Covered	T1,T2,T9

 LINE       139
 EXPRESSION (cnsty_set_period || cnsty_set_timeout)
             --------1-------    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5

 LINE       143
 EXPRESSION (integ_set_period ? ((lfsr_state & integ_mask)) : (40'(timeout_i)))
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T9

 LINE       144
 EXPRESSION (cnsty_set_period ? ((lfsr_state & cnsty_mask)) : (40'(timeout_i)))
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       167
 EXPRESSION (((!cnsty_cnt_zero)) && ((!cnsty_cnt_pause)))
             ---------1---------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T8,T14
1	1	Covered	T1,T4,T5

 LINE       191
 EXPRESSION (set_all_integ_reqs ? ({otp_ctrl_reg_pkg::NumPart {1'b1}}) : ((integ_chk_req_q & (~integ_chk_ack_i))))
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T9

 LINE       193
 EXPRESSION (set_all_cnsty_reqs ? ({otp_ctrl_reg_pkg::NumPart {1'b1}}) : ((cnsty_chk_req_q & (~cnsty_chk_ack_i))))
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       201
 EXPRESSION ((integ_chk_trig_q & ((~clr_integ_chk_trig))) | integ_chk_trig_i)
             ----------------------1---------------------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T9
1	0	Not Covered

 LINE       201
 SUB-EXPRESSION (integ_chk_trig_q & ((~clr_integ_chk_trig)))
                 --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Not Covered

 LINE       202
 EXPRESSION ((cnsty_chk_trig_q & ((~clr_cnsty_chk_trig))) | cnsty_chk_trig_i)
             ----------------------1---------------------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T5,T11,T28

 LINE       202
 SUB-EXPRESSION (cnsty_chk_trig_q & ((~clr_cnsty_chk_trig)))
                 --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T5,T11,T28

 LINE       262
 EXPRESSION (cnsty_chk_trig_q || integ_chk_trig_q)
             --------1-------    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T9
1	0	Covered	T1,T4,T5

 LINE       283
 EXPRESSION ((((!integ_msk_zero)) && integ_cnt_zero) || integ_chk_trig_q)
             -------------------1-------------------    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T9
1	0	Covered	T6,T7,T8

 LINE       283
 SUB-EXPRESSION (((!integ_msk_zero)) && integ_cnt_zero)
                 ---------1---------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

 LINE       288
 EXPRESSION ((((!cnsty_msk_zero)) && cnsty_cnt_zero) || cnsty_chk_trig_q)
             -------------------1-------------------    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T6,T8,T19

 LINE       288
 SUB-EXPRESSION (((!cnsty_msk_zero)) && cnsty_cnt_zero)
                 ---------1---------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T8,T19
1	1	Covered	T6,T8,T19

 LINE       301
 EXPRESSION (((!timeout_zero)) && integ_cnt_zero)
             --------1--------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T12,T28,T103
1	0	Covered	T1,T2,T9
1	1	Covered	T5,T11,T52

 LINE       304
 EXPRESSION (integ_chk_req_q == '0)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T9
1	Covered	T1,T2,T9

 LINE       323
 EXPRESSION (((!timeout_zero)) && cnsty_cnt_zero)
             --------1--------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T36,T107
1	0	Covered	T1,T4,T5
1	1	Covered	T5,T11,T6

 LINE       326
 EXPRESSION (cnsty_chk_req_q == '0)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

---

FSM Coverage for Instance : tb.dut.u_otp_ctrl_lfsr_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	9	9	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
CnstyWaitSt	289	Covered	T1,T4,T5
ErrorSt	302	Covered	T2,T5,T11
IdleSt	275	Covered	T1,T2,T3
IntegWaitSt	284	Covered	T1,T2,T9
ResetSt	273	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
CnstyWaitSt->ErrorSt	324	Covered	T5,T11,T6
CnstyWaitSt->IdleSt	327	Covered	T1,T4,T5
IdleSt->CnstyWaitSt	289	Covered	T1,T4,T5
IdleSt->ErrorSt	358	Covered	T63,T103,T105
IdleSt->IntegWaitSt	284	Covered	T1,T2,T9
IntegWaitSt->ErrorSt	302	Covered	T5,T11,T52
IntegWaitSt->IdleSt	305	Covered	T1,T2,T9
ResetSt->ErrorSt	358	Covered	T2,T169,T95
ResetSt->IdleSt	275	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_otp_ctrl_lfsr_timer

	Line No.	Total	Covered	Percent
Branches		34	31	91.18
TERNARY	72	4	2	50.00
TERNARY	87	2	1	50.00
TERNARY	143	2	2	100.00
TERNARY	144	2	2	100.00
TERNARY	191	2	2	100.00
TERNARY	193	2	2	100.00
CASE	269	14	14	100.00
IF	356	2	2	100.00
IF	367	2	2	100.00
IF	370	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lfsr_timer.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lfsr_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	72	(reseed_en) ? 
-2-:	72	(edn_req_o) ? 
-3-:	72	(lfsr_en) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	87	(reseed_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	143	(integ_set_period) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	144	(cnsty_set_period) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	(set_all_integ_reqs) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	193	(set_all_cnsty_reqs) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	269	case (state_q)
-2-:	274	if (timer_en_i)
-3-:	283	if ((((!integ_msk_zero) && integ_cnt_zero) || integ_chk_trig_q))
-4-:	288	if ((((!cnsty_msk_zero) && cnsty_cnt_zero) || cnsty_chk_trig_q))
-5-:	301	if (((!timeout_zero) && integ_cnt_zero))
-6-:	304	if ((integ_chk_req_q == '0))
-7-:	323	if (((!timeout_zero) && cnsty_cnt_zero))
-8-:	326	if ((cnsty_chk_req_q == '0))
-9-:	339	if ((!chk_timeout_q))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	1	-	-	-	-	-	-	Covered	T1,T2,T9
IdleSt	-	0	1	-	-	-	-	-	Covered	T1,T4,T5
IdleSt	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
IntegWaitSt	-	-	-	1	-	-	-	-	Covered	T5,T11,T52
IntegWaitSt	-	-	-	0	1	-	-	-	Covered	T1,T2,T9
IntegWaitSt	-	-	-	0	0	-	-	-	Covered	T1,T2,T9
CnstyWaitSt	-	-	-	-	-	1	-	-	Covered	T5,T11,T6
CnstyWaitSt	-	-	-	-	-	0	1	-	Covered	T1,T4,T5
CnstyWaitSt	-	-	-	-	-	0	0	-	Covered	T1,T4,T5
ErrorSt	-	-	-	-	-	-	-	1	Covered	T2,T63,T103
ErrorSt	-	-	-	-	-	-	-	0	Covered	T5,T11,T6
default	-	-	-	-	-	-	-	-	Covered	T22,T23,T24

	LineNo.	Expression
-1-:	356	if ((((lfsr_err || integ_cnt_err) || cnsty_cnt_err) || lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)))

Branches:

-1-	Status	Tests
1	Covered	T2,T63,T103
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	367	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	370	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_otp_ctrl_lfsr_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ChkPendingKnown_A	464535028	463675205	0	0
ChkTimeoutKnown_A	464535028	463675205	0	0
CnstyChkReqKnown_A	464535028	463675205	0	0
EdnIsWideEnough_A	1143	1143	0	0
EdnReqKnown_A	464535028	463675205	0	0
IntegChkReqKnown_A	464535028	463675205	0	0
u_state_regs_A	464535028	463675205	0	0

ChkPendingKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464535028	463675205	0	0
T1	121959	120684	0	0
T2	13718	13483	0	0
T3	10752	10697	0	0
T4	22136	21994	0	0
T5	52662	51765	0	0
T9	13364	12973	0	0
T10	11684	11498	0	0
T11	61570	60480	0	0
T12	42988	42125	0	0
T13	12013	11845	0	0

ChkTimeoutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464535028	463675205	0	0
T1	121959	120684	0	0
T2	13718	13483	0	0
T3	10752	10697	0	0
T4	22136	21994	0	0
T5	52662	51765	0	0
T9	13364	12973	0	0
T10	11684	11498	0	0
T11	61570	60480	0	0
T12	42988	42125	0	0
T13	12013	11845	0	0

CnstyChkReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464535028	463675205	0	0
T1	121959	120684	0	0
T2	13718	13483	0	0
T3	10752	10697	0	0
T4	22136	21994	0	0
T5	52662	51765	0	0
T9	13364	12973	0	0
T10	11684	11498	0	0
T11	61570	60480	0	0
T12	42988	42125	0	0
T13	12013	11845	0	0

EdnIsWideEnough_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143	1143	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EdnReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464535028	463675205	0	0
T1	121959	120684	0	0
T2	13718	13483	0	0
T3	10752	10697	0	0
T4	22136	21994	0	0
T5	52662	51765	0	0
T9	13364	12973	0	0
T10	11684	11498	0	0
T11	61570	60480	0	0
T12	42988	42125	0	0
T13	12013	11845	0	0

IntegChkReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464535028	463675205	0	0
T1	121959	120684	0	0
T2	13718	13483	0	0
T3	10752	10697	0	0
T4	22136	21994	0	0
T5	52662	51765	0	0
T9	13364	12973	0	0
T10	11684	11498	0	0
T11	61570	60480	0	0
T12	42988	42125	0	0
T13	12013	11845	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464535028	463675205	0	0
T1	121959	120684	0	0
T2	13718	13483	0	0
T3	10752	10697	0	0
T4	22136	21994	0	0
T5	52662	51765	0	0
T9	13364	12973	0	0
T10	11684	11498	0	0
T11	61570	60480	0	0
T12	42988	42125	0	0
T13	12013	11845	0	0