Line Coverage for Module :
prim_double_lfsr
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 102 | 1 | 1 | 100.00 |
CONT_ASSIGN | 103 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_double_lfsr_0/rtl/prim_double_lfsr.sv' or '../src/lowrisc_prim_double_lfsr_0/rtl/prim_double_lfsr.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
102 |
1 |
1 |
103 |
1 |
1 |
Cond Coverage for Module :
prim_double_lfsr
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 103
EXPRESSION (lfsr_state[0] != lfsr_state[1])
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T22,T23,T24 |
Assert Coverage for Module :
prim_double_lfsr
Assertion Details
AssertConnected_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1143 |
1143 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |