Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_buf_err_code_cg_wrap::buf_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_buf_err_code_cg_wrap::buf_err_code_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
83.33	69.44	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

6 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
buf_err_code_cg_wrap[OtpSecret0ErrIdx]	0.00	1	100	1	64	64
buf_err_code_cg_wrap[OtpHwCfg0ErrIdx]	83.33	1	100	1	64	64
buf_err_code_cg_wrap[OtpHwCfg1ErrIdx]	83.33	1	100	1	64	64
buf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx]	83.33	1	100	1	64	64
buf_err_code_cg_wrap[OtpRotCreatorAuthCodesignErrIdx]	83.33	1	100	1	64	64
buf_err_code_cg_wrap[OtpRotCreatorAuthStateErrIdx]	83.33	1	100	1	64	64

---

Group Instance : buf_err_code_cg_wrap[OtpSecret0ErrIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

---

Summary for Group Instance buf_err_code_cg_wrap[OtpSecret0ErrIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	6	0	0.00

Variables for Group Instance buf_err_code_cg_wrap[OtpSecret0ErrIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	6	6	0	0.00	100	1	1	0

---

Group Instance : buf_err_code_cg_wrap[OtpHwCfg0ErrIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

---

Summary for Group Instance buf_err_code_cg_wrap[OtpHwCfg0ErrIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	1	5	83.33

Variables for Group Instance buf_err_code_cg_wrap[OtpHwCfg0ErrIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	6	1	5	83.33	100	1	1	0

---

Group Instance : buf_err_code_cg_wrap[OtpHwCfg1ErrIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

---

Summary for Group Instance buf_err_code_cg_wrap[OtpHwCfg1ErrIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	1	5	83.33

Variables for Group Instance buf_err_code_cg_wrap[OtpHwCfg1ErrIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	6	1	5	83.33	100	1	1	0

---

Group Instance : buf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

---

Summary for Group Instance buf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	1	5	83.33

Variables for Group Instance buf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	6	1	5	83.33	100	1	1	0

---

Group Instance : buf_err_code_cg_wrap[OtpRotCreatorAuthCodesignErrIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

---

Summary for Group Instance buf_err_code_cg_wrap[OtpRotCreatorAuthCodesignErrIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	1	5	83.33

Variables for Group Instance buf_err_code_cg_wrap[OtpRotCreatorAuthCodesignErrIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	6	1	5	83.33	100	1	1	0

---

Group Instance : buf_err_code_cg_wrap[OtpRotCreatorAuthStateErrIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

---

Summary for Group Instance buf_err_code_cg_wrap[OtpRotCreatorAuthStateErrIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	1	5	83.33

Variables for Group Instance buf_err_code_cg_wrap[OtpRotCreatorAuthStateErrIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	6	1	5	83.33	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	6	0	0.00

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
fsm_err	0	1	1
check_fail	0	1	1
ecc_uncorr_err	0	1	1
ecc_corr_err	0	1	1
macro_err	0	1	1
no_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	1	5	83.33

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	116456	1			T2	200		T4	415		T10	549
check_fail	5	1			T67	1		T68	1		T69	1
ecc_uncorr_err	363	1			T84	75		T83	1		T72	1
ecc_corr_err	74	1			T61	37		T66	37		-	-
no_err	159161	1			T1	71		T3	84		T4	58

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	1	5	83.33

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	116594	1			T2	200		T4	415		T10	549
check_fail	4	1			T41	1		T42	1		T43	1
ecc_uncorr_err	233	1			T23	1		T85	3		T62	55
ecc_corr_err	228	1			T39	26		T29	61		T40	70
no_err	158939	1			T1	71		T3	84		T4	58

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	1	5	83.33

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	116744	1			T2	200		T4	415		T8	1
check_fail	13	1			T31	1		T32	1		T33	1
ecc_uncorr_err	75	1			T62	57		T65	1		T117	1
ecc_corr_err	98	1			T28	19		T29	56		T30	12
no_err	159392	1			T1	71		T3	85		T4	58

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	1	5	83.33

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	116687	1			T2	200		T4	415		T8	1
check_fail	34	1			T49	1		T50	1		T51	1
ecc_uncorr_err	97	1			T70	1		T71	1		T86	1
ecc_corr_err	236	1			T46	4		T47	64		T48	111
no_err	159161	1			T1	71		T3	84		T4	58

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	1	5	83.33

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	116752	1			T2	200		T4	415		T10	549
check_fail	22	1			T57	1		T58	1		T59	1
ecc_uncorr_err	44	1			T87	32		T126	1		T127	1
ecc_corr_err	278	1			T54	76		T55	53		T56	22
no_err	159042	1			T1	71		T3	84		T4	58