Design Module List
dashboard | hierarchy | modlist | groups | tests | asserts
Total Module Definition Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.95 93.62 89.06 88.03 84.83 92.19 97.96


Total modules in report: 73
NAME   SCORE   LINE   COND   TOGGLE   FSM   BRANCH   ASSERT   
prim_lfsr 51.81 51.81
prim_packer_fifo 73.33 100.00 93.33 100.00 0.00
prim_arbiter_fixed 74.36 65.65 89.08 88.89 53.85
tlul_lc_gate 82.86 98.04 88.89 85.71 91.67 50.00
  otp_ctrl_part_buf 86.29 83.94 83.20 89.36 77.72 97.22
  prim_subreg_arb 89.36 75.00 93.07 100.00
  otp_ctrl_part_unbuf 90.82 98.49 96.36 64.71 94.57 100.00
otp_ctrl_dai 91.07 94.33 90.59 83.33 87.10 100.00
otp_ctrl 91.48 92.95 86.96 87.22 93.10 97.18
  prim_arbiter_tree 92.91 97.11 80.77 100.00 93.75
  prim_fifo_sync 92.97 100.00 71.88 100.00 100.00
otp_ctrl_kdi 93.11 98.65 94.44 83.33 89.13 100.00
  prim_fifo_sync_cnt 93.67 96.00 85.00 100.00
tlul_adapter_sram 94.22 98.63 85.95 92.31 100.00
  tlul_rsp_intg_gen 95.83 91.67 100.00
prim_sync_reqack 95.83 100.00 83.33 100.00 100.00
prim_secded_inv_72_64_dec 95.89 95.89
otp_ctrl_lfsr_timer 95.93 100.00 88.46 100.00 91.18 100.00
tlul_socket_1n 97.67 98.21 97.73 94.74 100.00
prim_generic_otp 97.81 97.27 96.67 100.00 95.12 100.00
otp_ctrl_scrmbl 97.95 91.67 100.00 100.00 98.08 100.00
prim_edn_req 98.08 100.00 92.31 100.00 100.00
otp_ctrl_core_reg_top 98.61 100.00 94.43 100.00 100.00
prim_generic_ram_1p 98.85 96.55 100.00 100.00
tlul_adapter_reg 98.91 100.00 95.65 100.00 100.00
  prim_count 99.20 99.20
otp_ctrl_prim_reg_top 99.49 100.00 97.98 100.00 100.00
prim_secded_inv_72_64_enc 100.00 100.00
  prim_lc_sync 100.00 100.00 100.00
  prim_lc_sender 100.00 100.00 100.00
tlul_data_integ_dec 100.00 100.00
prim_sparse_fsm_flop 100.00 100.00 100.00
tlul_cmd_intg_chk 100.00 100.00 100.00
prim_alert_sender 100.00 100.00
prim_mubi8_sender 100.00 100.00 100.00 100.00
prim_generic_and2 100.00 100.00
tlul_fifo_sync 100.00 100.00 100.00
tlul_assert 100.00 100.00 100.00 100.00
  prim_onehot_check 100.00 100.00
  prim_subreg 100.00 100.00 100.00 100.00
prim_secded_inv_39_32_dec 100.00 100.00
prim_double_lfsr 100.00 100.00 100.00 100.00
prim_generic_buf 100.00 100.00
prim_intr_hw 100.00 100.00 100.00 100.00 100.00
  prim_present 100.00 100.00 100.00 100.00 100.00
tlul_err_resp 100.00 100.00 100.00 100.00
prim_subreg_ext 100.00 100.00
prim_secded_inv_39_32_enc 100.00 100.00
tlul_sram_byte 100.00 100.00 100.00
otp_ctrl_lci 100.00 100.00 100.00 100.00 100.00 100.00
tlul_err 100.00 100.00 100.00 100.00 100.00
otp_ctrl_core_csr_assert_fpv 100.00 100.00
prim_secded_inv_64_57_enc 100.00 100.00
prim_secded_inv_64_57_dec 100.00 100.00
prim_secded_hamming_22_16_dec 100.00 100.00 100.00
prim_ram_1p_adv 100.00 100.00 100.00 100.00
prim_secded_hamming_22_16_enc 100.00 100.00
prim_sync_reqack_data 100.00 100.00 100.00
prim_generic_flop 100.00 100.00 100.00
  otp_ctrl_ecc_reg 100.00 100.00 100.00 100.00
tlul_data_integ_enc
prim_reg_we_check
prim_otp
prim_sec_anchor_flop
prim_blanker
prim_buf
prim_generic_flop_2sync
prim_flop
prim_flop_2sync
tb
prim_and2
prim_sec_anchor_buf
prim_ram_1p