Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

25562210

1

T1

3524

T2

2014

T3

8519

full_word

8330652

1

T1

715

T2

1666

T3

1579

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	33892562	1			T1	4239		T2	3680		T3	10098
auto[TlIntgErrCmd]	119	1			T288	3		T289	6		T290	3
auto[TlIntgErrData]	82	1			T288	2		T289	6		T290	3
auto[TlIntgErrBoth]	99	1			T288	5		T289	8		T290	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9867615

1

T1

4047

T2

3320

T3

9163

auto[1]

24025247

1

T1

192

T2

360

T3

935

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6265144	1			T1	3418		T2	1813		T3	7962
auto[TlIntgErrNone]	partial	auto[1]	19296795	1			T1	106		T2	201		T3	557
auto[TlIntgErrNone]	full_word	auto[0]	3602337	1			T1	629		T2	1507		T3	1201
auto[TlIntgErrNone]	full_word	auto[1]	4728286	1			T1	86		T2	159		T3	378
auto[TlIntgErrCmd]	partial	auto[0]	49	1			T288	1		T289	3		T358	4
auto[TlIntgErrCmd]	partial	auto[1]	65	1			T288	2		T289	3		T290	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T358	2		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T362	1		T356	2		-	-
auto[TlIntgErrData]	partial	auto[0]	31	1			T288	1		T289	1		T290	2
auto[TlIntgErrData]	partial	auto[1]	39	1			T288	1		T289	4		T290	1
auto[TlIntgErrData]	full_word	auto[0]	6	1			T363	1		T360	1		T364	2
auto[TlIntgErrData]	full_word	auto[1]	6	1			T289	1		T361	1		T365	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T288	1		T289	3		T290	2
auto[TlIntgErrBoth]	partial	auto[1]	46	1			T288	3		T289	4		T290	2
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T288	1		T289	1		T358	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T358	3		T364	1		T366	1