Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.17	94.16	96.15	96.94		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	496338613	8189679	0	0
check_regwen_rd_A	496338613	3229	0	0
check_timeout_rd_A	496338613	2510	0	0
check_trigger_regwen_rd_A	496338613	3268	0	0
consistency_check_period_rd_A	496338613	3340	0	0
creator_sw_cfg_read_lock_rd_A	496338613	2426	0	0
direct_access_address_rd_A	496338613	2271	0	0
direct_access_wdata_0_rd_A	496338613	1445	0	0
direct_access_wdata_1_rd_A	496338613	1621	0	0
integrity_check_period_rd_A	496338613	3319	0	0
intr_enable_rd_A	496338613	3985	0	0
owner_sw_cfg_read_lock_rd_A	496338613	2256	0	0
rot_creator_auth_codesign_read_lock_rd_A	496338613	2555	0	0
rot_creator_auth_state_read_lock_rd_A	496338613	2137	0	0
vendor_test_read_lock_rd_A	496338613	2335	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496338613	8189679	0	0
T5	979469	146417	0	0
T6	0	261713	0	0
T7	0	118843	0	0
T15	154671	0	0	0
T16	0	84011	0	0
T17	0	16936	0	0
T18	0	133740	0	0
T26	33871	0	0	0
T36	0	126157	0	0
T37	0	24605	0	0
T38	53667	0	0	0
T49	11535	0	0	0
T57	12986	0	0	0
T70	17884	0	0	0
T108	25575	0	0	0
T109	81460	0	0	0
T113	38386	0	0	0
T195	0	95043	0	0
T296	0	97173	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496338613	3229	0	0
T5	979469	179	0	0
T15	154671	0	0	0
T16	0	91	0	0
T18	0	86	0	0
T26	33871	0	0	0
T36	0	42	0	0
T37	0	13	0	0
T38	53667	0	0	0
T49	11535	0	0	0
T57	12986	0	0	0
T70	17884	0	0	0
T108	25575	0	0	0
T109	81460	0	0	0
T113	38386	0	0	0
T269	0	51	0	0
T297	0	37	0	0
T298	0	81	0	0
T338	0	50	0	0
T339	0	34	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496338613	2510	0	0
T5	979469	210	0	0
T15	154671	0	0	0
T16	0	135	0	0
T18	0	159	0	0
T26	33871	0	0	0
T36	0	73	0	0
T37	0	48	0	0
T38	53667	0	0	0
T49	11535	0	0	0
T57	12986	0	0	0
T70	17884	0	0	0
T108	25575	0	0	0
T109	81460	0	0	0
T113	38386	0	0	0
T269	0	50	0	0
T297	0	26	0	0
T298	0	100	0	0
T338	0	39	0	0
T339	0	63	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496338613	3268	0	0
T5	979469	176	0	0
T15	154671	0	0	0
T16	0	77	0	0
T18	0	174	0	0
T26	33871	0	0	0
T36	0	44	0	0
T37	0	11	0	0
T38	53667	0	0	0
T49	11535	0	0	0
T57	12986	0	0	0
T70	17884	0	0	0
T108	25575	0	0	0
T109	81460	0	0	0
T113	38386	0	0	0
T269	0	85	0	0
T297	0	39	0	0
T298	0	51	0	0
T338	0	37	0	0
T339	0	76	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496338613	3340	0	0
T5	979469	221	0	0
T15	154671	0	0	0
T16	0	95	0	0
T18	0	170	0	0
T26	33871	0	0	0
T36	0	90	0	0
T37	0	49	0	0
T38	53667	0	0	0
T49	11535	0	0	0
T57	12986	0	0	0
T70	17884	0	0	0
T108	25575	0	0	0
T109	81460	0	0	0
T113	38386	0	0	0
T269	0	73	0	0
T297	0	17	0	0
T298	0	109	0	0
T338	0	23	0	0
T339	0	45	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496338613	2426	0	0
T5	979469	247	0	0
T15	154671	0	0	0
T16	0	133	0	0
T18	0	169	0	0
T26	33871	0	0	0
T36	0	59	0	0
T37	0	56	0	0
T38	53667	0	0	0
T49	11535	0	0	0
T57	12986	0	0	0
T70	17884	0	0	0
T108	25575	0	0	0
T109	81460	0	0	0
T113	38386	0	0	0
T269	0	52	0	0
T297	0	24	0	0
T298	0	79	0	0
T338	0	39	0	0
T339	0	51	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496338613	2271	0	0
T5	979469	211	0	0
T15	154671	0	0	0
T16	0	97	0	0
T18	0	168	0	0
T26	33871	0	0	0
T36	0	47	0	0
T37	0	20	0	0
T38	53667	0	0	0
T49	11535	0	0	0
T57	12986	0	0	0
T70	17884	0	0	0
T108	25575	0	0	0
T109	81460	0	0	0
T113	38386	0	0	0
T269	0	62	0	0
T297	0	19	0	0
T298	0	59	0	0
T338	0	22	0	0
T339	0	47	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496338613	1445	0	0
T5	979469	117	0	0
T15	154671	0	0	0
T16	0	78	0	0
T18	0	124	0	0
T26	33871	0	0	0
T36	0	104	0	0
T37	0	15	0	0
T38	53667	0	0	0
T49	11535	0	0	0
T57	12986	0	0	0
T70	17884	0	0	0
T108	25575	0	0	0
T109	81460	0	0	0
T113	38386	0	0	0
T269	0	56	0	0
T297	0	9	0	0
T298	0	56	0	0
T338	0	21	0	0
T339	0	37	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496338613	1621	0	0
T5	979469	141	0	0
T15	154671	0	0	0
T16	0	86	0	0
T18	0	160	0	0
T26	33871	0	0	0
T36	0	81	0	0
T37	0	37	0	0
T38	53667	0	0	0
T49	11535	0	0	0
T57	12986	0	0	0
T70	17884	0	0	0
T108	25575	0	0	0
T109	81460	0	0	0
T113	38386	0	0	0
T269	0	61	0	0
T297	0	29	0	0
T298	0	50	0	0
T338	0	38	0	0
T339	0	47	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496338613	3319	0	0
T5	979469	156	0	0
T15	154671	0	0	0
T16	0	77	0	0
T18	0	168	0	0
T26	33871	0	0	0
T36	0	94	0	0
T37	0	47	0	0
T38	53667	0	0	0
T49	11535	0	0	0
T57	12986	0	0	0
T70	17884	0	0	0
T108	25575	0	0	0
T109	81460	0	0	0
T113	38386	0	0	0
T269	0	66	0	0
T297	0	26	0	0
T298	0	110	0	0
T338	0	11	0	0
T339	0	39	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496338613	3985	0	0
T5	979469	153	0	0
T15	154671	0	0	0
T16	0	89	0	0
T18	0	164	0	0
T26	33871	0	0	0
T36	0	51	0	0
T37	0	31	0	0
T38	53667	0	0	0
T49	11535	0	0	0
T57	12986	0	0	0
T70	17884	0	0	0
T108	25575	0	0	0
T109	81460	0	0	0
T113	38386	0	0	0
T269	0	71	0	0
T297	0	57	0	0
T298	0	87	0	0
T338	0	40	0	0
T339	0	42	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496338613	2256	0	0
T5	979469	157	0	0
T15	154671	0	0	0
T16	0	122	0	0
T18	0	193	0	0
T26	33871	0	0	0
T36	0	97	0	0
T37	0	31	0	0
T38	53667	0	0	0
T49	11535	0	0	0
T57	12986	0	0	0
T70	17884	0	0	0
T108	25575	0	0	0
T109	81460	0	0	0
T113	38386	0	0	0
T269	0	67	0	0
T297	0	44	0	0
T298	0	55	0	0
T338	0	5	0	0
T339	0	29	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496338613	2555	0	0
T5	979469	173	0	0
T15	154671	0	0	0
T16	0	92	0	0
T18	0	173	0	0
T26	33871	0	0	0
T36	0	60	0	0
T37	0	36	0	0
T38	53667	0	0	0
T49	11535	0	0	0
T57	12986	0	0	0
T70	17884	0	0	0
T108	25575	0	0	0
T109	81460	0	0	0
T113	38386	0	0	0
T269	0	87	0	0
T297	0	35	0	0
T298	0	90	0	0
T338	0	56	0	0
T339	0	72	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496338613	2137	0	0
T5	979469	153	0	0
T15	154671	0	0	0
T16	0	59	0	0
T18	0	151	0	0
T26	33871	0	0	0
T36	0	86	0	0
T37	0	29	0	0
T38	53667	0	0	0
T49	11535	0	0	0
T57	12986	0	0	0
T70	17884	0	0	0
T108	25575	0	0	0
T109	81460	0	0	0
T113	38386	0	0	0
T269	0	72	0	0
T297	0	8	0	0
T298	0	99	0	0
T338	0	45	0	0
T339	0	54	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496338613	2335	0	0
T5	979469	168	0	0
T15	154671	0	0	0
T16	0	113	0	0
T18	0	183	0	0
T26	33871	0	0	0
T36	0	76	0	0
T37	0	4	0	0
T38	53667	0	0	0
T49	11535	0	0	0
T57	12986	0	0	0
T70	17884	0	0	0
T108	25575	0	0	0
T109	81460	0	0	0
T113	38386	0	0	0
T269	0	48	0	0
T297	0	20	0	0
T298	0	72	0	0
T338	0	34	0	0
T339	0	21	0	0