Unified Coverage Report :: Module :: prim_lc_sender

Module : prim_lc_sender

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_lc_sender_otp_broadcast_valid	100.00	100.00
tb.dut.u_prim_lc_sender_test_tokens_valid	100.00	100.00				100.00
tb.dut.u_prim_lc_sender_rma_token_valid	100.00	100.00				100.00
tb.dut.u_prim_lc_sender_secrets_valid	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_lc_sender_otp_broadcast_valid

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.17	94.16	96.15	96.94		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_lc_sender_test_tokens_valid

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.17	94.16	96.15	96.94		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_no_flops.gen_bits[0].u_prim_buf	100.00	100.00
gen_no_flops.gen_bits[1].u_prim_buf	100.00	100.00
gen_no_flops.gen_bits[2].u_prim_buf	100.00	100.00
gen_no_flops.gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_prim_lc_sender_rma_token_valid

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.17	94.16	96.15	96.94		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_no_flops.gen_bits[0].u_prim_buf	100.00	100.00
gen_no_flops.gen_bits[1].u_prim_buf	100.00	100.00
gen_no_flops.gen_bits[2].u_prim_buf	100.00	100.00
gen_no_flops.gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_prim_lc_sender_secrets_valid

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.17	94.16	96.15	96.94		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_no_flops.gen_bits[0].u_prim_buf	100.00	100.00
gen_no_flops.gen_bits[1].u_prim_buf	100.00	100.00
gen_no_flops.gen_bits[2].u_prim_buf	100.00	100.00
gen_no_flops.gen_bits[3].u_prim_buf	100.00	100.00

Line Coverage for Module : prim_lc_sender ( parameter AsyncOn=1,ResetValueIsOn=0,ResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_prim_lc_sender_otp_broadcast_valid

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	66	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' or '../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
32	1	1
66	1	1

---

Line Coverage for Module : prim_lc_sender ( parameter AsyncOn=0,ResetValueIsOn=0,ResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_prim_lc_sender_test_tokens_valid

SCORE	LINE
100.00	100.00

tb.dut.u_prim_lc_sender_rma_token_valid

SCORE	LINE
100.00	100.00

tb.dut.u_prim_lc_sender_secrets_valid

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	32	1	1	100.00
ALWAYS	58	3	3	100.00
CONT_ASSIGN	66	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' or '../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
32	1	1
58	1	1
59	1	1
61	1	1
66	1	1

---

Branch Coverage for Module : prim_lc_sender

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	58	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' or '../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	58	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_prim_lc_sender_otp_broadcast_valid

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	66	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' or '../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
32	1	1
66	1	1

Line Coverage for Instance : tb.dut.u_prim_lc_sender_test_tokens_valid

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	32	1	1	100.00
ALWAYS	58	3	3	100.00
CONT_ASSIGN	66	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' or '../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
32	1	1
58	1	1
59	1	1
61	1	1
66	1	1

---

Branch Coverage for Instance : tb.dut.u_prim_lc_sender_test_tokens_valid

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	58	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' or '../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	58	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_prim_lc_sender_rma_token_valid

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	32	1	1	100.00
ALWAYS	58	3	3	100.00
CONT_ASSIGN	66	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' or '../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
32	1	1
58	1	1
59	1	1
61	1	1
66	1	1

---

Branch Coverage for Instance : tb.dut.u_prim_lc_sender_rma_token_valid

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	58	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' or '../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	58	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_prim_lc_sender_secrets_valid

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	32	1	1	100.00
ALWAYS	58	3	3	100.00
CONT_ASSIGN	66	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' or '../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
32	1	1
58	1	1
59	1	1
61	1	1
66	1	1

---

Branch Coverage for Instance : tb.dut.u_prim_lc_sender_secrets_valid

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	58	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' or '../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	58	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3