Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.19	94.16	96.15	97.04		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	472173590	8155310	0	0
check_regwen_rd_A	472173590	3461	0	0
check_timeout_rd_A	472173590	2509	0	0
check_trigger_regwen_rd_A	472173590	3424	0	0
consistency_check_period_rd_A	472173590	3817	0	0
creator_sw_cfg_read_lock_rd_A	472173590	2743	0	0
direct_access_address_rd_A	472173590	2262	0	0
direct_access_wdata_0_rd_A	472173590	1384	0	0
direct_access_wdata_1_rd_A	472173590	1395	0	0
integrity_check_period_rd_A	472173590	3605	0	0
intr_enable_rd_A	472173590	4608	0	0
owner_sw_cfg_read_lock_rd_A	472173590	2276	0	0
rot_creator_auth_codesign_read_lock_rd_A	472173590	2579	0	0
rot_creator_auth_state_read_lock_rd_A	472173590	2416	0	0
vendor_test_read_lock_rd_A	472173590	2159	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	472173590	8155310	0	0
T1	794146	25519	0	0
T2	10971	0	0	0
T3	16710	0	0	0
T4	48462	0	0	0
T5	25453	0	0	0
T6	16025	0	0	0
T7	0	156048	0	0
T8	0	165780	0	0
T9	0	85812	0	0
T13	43153	0	0	0
T14	10053	0	0	0
T15	15270	0	0	0
T16	27925	0	0	0
T23	0	86795	0	0
T32	0	69168	0	0
T33	0	54219	0	0
T191	0	35518	0	0
T215	0	81824	0	0
T274	0	117953	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	472173590	3461	0	0
T9	0	112	0	0
T23	470699	90	0	0
T32	255152	0	0	0
T39	10086	0	0	0
T43	14558	0	0	0
T107	14349	0	0	0
T108	21112	0	0	0
T109	54671	0	0	0
T110	21137	0	0	0
T145	15194	0	0	0
T165	14019	0	0	0
T191	0	43	0	0
T211	0	40	0	0
T285	0	84	0	0
T286	0	77	0	0
T338	0	24	0	0
T339	0	123	0	0
T340	0	89	0	0
T341	0	68	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	472173590	2509	0	0
T9	0	112	0	0
T23	470699	107	0	0
T32	255152	0	0	0
T39	10086	0	0	0
T43	14558	0	0	0
T107	14349	0	0	0
T108	21112	0	0	0
T109	54671	0	0	0
T110	21137	0	0	0
T145	15194	0	0	0
T165	14019	0	0	0
T191	0	23	0	0
T211	0	32	0	0
T285	0	90	0	0
T286	0	58	0	0
T338	0	35	0	0
T339	0	137	0	0
T340	0	41	0	0
T341	0	34	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	472173590	3424	0	0
T9	0	121	0	0
T23	470699	100	0	0
T32	255152	0	0	0
T39	10086	0	0	0
T43	14558	0	0	0
T107	14349	0	0	0
T108	21112	0	0	0
T109	54671	0	0	0
T110	21137	0	0	0
T145	15194	0	0	0
T165	14019	0	0	0
T191	0	56	0	0
T211	0	13	0	0
T285	0	74	0	0
T286	0	67	0	0
T338	0	16	0	0
T339	0	121	0	0
T340	0	49	0	0
T341	0	39	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	472173590	3817	0	0
T9	0	146	0	0
T23	470699	96	0	0
T32	255152	0	0	0
T39	10086	0	0	0
T43	14558	0	0	0
T107	14349	0	0	0
T108	21112	0	0	0
T109	54671	0	0	0
T110	21137	0	0	0
T145	15194	0	0	0
T165	14019	0	0	0
T191	0	72	0	0
T211	0	18	0	0
T285	0	134	0	0
T286	0	76	0	0
T338	0	8	0	0
T339	0	119	0	0
T340	0	120	0	0
T341	0	63	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	472173590	2743	0	0
T9	0	154	0	0
T23	470699	93	0	0
T32	255152	0	0	0
T39	10086	0	0	0
T43	14558	0	0	0
T107	14349	0	0	0
T108	21112	0	0	0
T109	54671	0	0	0
T110	21137	0	0	0
T145	15194	0	0	0
T165	14019	0	0	0
T191	0	74	0	0
T211	0	22	0	0
T285	0	89	0	0
T286	0	91	0	0
T338	0	14	0	0
T339	0	120	0	0
T340	0	75	0	0
T341	0	54	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	472173590	2262	0	0
T9	0	144	0	0
T23	470699	102	0	0
T32	255152	0	0	0
T39	10086	0	0	0
T43	14558	0	0	0
T107	14349	0	0	0
T108	21112	0	0	0
T109	54671	0	0	0
T110	21137	0	0	0
T145	15194	0	0	0
T165	14019	0	0	0
T191	0	26	0	0
T211	0	68	0	0
T285	0	101	0	0
T286	0	65	0	0
T338	0	15	0	0
T339	0	139	0	0
T340	0	76	0	0
T341	0	69	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	472173590	1384	0	0
T9	0	111	0	0
T23	470699	56	0	0
T32	255152	0	0	0
T39	10086	0	0	0
T43	14558	0	0	0
T107	14349	0	0	0
T108	21112	0	0	0
T109	54671	0	0	0
T110	21137	0	0	0
T145	15194	0	0	0
T165	14019	0	0	0
T191	0	52	0	0
T211	0	9	0	0
T285	0	68	0	0
T286	0	25	0	0
T338	0	9	0	0
T339	0	126	0	0
T340	0	27	0	0
T341	0	33	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	472173590	1395	0	0
T9	0	104	0	0
T23	470699	135	0	0
T32	255152	0	0	0
T39	10086	0	0	0
T43	14558	0	0	0
T107	14349	0	0	0
T108	21112	0	0	0
T109	54671	0	0	0
T110	21137	0	0	0
T145	15194	0	0	0
T165	14019	0	0	0
T191	0	47	0	0
T211	0	25	0	0
T285	0	84	0	0
T286	0	31	0	0
T338	0	23	0	0
T339	0	68	0	0
T340	0	18	0	0
T341	0	35	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	472173590	3605	0	0
T9	0	157	0	0
T23	470699	55	0	0
T32	255152	0	0	0
T39	10086	0	0	0
T43	14558	0	0	0
T107	14349	0	0	0
T108	21112	0	0	0
T109	54671	0	0	0
T110	21137	0	0	0
T145	15194	0	0	0
T165	14019	0	0	0
T191	0	86	0	0
T211	0	28	0	0
T285	0	99	0	0
T286	0	89	0	0
T338	0	35	0	0
T339	0	112	0	0
T340	0	34	0	0
T341	0	61	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	472173590	4608	0	0
T9	0	172	0	0
T23	470699	75	0	0
T32	255152	0	0	0
T34	0	57	0	0
T39	10086	0	0	0
T43	14558	0	0	0
T107	14349	0	0	0
T108	21112	0	0	0
T109	54671	0	0	0
T110	21137	0	0	0
T116	0	9	0	0
T145	15194	0	0	0
T165	14019	0	0	0
T191	0	61	0	0
T211	0	52	0	0
T285	0	105	0	0
T286	0	92	0	0
T338	0	18	0	0
T339	0	111	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	472173590	2276	0	0
T9	0	99	0	0
T23	470699	117	0	0
T32	255152	0	0	0
T39	10086	0	0	0
T43	14558	0	0	0
T107	14349	0	0	0
T108	21112	0	0	0
T109	54671	0	0	0
T110	21137	0	0	0
T145	15194	0	0	0
T165	14019	0	0	0
T191	0	36	0	0
T211	0	60	0	0
T285	0	70	0	0
T286	0	75	0	0
T338	0	22	0	0
T339	0	124	0	0
T340	0	74	0	0
T341	0	63	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	472173590	2579	0	0
T9	0	108	0	0
T23	470699	145	0	0
T32	255152	0	0	0
T39	10086	0	0	0
T43	14558	0	0	0
T107	14349	0	0	0
T108	21112	0	0	0
T109	54671	0	0	0
T110	21137	0	0	0
T145	15194	0	0	0
T165	14019	0	0	0
T191	0	81	0	0
T211	0	28	0	0
T285	0	75	0	0
T286	0	86	0	0
T338	0	23	0	0
T339	0	116	0	0
T340	0	73	0	0
T341	0	81	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	472173590	2416	0	0
T9	0	99	0	0
T23	470699	100	0	0
T32	255152	0	0	0
T39	10086	0	0	0
T43	14558	0	0	0
T107	14349	0	0	0
T108	21112	0	0	0
T109	54671	0	0	0
T110	21137	0	0	0
T145	15194	0	0	0
T165	14019	0	0	0
T191	0	78	0	0
T211	0	57	0	0
T285	0	111	0	0
T286	0	86	0	0
T338	0	22	0	0
T339	0	99	0	0
T340	0	46	0	0
T341	0	28	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	472173590	2159	0	0
T9	0	78	0	0
T23	470699	86	0	0
T32	255152	0	0	0
T39	10086	0	0	0
T43	14558	0	0	0
T107	14349	0	0	0
T108	21112	0	0	0
T109	54671	0	0	0
T110	21137	0	0	0
T145	15194	0	0	0
T165	14019	0	0	0
T191	0	55	0	0
T211	0	53	0	0
T285	0	73	0	0
T286	0	86	0	0
T338	0	32	0	0
T339	0	81	0	0
T340	0	99	0	0
T341	0	41	0	0